default search action
VTS 2008: San Diego, CA, USA
- 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA. IEEE Computer Society 2008, ISBN 978-0-7695-3123-6
- Qingqi Dou, Jacob A. Abraham:
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. 3-8 - Muhammad Mudassar Nisar, Abhijit Chatterjee:
Test Enabled Process Tuning for Adaptive Baseband OFDM Processor. 9-16 - Dongwoo Hong, Kwang-Ting (Tim) Cheng
:
Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links. 17-22 - François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh:
How Many Test Patterns are Useless? 23-28 - Emil Gizdarski:
Constructing Augmented Multimode Compactors. 29-34 - Ritesh Garg, Richard Putman, Nur A. Touba:
Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. 35-42 - Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey:
Inconsistent Fail due to Limited Tester Timing Accuracy. 47-52 - Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji:
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. 53-58 - Zhaoliang Pan, Melvin A. Breuer:
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). 59-66 - King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman:
Diagnosis of Scan Clock Failures. 67-72 - Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang:
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. 73-78 - Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. 79-84 - Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. 89-94 - Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. 95-100 - Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. 101-106 - Tze Wee Chen, Kyunglok Kim, Young Moon Kim, Subhasish Mitra:
Gate-Oxide Early Life Failure Prediction. 111-118 - Daniel Arumí
Full Open Defects in Nanometric CMOS. 119-124 - Uranmandakh Amgalan, Christian Hachmann
Signature Rollback - A Technique for Testing Robust Circuits. 125-130 - Anshuman Chandra, Rohit Kapur:
Bounded Adjacent Fill for Low Capture Power Scan Testing. 131-138 - Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
Reducing Scan Shift Power at RTL. 139-146 - Yu-Ze Wu, Mango Chia-Tso Chao:
Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. 147-154 - Apurva Mishra, Mani Soma:
A Time-Domain Method for Pseudo-Spectral Characterization. 163-168 - Chen-Wei Lin, Jiun-Lang Huang:
A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. 169-174 - Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhijit Chatterjee:
Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise. 175-180 - Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker
Automatic Test Pattern Generation for Interconnect Open Defects. 181-186 - Stelios Neophytou
On the Relaxation of n-detect Test Sets. 187-192 - Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. 193-198 - Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. 203-208 - Erdem Serkan Erdogan, Sule Ozev:
Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers. 209-214 - Vishwanath Natarajan, Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee:
ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends. 215-220 - Irith Pomeranz, Sudhakar M. Reddy:
Synthesis for Broadside Testability of Transition Faults. 221-226 - Jeremy Lee, Mohammad Tehranipoor:
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation. 227-232 - Mahmut Yilmaz, Krishnendu Chakrabarty
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. 233-239 - Zheng Wang, D. M. H. Walker:
Dynamic Compaction for High Quality Delay Test. 243-248 - Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang:
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. 249-254 - Jaekwang Lee, Intaik Park, Edward J. McCluskey:
Error Sequence Analysis. 255-260 - Yao-Hsin Chou, Sy-Yen Kuo
QBIST: Quantum Built-in Self-Test for any Boolean Circuit. 261-266 - James Dardig, Haralampos-G. D. Stratigopoulos, Eric Stern, Mark A. Reed
A Statistical Approach to Characterizing and Testing Functionalized Nanowires. 267-274 - Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi:
A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies. 275-282 - Byoungho Kim, Nash Khouzam, Jacob A. Abraham:
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. 293-298 - Sounil Biswas, R. D. (Shawn) Blanton:
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. 299-308 - Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Parallel Loopback Test of Mixed-Signal Circuits. 309-316 - Irith Pomeranz, Sudhakar M. Reddy:
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. 317-322 - Manoj Kumar Goparaju, Spyros Tragoudas:
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. 323-328 - Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal:
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. 329-335 - Desta Tadesse, R. Iris Bahar
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. 339-344 - Joon-Sung Yang, Nur A. Touba:
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. 345-351 - Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu:
A General Failure Candidate Ranking Framework for Silicon Debug. 352-358 - Carlos Arthur Lang Lisbôa, Costas Argyrides, Dhiraj K. Pradhan, Luigi Carro
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. 363-370 - Michael Nicolaidis, Renaud Perez, Dan Alexandrescu:
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors. 371-376 - Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu:
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. 377-382 - Minjin Zhang, Huawei Li
Multiple Coupling Effects Oriented Path Delay Test Generation. 383-388 - Kyriakos Christou, Maria K. Michael, Paolo Bernardi
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. 389-394 - I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty:
An Industrial Case Study of Sticky Path-Delay Faults. 395-402
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-27 20:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: