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David Trilla
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2020 – today
- 2024
- [c12]Alper Buyuktosunoglu, David Trilla, Bülent Abali, Deanna Postles Dunn Berger, Craig R. Walters, Jang-Soo Lee:
Enterprise-Class Cache Compression Design. HPCA 2024: 996-1011 - [c11]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - 2021
- [j2]David Trilla
, Carles Hernández
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. IEEE Trans. Sustain. Comput. 6(3): 522-530 (2021) - [c10]Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide
SafeSU: an Extended Statistics Unit for Multicore Timing Interference. ETS 2021: 1-4 - [c9]Francisco Bas, Sergi Alcaide
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping. IOLTS 2021: 1-7 - [c8]Oriol Sala, Sergi Alcaide
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. IOLTS 2021: 1-7 - [c7]David Trilla, John-David Wellman, Alper Buyuktosunoglu, Pradip Bose:
NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators. MICRO 2021: 507-521 - 2020
- [b1]David Trilla:
Non-functional considerations of time-randomized processor architectures. Polytechnic University of Catalonia, Spain, 2020
2010 – 2019
- 2019
- [j1]David Trilla
Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors. IEEE Des. Test 36(6): 39-47 (2019) - [c6]David Trilla, Carles Hernández
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. DSD 2019: 538-545 - [c5]David Trilla, Carles Hernández
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. DSD 2019: 601-605 - 2018
- [c4]David Trilla, Carles Hernández
Cache side-channel attacks and time-predictability in high-performance critical real-time systems. DAC 2018: 98:1-98:6 - 2017
- [c3]David Trilla, Carles Hernández
Modelling bus contention during system early design stages. SIES 2017: 1-8 - 2016
- [c2]David Trilla
Resilient random modulo cache memories for probabilistically-analyzable real-time systems. IOLTS 2016: 27-32 - [c1]David Trilla
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. RTAS 2016: 305-316
Coauthor Index
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