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18th IOLTS 2012: Sitges, Spain
- 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2082-5
SEU Tolerance
- Norhuzaimin Julai, Alexandre Yakovlev
, Alexandre V. Bystrov
Error detection and correction of single event upset (SEU) tolerant latch. 1-6 - Yang Lin, Mark Zwolinski
SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems. 7-12 - Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU tolerant robust memory cell design. 13-18 - Sujan Pandey, Klaas Brink:
Soft-errors resilient logic optimization for low power. 19-24
Reconfigurable Logic
- Cinzia Bernardeschi
SEU-X: A SEu un-excitability prover for SRAM-FPGAs. 25-30 - Arwa Ben Dhia, Lirida A. B. Naviner
Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster. 31-36 - Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Transparent structural online test for reconfigurable systems. 37-42
Radiation Experiments and Analysis
- Miguel Vilchis, Ramnath Venkatraman, Enrico Costenaro, Dan Alexandrescu:
A real-case application of a synergetic design-flow-oriented SER analysis. 43-48 - Eishi Ibe, Tadanobu Toba, Ken-ichi Shimbo, Hitoshi Taniguchi:
Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons. 49-54 - Paolo Rech
Neutron radiation test of graphic processing units. 55-60
Circuit Degradation
- Jackson Pachito, Celestino V. Martins, Jorge Semião
The influence of clock-gating on NBTI-induced delay degradation. 61-66 - Clement Bertolini, Olivier Héron, Nicolas Ventroux, François Marc:
Relation between HCI-induced performance degradation and applications in a RISC processor. 67-72 - Glenn H. Chapman, Israel Koren, Zahava Koren:
Do more camera pixels result in a better picture? 73-78
Memories and 3D Integration
- Pedro Reviriego, Alfonso Sánchez-Macián
Low Power embedded DRAM caches using BCH code partitioning. 79-83 - Michele Riga, Ernesto Sánchez, Matteo Sonza Reorda
On the functional test of L2 caches. 84-90 - Michael Nicolaidis, Vladimir Pasca, Lorena Anghel
Through-silicon-via built-in self-repair for aggressive 3D integration. 91-96
Miscellaneous
- Ozgur Sinanoglu
Test access mechanism for chips with spare identical cores. 97-102 - Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Dan Alexandrescu, Enrico Costenaro:
RIIF - Reliability information interchange format. 103-108 - Josep Altet
On line monitoring of RF power amplifiers with embedded temperature sensors. 109-113
Posters
- Eberhard Böhl, Markus Ihle:
A fault attack robust TRNG. 114-117 - Atieh Lotfi, Arash Bayat, Saeed Safari
Architectural vulnerability aware checkpoint placement in a multicore processor. 118-120 - Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. 121-122 - Mikhail Baklashov:
Event-driven on-line co-simulation with fault diagnostic. 123-126 - Julian Wolf, Bernhard Fechner
Fault coverage of a timing and control flow checker for hard real-time systems. 127-129 - Zhen Gao, Wenhui Yang, Xiang Chen, Ming Zhao, Jing Wang:
Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design. 130-133 - Ariel Burg, Osnat Keren:
Functional level embedded self testing for Walsh transform based adaptive hardware. 134-135 - Francisco R. Fernandes, Ricardo J. Machado
Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports. 136-137 - Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Neutron-induced soft error rate estimation for SRAM using PHITS. 138-141 - Sabyasachi Deyati, Aritra Banerjee, Abhijit Chatterjee:
Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis. 142-145 - Zhen Wang, Mark G. Karpovsky:
Reliable and secure memories based on algebraic manipulation correction codes. 146-149
Secure Hardware
- Victor Tomashevich, Sudarshan Srinivasan, Fabian Foerg, Ilia Polian:
Cross-level protection of circuits against faults and malicious attacks. 150-155 - Yaara Neumeier
Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices. 156-161 - Ameya Chaudhari, Jacob A. Abraham:
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors. 162-167
Future Reliability Solutions: New Applications and New Devices
- Rakesh Kumar:
Algorithmic techniques for robust applications. 168 - Esteve Amat
Analysis of FinFET technology on memories. 169
Soft Errors Analysis and Tolerance
- Liang Chen, Mehdi Baradaran Tahoori:
An efficient probability framework for error propagation and correlation estimation. 170-175 - Antonio Sanchez-Clemente, Luis Entrena
Logic masking for SET Mitigation Using Approximate Logic Circuits. 176-181 - Dan Alexandrescu, Enrico Costenaro:
Towards optimized functional evaluation of SEE-induced failures in complex designs. 182-187 - Celia López-Ongil
SEU sensitivity of robust communication protocols. 188-193
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