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FPT 2020: Maui, HI, USA
- International Conference on Field-Programmable Technology, (IC)FPT 2020, Maui, HI, USA, December 9-11, 2020. IEEE 2020, ISBN 978-1-6654-2302-1
- Stefano Ribes, Pedro Trancoso
, Ioannis Sourdis, Christos-Savvas Bouganis:
Mapping Multiple LSTM models on FPGAs. 1-9 - Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer:
Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. 10-19 - Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. 20-28 - Yasuhiro Nitta, Hideki Takase:
An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing Elements. 29-34 - Yue Li, Wei Cao, Xuegong Zhou, Lingli Wang:
A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications. 35-38 - Shuanglong Liu, Wayne Luk:
Optimizing Fully Spectral Convolutional Neural Networks on FPGA. 39-47 - Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott:
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. 48-55 - Mathew Hall, Vaughn Betz:
From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware Generation. 56-65 - Shikha Goel, Rajesh Kedia, M. Balakrishnan, Rijurekha Sen:
INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs. 66-71 - Arish Sateesan
DASH: Design Automation for Synthesis and Hardware Generation for CNN. 72-75 - Hongxin Kong, Lang Feng, Chunhua Deng, Bo Yuan, Jiang Hu:
How Much Does Regularity Help FPGA Placement? 76-84 - Mohamed A. Elgammal, Kevin E. Murray, Vaughn Betz:
Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves. 85-93 - Behnam Khaleghi, Sahand Salamat, Tajana Simunic Rosing:
Revisiting FPGA Routing under Varying Operating Conditions. 94-102 - Andrew Boutros, Mathew Hall, Nicolas Papernot, Vaughn Betz:
Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs. 103-111 - Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb:
Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud. 112-119 - Luke Beckwith, William Diehl:
New Directions for NewHope: Improving Performance of Post-Quantum Cryptography through Algorithm-level Pipelining. 120-128 - Gongjin Sun, Sang-Woo Jun:
Bandwidth Efficient Near-Storage Accelerator for High-Dimensional Similarity Search. 129-138 - Alec Lu, Zhenman Fang, Nazanin Farahpour, Lesley Shannon:
CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs. 139-147 - Yang Yang, Sanmukh R. Kuppannagari
A High Throughput Parallel Hash Table Accelerator on HBM-enabled FPGAs. 148-153 - Shanquan Tian, Andrew Krzywosz, Ilias Giechaskiel, Jakub Szefer:
Cloud FPGA Security with RO-Based Primitives. 154-158 - Pouya Haghi
A Reconfigurable Compute-in-the-Network FPGA Assistant for High-Level Collective Support with Distributed Matrix Multiply Case Study. 159-164 - Johannes Pfau
Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology. 165-173 - Kaichuang Shi
GIB: A Novel Unidirectional Interconnection Architecture for FPGA. 174-181 - Pepijn de Vos, Michael Kirchhoff, Daniel Ziener
A Complete Open Source Design Flow for Gowin FPGAs. 182-189 - Nguyen Dao, Andrew Attwood, Bea Healy, Dirk Koch:
FlexBex: A RISC-V with a Reconfigurable Instruction Extension. 190-195 - Yuanlong Xiao
Fast Linking of Separately-Compiled FPGA Blocks without a NoC. 196-205 - Sameh Attia
StateReveal: Enabling Checkpointing of FPGA Designs with Buried State. 206-214 - Alex R. Bucknall, Shanker Shreejith
Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+. 215-220 - Khoa Dang Pham, Dirk Koch, Anuj Vaishnav, Konstantinos Georgopoulos, Pavlos Malakonakis, Aggelos Ioannou
Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation. 221-226 - Tiago Santos
Automatic Selection and Insertion of HLS Directives Via a Source-to-Source Compiler. 227-232 - Westerley Carvalho, Michael Canesche, Lucas Reis, Frank Sill Torres, Lucas B. da Silva, Peter Jamieson, José Augusto Miranda Nacif, Ricardo S. Ferreira:
A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators. 233-236 - Ce Guo, Wayne Luk:
Quantisation-aware Dimensionality Reduction. 237-240 - Niklas Schelten
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators. 241-249 - Sultan Alqahtani, Yiqun Zhu, Qizhi Shi, Xiaolin Meng
Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion. 250-255 - Ho-Cheung Ng, Shuanglong Liu, Izaak Coleman
Acceleration of Short Read Alignment with Runtime Reconfiguration. 256-262 - Xuzhi Zhang, Russell Tessier:
Service Chaining for Heterogeneous Middleboxes. 263-267 - Christian Lienen, Marco Platzner, Bernhard Rinner:
ReconROS: Flexible Hardware Acceleration for ROS2 Applications. 268-276 - Haowen Chen, Feiteng Li, Zhuo Zhang:
A Bucket-Stream rBRIEF Extraction Architecture for SLAM Applications on Embedded Platforms. 277-280 - Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA. 281-286 - Martin Koppehel, Thilo Pionteck:
Ultra-Low-Latency Video Encoding on Heterogenous Hardware Platforms. 287 - Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. 288-289 - Hankun Lv, Yuchen Ren, Yunhui Qiu, Wenbo Yin, Lingli Wang:
High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator. 290-291 - Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems. 292-293 - Naoto Soga, Hiroki Nakahara:
Design Method for an LUT Network-Based CNN with a Sparse Local Convolution. 294-295 - Haoyan Liu, Atiyehsadat Panahi, David Andrews
An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks. 296-297 - Danielle Tchuinkou Kwadjo, Joel Mandebi Mbongue, Christophe Bobda:
Performance Exploration on Pre-implemented CNN Hardware Accelerator on FPGA. 298-299 - Tim Todman, David B. Thomas
Exploring performance enhancement of event-driven processor networks. 300 - Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk:
Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. 301
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