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Hongxiang Fan
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2020 – today
- 2024
- [j12]Zhiqiang Que
, Minghao Zhang, Hongxiang Fan, He Li
Low Latency Variational Autoencoder on FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(2): 323-333 (2024) - [j11]Zhiqiang Que
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics. ACM Trans. Embed. Comput. Syst. 23(2): 17:1-17:28 (2024) - [j10]Shuanglong Liu
Design of Fully Spectral CNNs for Efficient FPGA-Based Acceleration. IEEE Trans. Neural Networks Learn. Syst. 35(6): 8111-8123 (2024) - [c29]Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk:
Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network. ASAP 2024: 107-115 - [c28]Zehuan Zhang
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. DAC 2024: 301:1-301:6 - [c27]Wanru Zhao, Yihong Chen, Royson Lee, Xinchi Qiu, Yan Gao, Hongxiang Fan, Nicholas Donald Lane:
Breaking Physical and Linguistic Borders: Multilingual Federated Prompt Tuning for Low-Resource Languages. ICLR 2024 - [c26]Yuan Li, Jianbin Zhu, Yao Fu, Yu Lei, Toshio Nagata, Ryan Braidwood, Haohuan Fu, Juepeng Zheng, Wayne Luk, Hongxiang Fan:
Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶. ISCA 2024: 863-875 - [i15]Martin Ferianc, Hongxiang Fan, Miguel Rodrigues:
SAE: Single Architecture Ensemble Neural Networks. CoRR abs/2402.06580 (2024) - [i14]Hao Mark Chen, Wayne Luk, Ka Fai Cedric Yiu, Rui Li, Konstantin Mishchenko, Stylianos I. Venieris, Hongxiang Fan:
Hardware-Aware Parallel Prompt Decoding for Memory-Efficient Acceleration of LLM Inference. CoRR abs/2405.18628 (2024) - [i13]Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan:
Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA. CoRR abs/2406.14593 (2024) - [i12]Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk:
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. CoRR abs/2406.16198 (2024) - [i11]Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk:
Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network. CoRR abs/2407.05521 (2024) - [i10]Hao Mark Chen, Fuwen Tan, Alexandros Kouris, Royson Lee, Hongxiang Fan, Stylianos I. Venieris:
Progressive Mixed-Precision Decoding for Efficient LLM Inference. CoRR abs/2410.13461 (2024) - 2023
- [j9]He Li
Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic. IEEE Trans. Computers 72(6): 1822-1829 (2023) - [j8]Hongxiang Fan
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. 34(8): 4473-4487 (2023) - [j7]Zhiqiang Que
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(1): 4:1-4:26 (2023) - [c25]Hongxiang Fan, Mark Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. DAC 2023: 1-6 - [c24]Hongxiang Fan
Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads. MICRO 2023: 353-366 - [i9]Hongxiang Fan, Hao Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk:
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. CoRR abs/2308.06849 (2023) - [i8]Hongxiang Fan, Stylianos I. Venieris, Alexandros Kouris, Nicholas D. Lane:
Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads. CoRR abs/2310.11096 (2023) - 2022
- [j6]Hongxiang Fan
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5343-5356 (2022) - [j5]Shuanglong Liu
Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs. IEEE Trans. Neural Networks Learn. Syst. 33(8): 3974-3987 (2022) - [j4]Hongxiang Fan
Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations. IEEE Trans. Parallel Distributed Syst. 33(12): 3387-3399 (2022) - [j3]Zhiqiang Que
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 227-237 (2022) - [c23]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC 2022: 250-255 - [c22]Hongxiang Fan, Ce Guo, Wayne Luk:
Optimizing quantum circuit placement via machine learning. DAC 2022: 19-24 - [c21]Hongxiang Fan, Martin Ferianc
Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations. DAC 2022: 325-330 - [c20]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. FPL 2022: 327-333 - [c19]Ziwei Wang, Zhiqiang Que, Wayne Luk, Hongxiang Fan:
Customizable FPGA-based Accelerator for Binarized Graph Neural Networks. ISCAS 2022: 1968-1972 - [c18]Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. MICRO 2022: 599-615 - [i7]Hongxiang Fan, Thomas Chun-Pong Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. CoRR abs/2209.09570 (2022) - [i6]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors. CoRR abs/2209.14065 (2022) - 2021
- [c17]Hongxiang Fan, Martin Ferianc
High-Performance FPGA-based Accelerator for Bayesian Neural Networks. DAC 2021: 1063-1068 - [c16]Shuanglong Liu, Hongxiang Fan, Wayne Luk:
Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA. DATE 2021: 1530-1535 - [c15]Martin Ferianc
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator. FPT 2021: 1-10 - [c14]He Li, Hongxiang Fan, Jiawei Liang
Quantum Most-Significant Digit-First Addition. IGSC (Workshops) 2021: 1-8 - [c13]Martin Ferianc
ComBiNet: Compact Convolutional Bayesian Neural Network for Image Segmentation. ICANN (3) 2021: 483-494 - [i5]Martin Ferianc, Divyansh Manocha, Hongxiang Fan, Miguel Rodrigues:
ComBiNet: Compact Convolutional Bayesian Neural Network for Image Segmentation. CoRR abs/2104.06957 (2021) - [i4]Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk:
High-Performance FPGA-based Accelerator for Bayesian Neural Networks. CoRR abs/2105.09163 (2021) - [i3]Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues:
High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks. CoRR abs/2106.06048 (2021) - [i2]Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk:
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR abs/2111.12787 (2021) - 2020
- [j2]Zhiqiang Que
Mapping Large LSTMs to FPGAs with Weight Reuse. J. Signal Process. Syst. 92(9): 965-979 (2020) - [c12]Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk:
Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. ARC 2020: 3-13 - [c11]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. FCCM 2020: 10-18 - [c10]Hongxiang Fan, Martin Ferianc
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD 2020: 465-468 - [c9]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT 2020: 20-28 - [i1]Martin Ferianc, Hongxiang Fan, Miguel Rodrigues:
VINNAS: Variational Inference-based Neural Network Architecture Search. CoRR abs/2007.06103 (2020)
2010 – 2019
- 2019
- [c8]Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP 2019: 1-8 - [c7]Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo:
Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism. FCCM 2019: 45-52 - [c6]Hongxiang Fan, Gang Wang, Martin Ferianc
Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA. FPT 2019: 28-35 - 2018
- [j1]Shuanglong Liu
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. 11(3): 19:1-19:22 (2018) - [c5]Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL 2018: 287-294 - [c4]Hongxiang Fan, Shuanglong Liu, Martin Ferianc
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT 2018: 14-21 - [c3]Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk:
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT 2018: 30-37 - 2017
- [c2]Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk:
F-C3D: FPGA-based 3-dimensional convolutional neural network. FPL 2017: 1-4 - 2016
- [c1]Song Xu, Qiang Liu, Tao Li, Hongxiang Fan:
IC security evaluation against fault injection attack based on FPGA emulation. FPT 2016: 285-288
Coauthor Index
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