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38th ICCD 2020: Hartford, CT, USA
- 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020. IEEE 2020, ISBN 978-1-7281-9710-4
- Maciej Ciesielski:
Message from the General Chair ICCD 2020. 1 - Daniel Volya
, Prabhat Mishra
Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum Systems. 1-4 - Himanshu Thapliyal
Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. 5-8 - Ritajit Majumdar, Susmita Sur-Kolay:
Special Session: Quantum Error Correction in Near Term Systems. 9-12 - Christopher J. Wood:
Special Session: Noise Characterization and Error Mitigation in Near-Term Quantum Computers. 13-16 - Krithika Dhananjay, Emre Salman:
Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems. 17-20 - Michael P. Frank, Robert W. Brocato, Thomas M. Conte
Special Session: Exploring the Ultimate Limits of Adiabatic Circuits. 21-24 - Himanshu Thapliyal
Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ. 25-28 - Kohei Ogura, Yasuhiro Takahashi
Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function. 29-32 - Dimitrios Tychalas, Michail Maniatakos
Special Session: Potentially Leaky Controller: Examining Cache Side-Channel Attacks in Programmable Logic Controllers. 33-36 - Solon Falas
Special Session: Physics- Informed Neural Networks for Securing Water Distribution Systems. 37-40 - Feng Yu, Yaodan Hu, Teng Zhang, Yier Jin
Special Issue: Resilient Distributed Estimator with Information Consensus for CPS Security. 41-44 - Anomadarshi Barua, Mohammad Abdullah Al Faruque:
Special Session: Noninvasive Sensor-Spoofing Attacks on Embedded and Cyber-Physical Systems. 45-48 - Ioannis Zografopoulos
Special Session: Harness the Power of DERs for Secure Communications in Electric Energy Systems. 49-52 - Ravikumar V. Chakaravarthy, Hua Jiang:
Special Session: XTA: Open Source eXtensible, Scalable and Adaptable Tensor Architecture for AI Acceleration. 53-56 - Jeong-Jun Lee, Peng Li:
Reconfigurable Dataflow Optimization for Spatiotemporal Spiking Neural Computation on Systolic Array Accelerators. 57-64 - Bing Wu
DualFS: A Coordinative Flash File System with Flash Block Dual-mode Switching. 65-72 - Rashmi S. Agrawal, Lake Bu, Michel A. Kinsy:
Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design. 73-79 - Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, Sung Kyu Lim:
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration. 80-87 - Hengyu Zhao, Yubo Zhang, Pingfan Meng, Hui Shi, Li Erran Li, Tiancheng Lou, Jishen Zhao:
Driving Scenario Perception-Aware Computing System Design in Autonomous Vehicles. 88-95 - Anuradha Chathuranga Ranasinghe, Sabih H. Gerez
MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing. 96-104 - Heming Zeng, Chi Zhang, Chentao Wu, Gen Yang, Jie Li
FAGR: An Efficient File-aware Graph Recovery Scheme for Erasure Coded Cloud Storage Systems. 105-112 - Ali Ebrahim
An Efficient Hardware Architecture for Finding Frequent Items in Data Streams. 113-119 - Ivan Fernandez, Ricardo Quislant
NATSA: A Near-Data Processing Accelerator for Time Series Analysis. 120-129 - Bahar Asgari
MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. 130-137 - Yingxun Fu, Yao Sun, Tao Li:
QuPAA: Exploiting Parallel and Adaptive Architecture to Scale up Quantum Computing. 138-145 - Yaobin Qin, Xianbo Zhang, David J. Lilja:
PBCCF: Accelerated Deduplication by Prefetching Backup Content Correlated Fingerprints. 146-154 - Suzhen Wu, Jindong Zhou, Weidong Zhu
EaD: a Collision-free and High Performance Deduplication Scheme for Flash Storage Systems. 155-162 - Chunhua Xiao, Zipei Feng, Ting Wu
COSMA: An Efficient Concurrency-Oriented Space Management Scheme for In-memory File Systems. 163-166 - Tianqi Zhan, Xianpeng Wang, Dan Feng, Wei Tong:
AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs. 167-174 - Hui Chen, Yina Lv
An Empirical Study of Hybrid SSD with Optane and QLC Flash. 175-178 - Mehran Goli
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. 179-186 - Leonid Yavits, Lois Orosa
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. 187-196 - Xiaoming Du, Cong Li
DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention. 197-204 - Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture. 205-212 - Haoqiang Guo, Lu Peng, Jian Zhang, Qing Chen, Travis LeCompte:
ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural Networks. 213-221 - Xiaoyang Lu
APAC: An Accurate and Adaptive Prefetch Framework with Concurrent Memory Access Analysis. 222-229 - Abhijit Das
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers. 230-238 - Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam:
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. 239-246 - Kyle Kuan, Tosiron Adegbija:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. 247-254 - Zhulin Ma, Yujuan Tan, Hong Jiang, Zhichao Yan, Duo Liu, Xianzhang Chen
Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation. 255-262 - Amir Erfan Eshratifar, Massoud Pedram:
Runtime Deep Model Multiplexing for Reduced Latency and Energy Consumption Inference. 263-270 - Md Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda:
Near-Sensor Inference Architecture with Region Aware Processing. 271-278 - Jiangsu Du, Minghua Shen, Yunfei Du:
A Distributed In-Situ CNN Inference System for IoT Applications. 279-287 - Xiangzhong Luo, Di Liu, Hao Kong, Weichen Liu:
EdgeNAS: Discovering Efficient Neural Architectures for Edge Systems. 288-295 - Wentian Jin, Sheriff Sadiqbatcha, Zeyu Sun, Han Zhou, Sheldon X.-D. Tan:
EM-GAN: Data-Driven Fast Stress Analysis for Multi-Segment Interconnects. 296-303 - Xu He, Yipei Wang, Zhiyong Fu, Yao Wang, Yang Guo:
Maximum Clique Based Method for Optimal Solution of Pattern Classification. 304-311 - Vladimir Herdt, Daniel Große, Sören Tempel
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. 312-315 - Marcos T. Leipnitz, Gabriel L. Nazar:
Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis. 316-323 - Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. 324-331 - Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann
4-output Programmable Spin Wave Logic Gate. 332-335 - Rohit Sreekumar, Prattay Chowdhury, Benjamin Carrión Schäfer:
Bespoke Behavioral Processors. 336-339 - Ponnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes:
Hardware-based Fast Real-time Image Classification with Stochastic Computing. 340-347 - Kunal Bharathi, Jiang Hu, Sunil P. Khatri:
Scaled Population Subtraction for Approximate Computing. 348-355 - Joonas Multanen, Kari Hepola
Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. 356-363 - Giovanni Bambini
An Open-Source Scalable Thermal and Power Controller for HPC Processors. 364-367 - Sandeep Krishna Thirumala, Arnab Raha, Vijay Raghunathan, Sumeet Kumar Gupta:
IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-Memory. 368-376 - Ki-Dong Kang, Hyungwon Park, Gyeongseo Park, Daehoon Kim:
Improving the Efficiency of Power Management via Dynamic Interrupt Management. 377-380 - Cheng Tan
OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs. 381-388 - Jin Wu
PerfDBT: Efficient Performance Regression Testing of Dynamic Binary Translation. 389-392 - Rahul Krishnamurthy, Michael S. Hsiao:
Transforming Natural Language Specifications to Logical Forms for Hardware Verification. 393-396 - Yongjian Li, Taifeng Cao, David N. Jansen
Accelerated Verification of Parametric Protocols with Decision Trees. 397-404 - Wenpeng He
H2ORAM: Low Response Latency Optimized ORAM for Hybrid Memory Systems. 405-408 - Rui Xu, Edwin H.-M. Sha, Qingfeng Zhuge, Shouzhen Gu, Liang Shi:
Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory. 409-416 - Chao-Hsuan Huang, Ishan G. Thakkar:
Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. 417-420 - Beomjun Kim, Prashant J. Nair, Seokin Hong:
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches. 421-424 - Anthony Agnesina, Da Eun Shim, James Yamaguchi, Christian Krutzik, John Carson, Dan Nakamura, Sung Kyu Lim
A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications. 425-432 - Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. 433-440 - Raghda El Shehaby, Andreas Steininger
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. 441-444 - S. Ross Thompson, James E. Stine:
A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier. 445-452 - Farid Uddin Ahmed, Zarin Tasnim Sandhie
An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V. 453-456 - Wei Chu, Wei-Hao Chen, Shi-Yu Huang:
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. 457-460 - Xiaowei Wang, Li Zhao, Pengcheng Li:
High Throughput CNN Inference and Training with In-Cache Computation. 461-464 - Hongxiang Fan, Martin Ferianc
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. 465-468 - Xinyi Zhang, Weiwen Jiang, Jingtong Hu:
Achieving Full Parallelism in LSTM via a Unified Accelerator Design. 469-477 - Dawen Xu, Cheng Chu, Qianlong Wang, Cheng Liu, Ying Wang, Lei Zhang, Huaguo Liang, Kwang-Ting Cheng
A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. 478-485 - Jianhao Chen, Joseph Riad, Edgar Sánchez-Sinencio, Peng Li:
Dynamic Heterogeneous Voltage Regulation for Systolic Array-Based DNN Accelerators. 486-493 - Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo:
CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks. 494-497 - Ajinkya S. Bankar, Shi Sha
Thermal Aware Lifetime Reliability Optimization for Automotive Distributed Computing Applications. 498-505 - Md Toufiq Hasan Anik, Mohammad Ebrahimabadi, Hamed Pirsiavash, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi:
On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability. 506-509 - Zhe Jiang, Shuai Zhao, Pan Dong, Dawei Yang, Ran Wei, Nan Guan
Re-Thinking Mixed-Criticality Architecture for Automotive Industry. 510-517 - Sangyoung Park
Design- Time Optimization of Reconfigurable PV Architectures for Irregular Surfaces. 518-524 - Xin Wang, Wei Zhang:
pacSCA: A Profiling-Assisted Correlation-based Side-Channel Attack on GPUs. 525-528 - Md Hafizul Islam Chowdhuryy
BranchSpec: Information Leakage Attacks Exploiting Speculative Branch Instruction Executions. 529-536 - Md. Shohidul Islam, Abraham Peedikayil Kuruvila, Kanad Basu, Khaled N. Khasawneh:
ND-HMDs: Non-Differentiable Hardware Malware Detectors against Evasive Transient Execution Attacks. 537-544 - Yukui Luo, Cheng Gongye, Shaolei Ren, Yunsi Fei
Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs. 545-552 - Wei Yang, Hailong Zhang, Yansong Gao, Anmin Fu
Side-Channel Leakage Detection Based on Constant Parameter Channel Model. 553-560 - Zhiyuan Lu, Jianhui Yue, Yifu Deng, Yifeng Zhu:
Improving the Performance of NVM Crash Consistency under Multicore. 561-564 - Ning Bao, Yunpeng Chai, Yuxuan Zhang, Chuanwen Wang, Dafang Zhang:
More Space may be Cheaper: Multi-Dimensional Resource Allocation for NVM-based Cloud Cache. 565-572 - Chundong Wang, Sudipta Chattopadhyay:
Isle-Tree: A B+-Tree with Intra-Cache Line Sorted Leaves for Non-volatile Memory. 573-580 - Wei Li, Libing Wu
Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory. 581-588 - Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. 589-596 - Qiong Chang
Z2-ZNCC: ZigZag Scanning based Zero-means Normalized Cross Correlation for Fast and Accurate Stereo Matching on Embedded GPU. 597-600 - Haoran Zhao, Tian Xia, Chenyang Li, Wenzhe Zhao, Nanning Zheng, Pengju Ren:
Exploring Better Speculation and Data Locality in Sparse Matrix-Vector Multiplication on Intel Xeon. 601-609 - Wei Wang, Lei Cui, Zhiyu Hao, Haiqiang Fei, Chonghua Wang, Yaqiong Peng:
pRnR: A Parallel Record-Replay Framework for Virtual Machines. 610-618 - Tom Glint
ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator. 619-622 - Xi Zeng, Tian Zhi, Zidong Du, Qi Guo, Ninghui Sun, Yunji Chen
ALT: Optimizing Tensor Compilation in Deep Learning Compilers with Active Learning. 623-630 - Hyunjong Choi, Mohsen Karimi, Hyoseung Kim
Chain-Based Fixed-Priority Scheduling of Loosely-Dependent Tasks. 631-639 - Kalle Ngo, Elena Dubrova, Michail Moraitis
Attacking Trivium at the Bitstream Level. 640-647 - Han Wang, Hossein Sayadi, Gaurav Kolhe, Avesta Sasan, Setareh Rafatirad, Houman Homayoun:
Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks. 648-655 - Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai:
ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. 656-662 - Zhixin Pan, Jennifer Sheldon, Prabhat Mishra
Hardware-Assisted Malware Detection using Explainable Machine Learning. 663-666
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