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Alireza Mahzoon
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2020 – today
- 2024
- [j4]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Arithmetic Circuits. Found. Trends Electron. Des. Autom. 14(3): 171-244 (2024) - 2023
- [c23]Alireza Mahzoon
, Rolf Drechsler
Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. Applicable Formal Methods for Safe Industrial Products 2023: 308-319 - [c22]Rolf Drechsler, Alireza Mahzoon:
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. DATE 2023: 1-2 - [c21]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Floating Point Adders. DATE 2023: 1-2 - [c20]Rolf Drechsler, Alireza Mahzoon:
Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. ISDCS 2023: 1-4 - [c19]Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED 2023: 1-7 - 2022
- [b1]Alireza Mahzoon:
Formal verification of structurally complex multipliers. University of Bremen, Germany, 2022, pp. 1-164 - [j3]Alireza Mahzoon
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1573-1586 (2022) - [c18]Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC 2022: 1183-1188 - [c17]Rolf Drechsler
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS 2022: 1-6 - [c16]Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD 2022: 1-10 - [c15]Rolf Drechsler
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. ICCAD 2022: 70:1-70:9 - [c14]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Complex Multipliers. MBMV 2022: 1-4 - [c13]Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP 2022: 22-28 - [c12]Rolf Drechsler
Preserving Design Hierarchy Information for Polynomial Formal Verification. VLSI-SoC 2022: 1-7 - [p1]Alireza Mahzoon:
Formale Verifikation von strukturell komplexen Multiplizierern. Ausgezeichnete Informatikdissertationen 2022: 191-200 - [i1]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
Lower Bound Proof for the Size of BDDs representing a Shifted Addition. CoRR abs/2209.12477 (2022) - 2021
- [c11]Alireza Mahzoon, Rolf Drechsler
Polynomial Formal Verification of Prefix Adders. ATS 2021: 85-90 - [c10]Alireza Mahzoon, Rolf Drechsler
Late Breaking Results: Polynomial Formal Verification of Fast Adders. DAC 2021: 1376-1377 - [c9]Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE 2021: 1110-1115 - [c8]Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD 2021: 519-526 - [c7]Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
Polynomial word-level verification of arithmetic circuits. MEMOCODE 2021: 1-9 - 2020
- [c6]Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Towards Formal Verification of Optimized and Industrial Multipliers. DATE 2020: 544-549 - [c5]Mehran Goli
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD 2020: 179-186
2010 – 2019
- 2019
- [c4]Alireza Mahzoon, Daniel Große
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC 2019: 185 - 2018
- [c3]Alireza Mahzoon, Daniel Große
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD 2018: 129 - [c2]Alireza Mahzoon, Daniel Große
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI 2018: 351-356 - 2017
- [j2]Alireza Mahzoon, Bijan Alizadeh
Systematic Design Space Exploration of Floating-Point Expressions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 274-278 (2017) - [j1]Alireza Mahzoon, Bijan Alizadeh
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 198-209 (2017) - 2015
- [c1]Alireza Mahzoon, Bijan Alizadeh:
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. ISVLSI 2015: 243-248
Coauthor Index
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