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Qing'an Li
Person information
- affiliation: Wuhan University, Computer School, China
- affiliation: Wuhan University, State Key Laboratory of Software Engineering, China
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2020 – today
- 2024
- [j22]Zekun Wang
, Zifei Xu, Chang Cai, Xiaodong Wang
Rolling bearing fault diagnosis method using time-frequency information integration and multi-scale TransFusion network. Knowl. Based Syst. 284: 111344 (2024) - [c28]Jiacheng Huang
More Apps, Faster Hot-Launch on Mobile Devices via Fore/Background-aware GC-Swap Co-design. ASPLOS (3) 2024: 654-670 - [c27]Junhui He, Shangyu Wu, Weidong Wen, Chun Jason Xue, Qingan Li:
CHESS: Optimizing LLM Inference via Channel-Wise Thresholding and Selective Sparsification. EMNLP 2024: 18658-18668 - [i3]Junhui He, Shangyu Wu, Weidong Wen, Chun Jason Xue, Qingan Li:
CHESS: Optimizing LLM Inference via Channel-Wise Thresholding and Selective Sparsification. CoRR abs/2409.01366 (2024) - 2023
- [j21]Ziwei Wang, Wei Li, Ziqi Shuai, Qingan Li:
GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory. Microprocess. Microsystems 103: 104971 (2023) - [j20]Jifeng Wu
Effective Stack Wear Leveling for NVM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3250-3263 (2023) - [c26]Jinheng Li
Shared Dictionary Compression for Efficient Mobile Software Distribution. RTCSA 2023: 85-94 - [c25]Yaohui Peng
Statistical Type Inference for Incomplete Programs. ESEC/SIGSOFT FSE 2023: 720-732 - 2022
- [j19]Wei Li, Qingan Li, Yunlong Ming, Weijiao Dai, Shi Ying, Mengting Yuan
An empirical study of the effectiveness of IR-based bug localization for large-scale industrial projects. Empir. Softw. Eng. 27(2): 47 (2022) - [j18]Libing Wu, Rui Zhang, Qingan Li, Chao Ma, Xiaochuan Shi:
A mobile edge computing-based applications execution framework for Internet of Vehicles. Frontiers Comput. Sci. 16(5): 165506 (2022) - [j17]Shuqin Cao, Libing Wu, Jia Wu
A spatio-temporal sequence-to-sequence network for traffic flow prediction. Inf. Sci. 610: 185-203 (2022) - [j16]Fajun Sun
A Fully Authenticated Diffie-Hellman Protocol and Its Application in WSNs. IEEE Trans. Inf. Forensics Secur. 17: 1986-1999 (2022) - [j15]Rui Zhang, Libing Wu, Shuqin Cao
Task Offloading with Task Classification and Offloading Nodes Selection for MEC-Enabled IoV. ACM Trans. Internet Techn. 22(2): 51:1-51:24 (2022) - [c24]Jiacheng Huang
Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail. ASP-DAC 2022: 377-382 - [c23]Xudong Wang, Xuezheng Xu, Qingan Li, Mengting Yuan, Jingling Xue:
Recovering Container Class Types in C++ Binaries. CGO 2022: 131-143 - [c22]Jiaqi Li, Min Peng, Qingan Li, Meizheng Peng, Mengting Yuan:
GLite: a fast and efficient automatic graph-level optimizer for large-scale DNNs. DAC 2022: 199-204 - 2021
- [j14]Zekun Wang
Study on the Optimal Configuration of a Wind-Solar-Battery-Fuel Cell System Based on a Regional Power Supply. IEEE Access 9: 47056-47068 (2021) - [c21]Liu He, Qing'an Li, Libing Wu, Min Wang
A Spatial-Temporal Graph Attention Network for Multi-intersection Traffic Light Control. IJCNN 2021: 1-8 - [i2]Fajun Sun, Selena He, Xiaotong Zhang, Fanfan Shen, Qingan Li, Yanxiang He:
TinyAKE: A More Practicable and Trustable Scheme for Authenticated Key Establishment in WSNs. CoRR abs/2104.01907 (2021) - 2020
- [c20]Wei Li, Libing Wu
Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory. ICCD 2020: 581-588
2010 – 2019
- 2019
- [j13]Fanfan Shen, Yanxiang He, Jun Zhang, Qingan Li, Jianhua Li
Reuse locality aware cache partitioning for last-level cache. Comput. Electr. Eng. 74: 319-330 (2019) - [j12]Jun Zhang, Yanxiang He, Fanfan Shen, Qing'an Li, Hai Tan:
Memory-aware TLP throttling and cache bypassing for GPUs. Clust. Comput. 22(Suppl 1): 871-883 (2019) - [c19]Wei Li, Ziqi Shuai
A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems. DATE 2019: 228-233 - [c18]Fuyang Li
Checkpointing-aware Data Allocation for Energy Harvesting Powered Non-volatile Processors. NVMSA 2019: 1-6 - 2017
- [j11]Mengying Zhao
Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1804-1816 (2017) - 2016
- [j10]Keni Qiu, Qing'an Li
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems. IEEE Trans. Computers 65(7): 2313-2324 (2016) - 2015
- [j9]Yanxiang He, Tao Yu, Yanzhao Chen, Qingan Li, Tongrang Fan:
物联网环境中数据存储与查询机制研究 (Data Storage and Query in Internet of Things). 计算机科学 42(3): 185-190 (2015) - [j8]Qing'an Li, Yanxiang He, Jianhua Li, Liang Shi, Yiran Chen, Chun Jason Xue:
Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. IEEE Trans. Computers 64(8): 2169-2181 (2015) - [c17]Qing'an Li, Mengying Zhao, Jingtong Hu
Compiler directed automatic stack trimming for efficient non-volatile processors. DAC 2015: 183:1-183:6 - [c16]Mengying Zhao, Qing'an Li, Mimi Xie, Yongpan Liu, Jingtong Hu, Chun Jason Xue:
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system. DATE 2015: 567-572 - 2014
- [j7]Keni Qiu, Mengying Zhao, Qing'an Li, Chenchen Fu, Chun Jason Xue
Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 329-342 (2014) - [j6]Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue
Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols. IEEE Trans. Parallel Distributed Syst. 25(10): 2697-2707 (2014) - [j5]Yazhi Huang, Liang Shi, Jianhua Li, Qing'an Li
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 168-180 (2014) - [j4]Qing'an Li
Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1829-1840 (2014) - [j3]Liang Shi, Jianhua Li, Qing'an Li
A Unified Write Buffer Cache Management Scheme for Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2779-2792 (2014) - [c15]Keni Qiu, Qing'an Li, Chun Jason Xue
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM. DAC 2014: 106:1-106:6 - [c14]Qing'an Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu:
A wear-leveling-aware dynamic stack for PCM memory in embedded systems. DATE 2014: 1-4 - [c13]Yiqun Wang, Hongyang Jia, Yongpan Liu, Qing'an Li, Chun Jason Xue
Register allocation for hybrid register architecture in nonvolatile processors. ISCAS 2014: 1050-1053 - 2013
- [j2]Jianhua Li, Liang Shi, Qing'an Li
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh. ACM Trans. Design Autom. Electr. Syst. 19(1): 5:1-5:23 (2013) - [j1]Wanyong Tian, Yingchao Zhao
Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1271-1284 (2013) - [c12]Qing'an Li
Compiler-assisted refresh minimization for volatile STT-RAM cache. ASP-DAC 2013: 273-278 - [c11]Mengting Yuan, Chun Jason Xue
Minimizing code size via page selection optimization on partitioned memory architectures. CASES 2013: 12:1-12:10 - [c10]Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen, Yinlong Xu:
Cache coherence enabled adaptive refresh for volatile STT-RAM. DATE 2013: 1247-1250 - [c9]Qing'an Li
Compiler directed write-mode selection for high performance low power volatile PCM. LCTES 2013: 101-110 - 2012
- [c8]Qing'an Li
MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory. Interaction between Compilers and Computer Architectures 2012: 17-24 - [c7]Jianhua Li, Liang Shi, Qing'an Li
TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols. ESTIMedia 2012: 19-26 - [c6]Qing'an Li
MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems. ISLPED 2012: 351-356 - [c5]Qing'an Li
Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache. ISVLSI 2012: 410-415 - [c4]Qing'an Li, Mengying Zhao, Chun Jason Xue
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache. LCTES 2012: 109-118 - 2011
- [c3]Yong Chen, Yanxiang He, Wei Wu, Qing'an Li:
Game Model Based Register Allocation. ICAIC (4) 2011: 268-273 - [c2]Yazhi Huang, Qing'an Li
Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems. TrustCom 2011: 1038-1044 - 2010
- [c1]Qing'an Li, Yanxiang He, Lei Zhou, Wei Wu, Yong Chen:
Integer Promotion Elimination on Abstract Syntax Tree. CIT 2010: 2367-2372 - [i1]Qing'an Li, Yanxiang He, Yong Chen, Wei Wu, Wenwen Xu:
A Heuristic Algorithm for optimizing Page Selection Instructions. CoRR abs/1008.0909 (2010)
Coauthor Index
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last updated on 2024-11-15 19:33 CET by the dblp team
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