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(IC)FPT 2021: Auckland, New Zealand
- International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021. IEEE 2021, ISBN 978-1-6654-2010-5
- Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. 1-10 - Johannes Wirth, Jaco A. Hofmann, Lasse Thostrup, Carsten Binnig
, Andreas Koch:
Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases. 1-9 - Kaichuang Shi
A Hexagon-Based Honeycomb Routing Architecture for FPGA. 1-6 - Cheng Wang, Yingkun Liu, Kedai Zuo, Jianming Tong, Yan Ding, Pengju Ren:
ac2SLAM: FPGA Accelerated High-Accuracy SLAM with Heapsort and Parallel Keypoint Extractor. 1-9 - Ichiro Kawashima, Yuichi Katori, Takashi Morie, Hakaru Tamukoh:
An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing. 1-4 - Ryohei Yamamoto, Yuki Izumi, Ryo Aono, Takumi Nagahara, Tomonari Tanaka, Wang Liao, Yukio Mitsuyama:
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs. 1-4 - Zhewen Yu, Christos-Savvas Bouganis:
StreamSVD: Low-rank Approximation and Streaming Accelerator Co-design. 1-9 - Siyang Jiang, Hsi-Wen Chen, Ming-Syan Chen:
Dataflow Systolic Array Implementations of Exploring Dual-Triangular Structure in QR Decomposition Using High-Level Synthesis. 1-4 - Austin Liolli, Omar Ragheb, Jason Helge Anderson:
Profiling-Based Control-Flow Reduction in High-Level Synthesis. 1-6 - Torben Kalkhof, Andreas Koch:
Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems. 1-10 - Pedro Filipe Silva, João Bispo, Nuno Paulino
FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example. 1-4 - Johan Peltenburg, Ákos Hadnagy, Matthijs Brobbel, Robert Morrow, Zaid Al-Ars:
Tens of gigabytes per second JSON-to-Arrow conversion with FPGA accelerators. 1-9 - Ruth Abra, Dmitry Denisenko, Richard Allen, Tim Vanderhoek, Sarah Wolstencroft, Peter M. Gibson:
Low Precision Networks for Efficient Inference on FPGAs. 1-5 - Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo:
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. 1-9 - Jing Tan, Gaofeng Lv, Yanni Ma, Guanjie Qiao:
High-performance pipeline architecture for packet classification accelerator in DPU. 1-4 - Sameh Attia
StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration. 1-10 - Martin Ferianc
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator. 1-10 - Hyuga Hashimoto, Ryo Naka, Yasutaka Wada:
An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit". 1-3 - Akira Kojima:
Autonomous Driving System implemented on Robot Car using SoC FPGA. 1-4 - Tomás Fukac, Jirí Matousek, Jan Korenek, Lukás Kekely:
Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. 1-9 - Xuan Feng, Yue Li, Yu Qian
A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions. 1-4 - Philippos Papaphilippou
Efficient Queue-Balancing Switch for FPGAs. 1-5 - Tiago Santos
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. 1-4 - A. Manjarrés García, Carlos Alexander Osorio Quero
Parallel-Pipeline Fast Walsh-Hadamard Transform Implementation Using HLS. 1-4 - Xiaoxi Wang, Moucheng Yang, Zhen Li
Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning. 1-5 - Hayato Amano, Hayato Mori, Akinobu Mizutani
A dataset generation for object recognition and a tool for generating ROS2 FPGA node. 1-4 - Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai:
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim. 1-5 - Ryota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase:
Zytlebot : FPGA integrated ros-based autonomous mobile robot. 1-4 - Keisuke Sugiura, Hiroki Matsutani:
A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs. 1-9 - Nathan Zhang, Matthew Feldman, Kunle Olukotun
High performance lattice regression on FPGAs via a high level hardware description language. 1-10 - Andrei Tosa, Anca Hangan
In-Storage Computation of Histograms with differential privacy. 1-4 - Alexander Klemd, Patrick Nowak, Piero Rivera Benois, Etienne Gerat, Udo Zölzer, Bernd Klauer:
Exponential sine sweep measurement implementation targeting FPGA platforms. 1-6 - Keigo Motoyoshi, Yuta Imamura, Taichi Saikai, Koki Fujita, Daiki Furukawa, Masatomo Matsuda, Tatsuma Mori, Yasutoshi Araki, Takehiro Miura, Keizo Yamashita, Haruto Ikehara, Kaito Ohira, Katsuaki Kamimae, Takuho Kawazu, Masahiro Nishimura, Shintaro Matsui, Koki Tomonaga, Taito Manabe, Yuichiro Shibata:
SoC FPGA implementation of an unmanned mobile vehicle with an image transmission system over VNC. 1-4 - Chengcheng Huang, Xiaoxiao Dong, Zhao Li, Tengteng Song, Zhenguo Liu, Lele Dong:
Efficient Stride 2 Winograd Convolution Method Using Unified Transformation Matrices on FPGA. 1-9 - Richard Gebauer
A modular RFSoC-based approach to interface superconducting quantum bits. 1-9 - Hirotoshi Ito, Minoru Watanabe:
Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation. 1-4 - Jingyi Li:
Real-time Implementation of Cyclostationary Analysis using FPGAs. 1-4 - Luke Beckwith, Duc Tri Nguyen, Kris Gaj:
High-Performance Hardware Implementation of CRYSTALS-Dilithium. 1-10 - Jingbo Gao, Yu Qian
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. 1-9 - Yuan Dai
APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications. 1-8 - Su Zheng, Kaisen Zhang, Yaoguang Tian, Wenbo Yin, Lingli Wang, Xuegong Zhou:
FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays. 1-10 - Puya Amiri
FLOWER: A comprehensive dataflow compiler for high-level synthesis. 1-9 - Hector A. Li Sanchez, Alan D. George
A streaming hardware architecture for real-time SIFT feature extraction. 1-9 - Marcel Flottmann, Marc Eisoldt, Julian Gaal, Marc Rothmann, Marco Tassemeier, Thomas Wiemann, Mario Porrmann:
Energy-efficient FPGA-accelerated LiDAR-based SLAM for embedded robotics. 1-6 - Jiadong Qian, Yuhang Shen, Kaichuang Shi
General routing architecture modelling and exploration for modern FPGAs. 1-9 - Kazunari Takasaki, Kota Hisafuru, Ryotaro Negishi, Kazuki Yamashita, Keisuke Fukada, Tomoya Wakaizumi, Nozomu Togawa:
An autonomous driving system utilizing image processing accelerated by FPGA. 1-4 - Kazuki Furukawa, Ryohei Kobayashi
An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer. 1-9 - Hossein Borhanifar, Hamed Jani, Mohammad Mahdi Gohari, Amir Hossein Heydarian, Mostafa Lashkari, Mohammad Reza Lashkari:
Fast controling autonomous vehicle based on real time image processing. 1-4 - Najdet Charaf
AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs. 1-6 - Julia Burgiel, Daniel E. Holcomb, Ilias Giechaskiel, Shanquan Tian, Jakub Szefer:
Characterization of IOBUF-based Ring Oscillators. 1-4 - Prajith Ramakrishnan Geethakumari, Ioannis Sourdis:
StreamZip: Compressed Sliding-Windows for Stream Aggregation. 1-9
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