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ESSCIRC 2014: Venice Lido, Italy
- ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014. IEEE 2014, ISBN 978-1-4799-5694-4
- Greg Atwood, Scott DeBoer, Kirk Prall, Linda Somerville:
A semiconductor memory development and manufacturing perspective. 1-6 - Sehat Sutardja:
Slowing of Moore's law signals the beginning of Smart Everything. 7-8 - Walter Snoeys
:
How chips helped discover the Higgs boson at CERN. 9-19 - Fabio Marchio, Boris Vittorelli, Roberto Colombo:
Automotive electronics: Application & technology megatrends. 23-29 - Thomas H. Lee:
Terahertz electronics: The last frontier. 30-34 - Hooman Darabi, David Murphy, Mohyee Mikhemar, Ahmad Mirzaei:
Blocker tolerant software defined receivers. 35-42 - Nima Maghari, Un-Ku Moon:
Emerging analog-to-digital converters. 43-50 - Kathleen Philips:
Ultra Low Power short range radios: Covering the last mile of the IoT. 51-58 - Yusuf Haque, Donald E. Lewis, Rex Hales, Ryan J. Kier, Tracy Johancsik, Paul T. Watkins, William Picken, Marcellus Harper, Shyam Dujari:
Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration. 59-62 - Peng Zhu, Xinpeng Xing, Georges G. E. Gielen
A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer. 63-66 - Rohan Sehgal
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. 67-70 - Ilter Özkaya, Cagri Gurleyuk, Atilim Ergul, Arda Akkaya, Devrim Yilmaz Aksin
A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR. 71-74 - Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico
A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. 75-78 - Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. 79-82 - Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. 83-86 - Abhirup Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda:
A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process. 87-90 - Jason Silver, Kannan A. Sankaragomathi, Brian P. Otis:
An ultra-low-voltage all-digital PLL for energy harvesting applications. 91-94 - Hossein Kassiri, Arezu Bagheri, Nima Soltani, Karim Abdelhalim, Hamed Mazhab-Jafari, Muhammad Tariqus Salam, José Luis Pérez Velazquez, Roman Genov:
Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio. 95-98 - Peng Cong, Piyush Karande
A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation. 99-102 - Ulrich Bihr, Jens Anders
A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance. 103-106 - William Anthony Smith, Brian Mogen, Eberhard E. Fetz, Brian Otis:
A spectrum-equalizing analog front end for low-power electrocorticography recording. 107-110 - Abdelali El Amraoui, Marc Bocquet, F. Barros, Jean-Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih
Printed complementary organic thin film transistors based decoder for ferroelectric memory. 111-114 - Pinar Basak Basyurt, Devrim Yilmaz Aksin
A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference. 115-118 - Myungjoon Choi, Inhee Lee, Tae-Kwang Jang
A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs. 119-122 - Benjamin Saft, Eric Schaefer, André Jäger, Alexander Rolapp, Eckhard Hennig
An improved low-power CMOS thyristor-based micro-to-millisecond delay element. 123-126 - Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki
A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. 127-130 - Enrico Temporiti, Gabriele Minoia
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies. 131-134 - Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese
A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. 135-138 - Ilkka Nissinen
A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopy. 139-142 - Nikola Krstajic
A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensing. 143-146 - Piotr Maj
23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e- rms, 19 e- rms offset spread and 3% rms gain spread. 147-150 - Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht
A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters. 151-154 - Jung-Woo Ha, Bai-Sun Kong, Jung-Hoon Chun, Byeong-Ha Park:
A fast response integrated current-sensing circuit for peak-current-mode buck regulator. 155-158 - Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht
Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems. 159-162 - Waclaw Godycki, Bo Sun, Alyssa B. Apsel:
Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter. 163-166 - Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen
Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology. 167-170 - Yu Pei, Ying Chen, Domine M. W. Leenaerts, Bianca Slaats, A. Zamanifekri:
A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamforming. 171-174 - Aurelien Larie, Eric Kerherve
A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS. 175-178 - Junlei Zhao, Matteo Bassi
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP. 179-182 - Alaa Medra, Vito Giannini
A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C. 183-186 - Shunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren:
A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. 187-190 - Seongwook Park, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo:
A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR. 191-194 - Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai:
A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications. 195-198 - Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic:
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. 199-202 - Harald Kroll, Stefan Zwicky, Benjamin Weber
An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity. 203-206 - Luke Wang, Qiwei Wang, Anthony Chan Carusone
Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS. 207-210 - Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. 211-214 - Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. 215-218 - Long Chen, Arindam Sanyal, Ji Ma, Nan Sun:
A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. 219-222 - Remko E. Struiksma, Eric A. M. Klumperink, Bram Nauta
A 500MHz- 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering. 223-226 - Chul Kim, Sohmyung Ha
A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. 227-230 - Dongju Lee
A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receivers. 231-234 - Carl Bryant, Henrik Sjöland
A 2.45GHz, 50uW wake-up receiver front-end with -88dBm sensitivity and 250kbps data rate. 235-238 - Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. 239-242 - Oskar Andersson
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. 243-246 - Luca Ravezzi, Hamid Partovi, Dong Wang, C. Wang, Ronen Cohen, Matt Ashcraft, Alfred Yeung, Qawi Harvard, Russell Homer, John Ngai, Greg Favor:
Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC. 247-250 - Tzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
An on-die all-digital power supply noise analyzer with enhanced spectrum measurements. 251-254 - Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters. 255-258 - Michele Dini, Matteo Filippi, Aldo Romani, Marco Tartagni, Valeria Bottarel, Giulio Ricotti:
A 40 nA/source energy harvesting power converter for multiple and heterogeneous sources. 259-262 - Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai:
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. 263-266 - Athanasios Sarafianos, Michiel Steyaert
The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters. 267-270 - Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan:
A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency. 271-274 - Yao Liu, Duan Zhao, Yongjia Li, Wouter A. Serdijn:
A 5b 12.9 µW charge-redistribution phase domain ADC for low power FSK/PSK demodulation. 275-278 - André Mansano, Sumit Bagga, Wouter A. Serdijn:
A 13.56/402 MHz autonomous wireless sensor node with -18.2 dBm sensitivity and temperature monitoring in 0.18 /im CMOS. 279-282 - Gabriele Devita, Alan Chi Wai Wong, Mark Dawkins, Kostas N. Glaros, U. Kiani, Franco Lauria, V. Madaka, Okundu C. Omeni, Johannes Schiff, A. Vasudevan, L. Whitaker, S. Yu, Alison J. Burdett:
A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications. 283-286 - Fabio Padovan, Andrea Bevilacqua
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. 287-290 - Paramartha Indirayanti, Tuba Ayhan, Marian Verhelst
A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization. 291-294 - Sechang Oh
Dual-slope capacitance to digital converter integrated in an implantable pressure sensing system. 295-298 - Hanspeter Schmid, Alexander Huber, Dirk Sutterlin, Werner Tanner:
A highly sensitive frontend IC for very robust capacitive vortex flowmeter sensors. 299-302 - Assim Boukhayma, Jean-Pierre Rostaing, A. Mollard, Fabrice Guellec
A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation. 303-306 - Manuel Suarez, Víctor M. Brea
A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extraction. 311-314 - Shin-Hao Chen, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen
A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique. 315-318 - Vincent Binet, Francois Amiard, Emmanuel Allier, Simon Valcin, Angelo Nagari:
A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing. 319-322 - Paolo Bruschi
A very compact CMOS instrumentation amplifier with nearly rail-to-rail input common mode range. 323-326 - Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, Franklin Bien:
Dynamic range enhanced readout circuit for a capacitive touch screen panel with current subtraction technique. 327-330 - Marco Garampazzi, Paulo M. Mendes
A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering. 331-334 - Luca Fanori, Thomas Mattsson, Pietro Andreani:
A Class-D CMOS DCO with an on-chip LDO. 335-338 - Yoshiaki Yoshihara, Hideaki Majima, Ryuichi Fujimoto:
A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control. 339-342 - Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. 343-346 - Stefano Perticaroli, Fabrizio Palma:
A robust start-up Class-C CMOS VCO based on a common mode low frequency feedback loop. 347-350 - Nicolo Sabatino, Gabriele Minoia
A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS. 351-354 - Shahbaz Abbasi
1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS. 355-358 - Chun-Wei Hsu, Peter R. Kinget
A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensation. 359-362 - Marcello De Matteis
A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter. 363-366 - Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland
A 4th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS. 367-370 - Mikko Englund, Kim B. Ostman
A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator. 371-374 - Shiyuan Zheng, Howard C. Luong
A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS. 375-378 - Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3. 379-382 - Shahrzad Tadjpour, Paolo Rossi, Luca Romanò, Ramesh Chokkalingam, Hamid Firouzkouhi, Feng Shi, M. Leroux, Danilo Gerna, A. Venca, John Vasa, Bala Ramachandran, Brian Brunn, Alberto Pirola, Daniele Ottini, A. Milani, Enrico Sacchi, M. Behera, X. Chen, U. Decanis, Marika Tedeschi, S. DalToso, W. Eyssa, C. Cakir, C. Prakash, Yong He, Nader Damavandi, R. Srinivasan, Dan Shum, X. Fan, C. Yu, Engin Pehlivanoglu, Hossein Zarei, Aravind Loke, Gregory Uehara, Rinaldo Castello
A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope tracking. 383-386 - Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, Hiroki Ishikuro:
A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing. 387-390 - Pyoungwon Park, Kofi A. A. Makinwa, David Ruffieux:
A resistor-based temperature sensor for a real time clock with ±2ppm frequency stability. 391-394 - Ugur Sonmez, Rui Quan, Fabio Sebastiano
A 0.008-mm2 area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring. 395-398 - Igor I. Izyumin, Mitchell Kline, Yu-Ching Yeh, Burak Eminoglu, Bernhard E. Boser:
A 50 µW, 2.1 mdeg/s/√Hz frequency-to-digital converter for frequency-output MEMS gyroscopes. 399-402 - Ali Fekri, Mohammad Reza Nabavi, Nikola Radeljic-Jakic, Zu-yao Chang, Michiel A. P. Pertijs, Stoyan N. Nihtianov:
An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC. 403-406 - Marco Sautto, Davide Leone, Alessandro Savoia
A CMUT transceiver front-end with 100-V TX driver and 1-mW low-noise capacitive feedback RX amplifier in BCD-SOI technology. 407-410 - Kentaro Yoshioka
A 13b SAR ADC with eye-opening VCO based comparator. 411-414 - Debasish Behera, Nagendra Krishnapura
A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter. 415-418 - Zhiliang Qiao, Xiong Zhou, Qiang Li
A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs. 419-422 - Marco Vigilante, Patrick Reynaert:
An E-Band low-noise Transformer-Coupled Quadrature VCO in 40 nm CMOS. 423-426 - Clement Jany, Alexandre Siligaris, Jose-Luis Gonzalez Jimenez
A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation. 427-430 - Manthena Vamshi Krishna, Anil Jain, Nasir Abdul Quadir
A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. 431-434 - Pier Andrea Francese
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. 435-438 - Shayan Shahramian, Anthony Chan Carusone
A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS. 439-442 - Abhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, Sanjeev Chopra, Tapas Nandy, Vivek Uppal:
A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst. 443-446 - Woo-Rham Bae
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. 447-450 - Marko Aleksic:
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS. 451-454 - Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. 455-458 - Jonas Lindstrand, Ivaylo Vasilev, Henrik Sjöland
A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology. 459-462 - Barend van Liempd, Jan Craninckx
A dual-notch +27dBm Tx-power electrical-balance duplexer. 463-466 - Aritra Banerjee
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS. 467-470 - Xicheng Jiang, Xinyu Yu, Fang Lin, Felix Cheung, Mike Inerfield, Kevin Li, Abhishek Kamath, Harsh Mehta, Jingbo Duan, Jing Yang, Gautham Krishnamurthy, Sumant Ranganathan, Darwin Cheung, Naga Radha Krishna Damaraju, Jianlong Chen, Dongtian Lu, Vinod Jayakumar, Leon Wang, Dario Soltesz, Hongwei Kong, Min Zhang, David Chang:
A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-Chip. 471-474 - Xicheng Jiang, Narayan Prasad Ramachandran, Dae Woon Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang:
Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip. 475-478
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