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Avishek Biswas
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2020 – today
- 2022
- [c7]Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet:
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. CICC 2022: 1-2 - 2021
- [c6]Darshat Shah
, Avishek Biswas
Neural Network Based Brain Tumor Segmentation. BrainLes@MICCAI (2) 2021: 324-333 - [c5]Avinash Ranganath, Avishek Biswas, Ioannis Karamouzas, Victor B. Zordan:
Motor Babble: Morphology-Driven Coordinated Control of Articulated Characters. MIG 2021: 6:1-6:10
2010 – 2019
- 2019
- [j2]Avishek Biswas
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks. IEEE J. Solid State Circuits 54(1): 217-230 (2019) - 2018
- [b1]Avishek Biswas:
Energy-efficient smart embedded memory design for IoT and AI. Massachusetts Institute of Technology, Cambridge, USA, 2018 - [c4]Avishek Biswas, Anantha P. Chandrakasan:
Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. ISSCC 2018: 488-490 - 2017
- [c3]Avishek Biswas, Umut Arslan, Fatih Hamzaoglu, Anantha P. Chandrakasan:
An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS. CICC 2017: 1-4 - 2016
- [c2]Avishek Biswas, Anantha P. Chandrakasan:
A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI. ESSCIRC 2016: 433-436 - 2015
- [j1]Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan:
A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency. IEEE J. Solid State Circuits 50(7): 1540-1549 (2015) - 2014
- [c1]Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan:
A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency. ESSCIRC 2014: 271-274
Coauthor Index
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