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ESSCIRC 2009: Athens, Greece
- 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14-18 September 2009. IEEE 2009, ISBN 978-1-4244-4354-3
- Y. Papananos, D. Tsoukalas:
Foreword. V - Tze-Chiang Chen:
Challenges for silicon technology scaling in the Nanoscale Era. 1-7 - Tadashi Shibata:
Bio-inspired devices, circuits and systems. 8-15 - Victor V. Zhirnov, Ralph K. Cavin III:
Scaling beyond CMOS: Turing-Heisenberg Rapproachment. 16-22 - Michael L. Roukes:
Nanoelectromechanical systems: A new opportunity for microelectronics. 20 - Carlo Cognetti:
The impact of semiconductor packaging technologies on system integration an overview. 23-27 - Joachim N. Burghartz, Wolfgang Appel, Christine Harendt, Horst Rempp, Harald Richter, Martin Zimmermann:
Ultra-thin chips and related applications, a new paradigm in silicon technology. 28-35 - Wim Dehaene, Georges G. E. Gielen
, Michiel Steyaert
RFID, where are they? 36-43 - Ali Hajimiri
The future of high frequency circuit design. 44-51 - Klaas Bult:
Embedded analog-to-digital converters. 52-64 - Rainer Waser
Function by defects at the atomic scale - new concepts for non-volatile memories. 65-72 - Jörg Appenzeller:
Nanowire electronics. 73-75 - Sokrates T. Pantelides, L. Tsetseris, M. J. Beck, Sergey N. Rashkeev, G. Hadjisavvas, I. G. Batyrev, B. R. Tuttle, A. G. Marinopoulos, X. J. Zhou, Daniel M. Fleetwood, Ronald D. Schrimpf:
Performance, reliability, radiation effects, and aging issues in microelectronics - from atomic-scale physics to engineering-level modeling. 76-83 - Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? 84-87 - Claire Fenouillet-Béranger, P. Perreau, S. Denorme, L. Tosti, François Andrieu, Olivier Weber, S. Barnola, C. Arvet, Y. Campidelli, Sébastien Haendler, R. Beneyton, C. Perrot, C. de Buttet, P. Gros, Loan Pham-Nguyen
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. 88-91 - Stefan Drapatz, Thomas Fischer, Karl Hofmann, Ettore Amirante, Peter Huber, Martin Ostermayr, Georg Georgakos, Doris Schmitt-Landsiedel:
Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation. 92-95 - S. K. Hampel, Oliver Schmitz, Marc Tiebout, Ilona Rolfes
Wideband inductorless minimal area RF front-end. 96-99 - Jonathan Borremans, Steven Thijs, Morin Dehan, Abdelkarim Mercha, Piet Wambacq:
Low-cost feedback-enabled LNAs in 45nm CMOS. 100-103 - Sebastien Robert, Olivier Abed-Meraim, Luca Lo Coco:
Wide-band variable-gain LNA in 65 nm CMOS with inverter based amplifier for multi-tuners cable TV reception. 104-107 - Takahide Terada, Taizo Yamawaki, Masaru Kokubo, Koji Nasu:
100-1000 MHz cutoff frequency, 0-12 dB boost programmable Gm-C filter with digital calibration for HDD read channel. 108-111 - Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic:
An oscilloscope array for high-impedance device characterization. 112-115 - Eleonora Franchi, Federico Natali, Antonio Gnudi
3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation. 116-119 - Hagen Marien, Michiel Steyaert
A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate. 120-123 - Oliver Schmitz, S. K. Hampel, Koen L. R. Mertens, Marc Tiebout, Ilona Rolfes
A highly linear, differential gyrator in 65nm CMOS for reconfigurable GHz applications. 124-127 - Filip Tavernier, Michiel Steyaert
A low power, area efficient limiting amplifier in 90nm CMOS. 128-131 - Salvatore Drago, Domine Leenaerts, Bram Nauta
A 200 µA duty-cycled PLL for wireless sensor nodes. 132-135 - Devrim Yilmaz Aksin
25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS. 136-139 - Stefan Herzer, Sumeet Kulkarni, Maciej Jankowski, Jochen Neidhardt, Bernhard Wicht:
Capacitive-coupled current sensing and Auto-ranging slope compensation for current mode SMPS with wide supply and frequency range. 140-143 - Mike Wens, Jean-Michel Redoute
An integrated 10A, 2.2ns rise-time laser-diode driver for LIDAR applications. 144-147 - Benno Krabbenborg, Marco Berkhout:
Closed loop class-D amplifier with nonlinear loop integrators. 148-151 - Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas:
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. 152-155 - Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. 156-159 - Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. 160-163 - Armin Tajalli
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. 164-167 - Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau
A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI. 168-171 - Jean Gorisse, Andreia Cathelin, Andreas Kaiser
A 60GHz 65nm CMOS RMS power detector for antenna impedance mismatch detection. 172-175 - Francesco Carrara, Calogero D. Presti, Giuseppe Palmisano:
A 2.4-GHz 24-dBm SOI CMOS power amplifier with on-chip tunable matching network for enhanced efficiency in back-off. 176-179 - Holger Erkens, Ralf Wunderlich, Stefan Heinen:
A double balanced power amplifier for S-band phased arrays in SiGe BiCMOS. 180-183 - Liangge Xu, Kari Stadius, Jussi Ryynänen
A low-power wide-band digital frequency synthesizer for cognitive radio sensor units. 184-187 - Tsuyoshi Sekine, Ryuichi Fujimoto, Yoshimitsu Takamatsu, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Takaya Yasuda, Motohiko Hayashi, H. Itoh, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Shigehito Saigusa, M. Yano, Masaki Nishikawa, Hiroshi Yoshida, Yoshihiro Yoshida, Kenji Yoshioka, Nobuyuki Itoh:
A single-chip RF tuner / OFDM demodulator for mobile digital TV application. 188-191 - Theodoros Chalvatzis, Kostis Vavelidis, Nikos Kanakaris, Iason Vassiliou:
An S-band frontend receiver for mobile TV in 65nm CMOS. 192-195 - Marek Gersbach, Yuki Maruyama, E. Labonne, J. Richardson, Richard Walker
A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology. 196-199 - Andreas Spickermann, Daniel Durini
Pulsed time-of-flight 3D-CMOS imaging using photogate-based active pixel sensors. 200-203 - David Stoppa, Fausto Borghetti, Justin A. Richardson, Richard Walker
A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain. 204-207 - Oreste Sgrott, Daniel Mosconi, Massimo Saiani, David Stoppa, Gianmaria Pedretti, Matteo Perenzoni
A 134-pixel CMOS sensor for combined time-of-flight and Optical Triangulation 3-D imaging. 208-211 - Wei Xiong, Yang Guo, Boris Murmann
A 3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass. 212-215 - Xuan Zhang
A low variation GHz ring oscillator with addition-based current source. 216-219 - Emanuela Buccafurri, Abdelkrim Medjahdi, Françis Calmon, Raphael Clerc
Challenges and prospects of RF oscillators using silicon resonant tunneling diodes. 220-223 - Manolis Terrovitis, Michael P. Mack, J. Hwang, Brian J. Kaczynski, G. Tseng, B. Wang, Srenik S. Mehta, David K. Su:
A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization. 224-227 - Le Ye, Huailin Liao, Fei Song, Jiang Chen, Congyin Shi
A single-chip CMOS UHF RFID Reader transceiver for mobile applications. 228-231 - Francesco Carrara, Alessandro Italia, Giuseppe Palmisano, R. Guerra:
A 400-MHz CMOS radio front-end for ultra low-power medical implantable applications. 232-235 - Gerald Zach, Milos Davidovic, Horst Zimmermann
Extraneous-light resistant multipixel range sensor based on a low-power correlating pixel-circuit. 236-239 - Shin Sakai, Yoshiaki Tashiro, Nana Akahane, Rihito Kuroda
A pixel-shared CMOS image sensor using lateral overflow gate. 240-243 - Christian Koch, Jürgen Oehm, Andreas Gornik:
High precision optical angle measuring method applicable in standard CMOS technology. 244-247 - Hongbo Zhu, Tadashi Shibata:
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor. 248-251 - Bo Shi
A CMOS ESD-protected RF front-end for UWB receiver. 252-255 - Christophe De Roover, Michiel Steyaert
Ultra low power detection circuits in 130nm CMOS for a wireless UWB localization system. 256-259 - Stefano D'Amico
A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers. 260-263 - David Barras, Heinz Jäckel, Walter Hirt:
A wideband 0 to 60 dB CMOS variable gain amplifier for IR-UWB I/Q receivers. 264-267 - Ming-Hsin Huang, Yu-Nong Tsai, Yu-Huei Lee, Shih-Jung Wang, Ke-Horng Chen
Sub-1V input single-inductor dual-output (SIDO) DC-DC converter with adaptive load-tracking control (ALTC) for single-cell-powered system. 268-271 - Yu-Huei Lee, Shih-Jung Wang, Yao-Yi Yang, Kuo-Lin Zheng, Po-Fung Chen, Chun-Yu Hsieh, Ming-Hsin Huang, Yu-Nong Tsai, Yu-Zhou Ke, Ke-Horng Chen
A high efficiency and compact size 65nm power management module with 1.2v low-voltage PWM controller for UWB system application. 272-275 - Michael Karagounis, David Arutinov, Marlon Barbero, Fabian Hügging, Hans Krueger, Norbert Wermes:
An integrated Shunt-LDO regulator for serial powered systems. 276-279 - Jordi Colomer-Farrarons
A 60 µW low-power low-voltage power management unit for a self-powered system based on low-cost piezoelectric powering generators. 280-283 - Dominic Maurath, Yiannos Manoli:
A self-adaptive switched-capacitor voltage converter with dynamic input load control for energy harvesting. 284-287 - Marc Pastre, Maher Kayal, Hanspeter Schmid, Alexander Huber, Pascal Zwahlen, Anne-Marie Nguyen, Yufeng Dong:
A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th-order ΔΣ loop. 288-291 - Syed A. Jawed, Jannik Hammel Nielsen, Massimo Gottardi, Andrea Baschirotto
A multifunction low-power preamplifier for MEMS capacitive microphones. 292-295 - S. Mahdi Kashmiri, Kofi A. A. Makinwa:
A digitally-assisted electrothermal frequency-locked loop. 296-299 - Vadim Issakov
Merged power amplifier and mixer circuit topology for radar applications in CMOS. 300-303 - José Gabriel Macias-Montero, H. Yan, Atef Akhnoukh, Leo C. N. de Vreede, John R. Long, José María López-Villegas, John J. Pekarik:
A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS. 304-307 - Vadim Issakov
Low-noise ESD-protected 24 GHz receiver for radar applications in SiGe: C technology. 308-311 - Shoujun Yang, Hans Peter Forstner, Günther Haider, Harald Kainmueller, Klaus Aufinger, Linus Maurer, Richard Hagelauer:
A low noise, high gain, highly linear mixer for 77 GHz automotive radar applications in SiGe: C bipolar technology. 312-315 - Wolfgang Winkler, Wojciech Debski, Bernd Heinemann, Falk Korndörfer, Holger Rücker, Klaus Schmalz, Christoph Scheytt, Bernd Tillack:
122 GHz low-noise-amplifier in sige technology. 316-319 - Shanthi Pavan, Prabu Sankar:
A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range. 320-323 - Luca Picolli, Marco Grassi
A 1.0 mW, 71 dB SNDR, -1.8 dBFS input swing, fourth-order ΣΔ interface circuit for MEMS microphones. 324-327 - Jun Wang, Toshimasa Matsuoka
A 0.5 V feedforward delta-sigma modulator with inverter-based integrator. 328-331 - Koen Cornelissens, Michiel Steyaert
A 1-V 84-dB DR 1-MHz bandwidth cascade 3-1 Delta-Sigma ADC in 65-nm CMOS. 332-335 - Pieter Crombez, Geert Van der Plas
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. 336-339 - Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. 340-343 - Chia-Hsiang Yang
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS. 344-347 - Jérôme Martin
A Microprogrammable Memory Controller for high-performance dataflow applications. 348-351 - T. S. Doorn, J. A. Croon, E. Jan W. ter Maten, Alessandro Di Bucchianico
A yield centric statistical design method for optimization of the SRAM active column. 352-355 - Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
A resonant-clock 200MHz ARM926EJ-STM microcontroller. 356-359 - Domagoj Siprak, Piet Wambacq, Bertrand Parvais
FinFET RF receiver building blocks operating above 10 GHz. 360-363 - Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Marc Tiebout, Michael Fulde, Pierpaolo Palestri:
Assessment of the impact of technology scaling on the performance of LC-VCOs. 364-367 - L. Gerrer, Gérard Ghibaudo, G. Ribes:
Oxide Soft Breakdown : From device modeling to small circuit simulation. 368-371 - Ali Kiaei, Mounir Bohsali, Ahmad Bahai, Thomas H. Lee:
A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector. 372-375 - Salam Elahmadi, Matthias Bussmann, Jomo Edwards, Kelvin Tran, Lloyd F. Linder, Christopher A. Gill, Harry Tan, Devin Ng, Dalius Baranauskas, Denis Zelenin:
An 11.1Gbps analog PRML receiver for EDC of up to 400km-reach WDM fiber-optic links. 376-379 - Takashi Kawamoto, Tomoaki Takahashi, Shigeyuki Suzuki, Takayuki Noto, Katsushi Asahina:
Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application. 380-383 - George von Büren, David Barras, Heinz Jäckel, Alex Huber, Christian Kromer, Marcel A. Kossel:
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL. 384-387 - Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng:
Designing ultra-low voltage PLL Using a bulk-driven technique. 388-391 - Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. 392-395 - Valentijn De Smedt
A 0.4-1.4V 24MHz fully integrated 33µW, 104ppm/V supply-independent oscillator for RFIDs. 396-399 - Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, Jinwook Oh, Hoi-Jun Yoo:
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor. 400-403 - Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. 404-407 - Matthias Korb, Tobias G. Noll:
Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures. 408-411 - Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee:
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. 412-415 - Mohamad Rahal, Andreas Demosthenous
An integrated common-mode feedback topology for multi-frequency bioimpedance imaging. 416-419 - Liu Liu, Jürgen Wünschmann, Naser Pour Aryan, Amr Zohny, Michael Fischer, Steffen Kibbel, Albrecht Rothermel:
An ambient light adaptive subretinal stimulator. 420-423 - Vahid Majidzadeh, Alexandre Schmid
A fully on-chip LDO voltage regulator for remotely powered cortical implants. 424-427 - Lucio Pancheri
A SPAD-based pixel linear array for high-speed time-gated fluorescence lifetime imaging. 428-431 - Rachid El Waffaoui, Simon Lee:
A 5.8GHz LC-based digitally controlled oscillator with 20kHz frequency resolution and 37 % tuning range. 432-435 - Takahiro Nakamura, Toru Masuda, Nobuhiro Shiramizu, Akihiro Nakamura, Katsuyoshi Washio:
A 20-GHz 1-V VCO with dual-transformer configuration and a pseudo-static divider on self-stabilized concept. 436-439 - Yuka Kobayashi, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu:
A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS. 440-443 - Stefano Dal Toso, Andrea Bevilacqua
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. 444-447 - Jinhua Ni, Zhiliang Hong, Bill Yang Liu:
Improved on-chip components for integrated DC-DC converters in 0.13 µm CMOS. 448-451 - Massimiliano Belloni, Edoardo Bonizzoni, Franco Maloberti:
High efficiency DC-DC buck converter with 60/120-MHz switching frequency and 1-A output current. 452-455 - Ping-Ching Huang, Wei-Quan Wu, Hsin-Hsin Ho, Ke-Horng Chen
High efficiency buck-boost converter with reduced average inductor current (RAIC) technique. 456-459 - Yasuhiro Sugimoto:
A MOS current-mode buck DC-DC Converter with a 240-kHz loop bandwidth and unaltered frequency characteristics using a quadratic and input-voltage-dependent compensation slope. 460-463 - Paul Veldhorst, George Goksun, Anne-Johan Annema
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. 464-467 - Jae-Won Nam
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. 468-471 - Lei Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren:
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. 472-475 - Trevor C. Caldwell, David A. Johns:
An 8th-order MASH delta-sigma with an OSR of 3. 476-479
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