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Ralph K. Cavin III
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2010 – 2019
- 2018
- [j37]Rafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III
, Sami Issa, Marco Iansiti:
Nurturing the Growth of a National Infrastructure in Emerging Technologies. Proc. IEEE 106(7): 1126-1131 (2018) - 2012
- [j36]Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov:
Prolog to the Section on Science and Engineering Beyond Moore's Law. Proc. IEEE 100(Centennial-Issue): 1718-1719 (2012) - [j35]Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov:
Science and Engineering Beyond Moore's Law. Proc. IEEE 100(Centennial-Issue): 1720-1749 (2012) - 2010
- [j34]George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida:
Nanoelectronics Research for Beyond CMOS Information Processing. Proc. IEEE 98(12): 1986-1992 (2010) - [j33]Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida:
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. Proc. IEEE 98(12): 1993-2004 (2010) - [j32]Kerry Bernstein, Ralph K. Cavin III, Wolfgang Porod, Alan C. Seabaugh
Device and Architecture Outlook for Beyond CMOS Switches. Proc. IEEE 98(12): 2169-2184 (2010) - [j31]Victor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel
Memory Devices: Energy-Space-Time Tradeoffs. Proc. IEEE 98(12): 2185-2200 (2010)
2000 – 2009
- 2009
- [c15]Victor V. Zhirnov, Ralph K. Cavin III:
Scaling beyond CMOS: Turing-Heisenberg Rapproachment. ESSCIRC 2009: 16-22 - 2008
- [j30]Victor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis:
An Assessment of Integrated Digital Cellular Automata Architectures. Computer 41(1): 38-44 (2008) - [j29]James A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff:
Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. Computer 41(5): 28-32 (2008) - [j28]Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff:
Emerging Research Architectures. Computer 41(5): 33-37 (2008) - [j27]George Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov:
Boolean Logic and Alternative Information-Processing Devices. Computer 41(5): 38-46 (2008) - [c14]Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III:
The Viability of Cellular Automata Architectures for General Purpose Computing. ERSA 2008: 321-333 - 2006
- [j26]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. IEEE J. Solid State Circuits 41(2): 461-473 (2006) - 2005
- [c13]Ralph K. Cavin III, Victor V. Zhirnov:
Future devices for information processing. ESSCIRC 2005: 7-12 - 2004
- [j25]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 876-880 (2004) - 2003
- [j24]Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff:
Limits to binary logic switch scaling - a gedanken model. Proc. IEEE 91(11): 1934-1939 (2003) - [j23]Ralph K. Cavin III, William H. Joyner Jr., Virginia C. Wiggins:
A semiconductor industry perspective on future directions in ECE education. IEEE Trans. Educ. 46(4): 463-466 (2003) - [j22]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Current-mode signaling in deep submicrometer global interconnects. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 406-417 (2003) - [c12]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Low-power design methodology for an on-chip bus with adaptive bandwidth capability. DAC 2003: 628-633 - [c11]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. ISCAS (5) 2003: 169-172 - 2002
- [c10]Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Delay and power model for current-mode signaling in deep submicron global interconnects. CICC 2002: 513-516 - 2000
- [j21]Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III:
Integrated parametric timing optimization of digital systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 482-489 (2000)
1990 – 1999
- 1997
- [j20]Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
The delay vernier pattern generation technique. IEEE J. Solid State Circuits 32(4): 551-562 (1997) - [j19]Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III:
A CMOS high-speed data recovery circuit using the matched delay sampling technique. IEEE J. Solid State Circuits 32(10): 1588-1596 (1997) - [j18]Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. J. VLSI Signal Process. 16(2-3): 131-147 (1997) - 1995
- [c9]Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. ARVLSI 1995: 131-149 - [c8]Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray:
Concurrent timing optimization of latch-based digital systems. ICCD 1995: 680-685 - [c7]Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. ISCAS 1995: 405-408 - 1994
- [j17]C. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh:
Circuit delay calculation considering data dependent delays. Integr. 17(1): 1-23 (1994) - [j16]C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III:
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. IEEE J. Solid State Circuits 29(3): 340-349 (1994) - [j15]Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III:
A 250-MHz wave pipelined adder in 2-μm CMOS. IEEE J. Solid State Circuits 29(9): 1117-1128 (1994) - [j14]C. Thomas Gray, Wentai Liu, Ralph K. Cavin III:
Timing constraints for wave-pipelined systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 987-1004 (1994) - 1993
- [j13]Wentai Liu, Su-Shing Chen, Ralph K. Cavin III:
A bit-serial VLSI architecture for generating moments in real-time. IEEE Trans. Syst. Man Cybern. 23(2): 539-546 (1993) - 1991
- [c6]C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III:
Theoretical and Practical Issues in CMOS Wave Pipelining. VLSI 1991: 397-409 - 1990
- [j12]Ralph K. Cavin III, Jeffrey L. Hilbert:
Design of integrated circuits: directions and challenges. Proc. IEEE 78(2): 418-435 (1990) - [c5]C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III:
The design of a high-performance scalable architecture for image processing applications. ASAP 1990: 722-733 - [c4]C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III, Su-Shing Chen:
P3A: a partitionable parallel/pipeline architecture for real-time image processing. ICPR (2) 1990: 529-531
1980 – 1989
- 1989
- [j11]Ralph K. Cavin III, Larry W. Sumney, Robert M. Burger:
The Semiconductor Research Corporation: Cooperative research. Proc. IEEE 77(9): 1327-1344 (1989) - [j10]Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III:
Hamiltonian Cycles in the Shuffle-Exchange Network. IEEE Trans. Computers 38(5): 745-750 (1989) - 1988
- [j9]Wentai Liu, Ralph K. Cavin III:
Rasterization theory, architectures, and implementations for a class of two-dimensional problems. Integr. 6(2): 179-199 (1988) - [c3]Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III:
Bit-level concurrency in real-time geometric feature extractions. CVPR 1988: 957-962 - [c2]Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III:
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. ISCA 1988: 167-174 - 1986
- [j8]William C. Holton, Ralph K. Cavin III:
A perspective on CMOS technology trends. Proc. IEEE 74(12): 1646-1668 (1986) - 1984
- [j7]Robert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney:
The Impact of ICs on Computer Technology. Computer 17(10): 88-95 (1984) - [c1]Ralph K. Cavin III:
Introduction to the SRC design sciences program. DAC 1984: 216-217 - 1983
- [j6]Ralph K. Cavin III, Noel R. Strader:
Microelectronic architectures and devices for signal and symbol processing. Integr. 1(4): 283-304 (1983) - 1982
- [j5]Stephen K. Jones, Ralph K. Cavin III, William M. Reed:
Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes. IEEE Trans. Inf. Theory 28(2): 318-329 (1982) - 1980
- [j4]Stephen K. Jones, Ralph K. Cavin III, Donald A. Johnston:
An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities. IEEE Trans. Commun. 28(12): 2019-2020 (1980)
1970 – 1979
- 1977
- [j3]Ralph K. Cavin III, S. C. Tandon:
Distributed parameter system optimum control design via finite element discretization. Autom. 13(6): 611-614 (1977) - [j2]Stephen K. Jones, Ralph K. Cavin III:
Dynamic Modeling and Control of Digital Communication Networks. Computer 10(11): 60-64 (1977) - [j1]Stephen K. Jones, Ralph K. Cavin III, J. N. Holyoak:
On the Maximum Average Throughput Rate for a Tandem Node Network. IEEE Trans. Commun. 25(10): 1240-1242 (1977)
Coauthor Index
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