default search action
28th ETS 2023: Venezia, Italy
- IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023. IEEE 2023, ISBN 979-8-3503-3634-4
- Jiaoyan Yao, Ying Zhang, Yifeng Hua, Yuanxiang Li, Jizhong Yang, Xin Chen:
Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP. 1-4 - Hanzhi Xun, Moritz Fieback
, Sicong Yuan, Ziwei Zhang, Mottaqiallah Taouil, Said Hamdioui:
Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs. 1-6 - Tobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwörer, Matteo Sonza Reorda
Constraint-Based Automatic SBST Generation for RISC-V Processor Families. 1-6 - Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin:
DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. 1-6 - Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. 1-6 - Zaheer Tabassam, Andreas Steininger:
SET Effects on Quasi Delay Insensitive and Synchronous Circuits. 1-6 - Nikolaos Ioannis Deligiannis, Tobias Faller, Chenghan Zhou, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing. 1-5 - Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hybrid Ring Generators for In-System Test Applications. 1-6 - Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi:
BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering. 1-6 - Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. 1-10 - Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Görschwin Fey:
FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. 1-4 - Francesco Lorenzelli
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. 1-6 - Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. 1-6 - Soyed Tuhin Ahmed, Roman Rakhmatullin, Mehdi B. Tahoori:
Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local Approximation. 1-4 - Yi He, Yanjing Li:
Understanding Permanent Hardware Failures in Deep Learning Training Accelerator Systems. 1-6 - Moritz Fieback
Online Fault Detection and Diagnosis in RRAM. 1-6 - Giorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, Pierre Scaramuzza, Rudolf Ullmann:
Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip. 1-6 - Fernando Fernandes dos Santos, Luigi Carro, Paolo Rech:
Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation. 1-10 - Bruno E. Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis, Marco Ottavi
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? 1-6 - Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee:
Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression. 1-6 - Denis Schwachhofer
Automating Greybox System-Level Test Generation. 1-4 - Brojogopal Sapui, Jonas Krautter, Mahta Mayahinia, Atousa Jafari, Dennis Gnad, Sergej Meschkov
Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies. 1-6 - Peter Domanski, Dirk Pflüger, Raphaël Latty:
Learn to Tune: Robust Performance Tuning in Post-Silicon Validation. 1-4 - Alperen Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik
DEV-PIM: Dynamic Execution Validation with Processing-in-Memory. 1-6 - Stefan Holst, Ruijun Ma
BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell. 1-6 - Jayeeta Chaudhuri, Krishnendu Chakrabarty:
Criticality Analysis of Ring Oscillators in FPGA Bitstreams *. 1-4 - Deniz Kasap, Alessio Carpegna, Alessandro Savino
Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study. 1-5 - Ching-Yuan Chen, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors. 1-4 - Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys:
harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs. 1-6 - Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Semi-Supervised Deep Learning for Microcontroller Performance Screening. 1-6 - Xhesila Xhafa, Patrick Girard, Arnaud Virazel:
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. 1-2 - Gabriele Gavarini, Annachiara Ruospo, Ernesto Sánchez:
SCI-FI: a Smart, aCcurate and unIntrusive Fault-Injector for Deep Neural Networks. 1-6 - Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li:
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. 1-6 - Annachiara Ruospo, Gabriele Gavarini, A. Porsia
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs. 1-6 - Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, C. Dominguez, Maria Angeles Jalón, L. Carranza:
A Single-Event Latchup setup for high-precision AMS circuits. 1-6 - Josie E. Rodriguez Condia
Evaluating the Prevalence of SFUs in the Reliability of GPUs. 1-6 - Theofilos Spyrou, Haralampos-G. Stratigopoulos:
On-Line Testing of Neuromorphic Hardware. 1-6 - Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. 1-4 - Lorenzo Masciullo, Roberto Passerone, Francesco Regazzoni
Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing. 1-6 - Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen:
High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis. 1-4 - Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas
Harvesting Wasted Clock Cycles for Efficient Online Testing. 1-6 - Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler:
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. 1-6 - Upoma Das, M. Sazadur Rahman
PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates. 1-6 - Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi:
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. 1-6 - Anurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee:
A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural Networks. 1-4 - Yanning Ji, Ruize Wang, Kalle Ngo, Elena Dubrova, Linus Backlund:
A Side-Channel Attack on a Hardware Implementation of CRYSTALS-Kyber. 1-5 - Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, Milos Krstic
PULP Fiction No More - Dependable PULP Systems for Space. 1-10 - Athanasios Xynos, Vasileios Tenentes
SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. 1-6 - Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI. 1-4 - Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty:
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*. 1-6 - Marti Alonso, David Andreu, Ramon Canal, Stefano Di Carlo, Cristiano Pegoraro Chenet, Juanjo Costa, Andreu Girones, Dimitris Gizopoulos, Vasileios Karakostas, Beatriz Otero, George Papadimitriou, Eva Rodríguez, Alessandro Savino
Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective. 1-6 - Matthias Ludwig
Counterfeit Detection by Semiconductor Process Technology Inspection. 1-4 - Changming Cui, Tuanhui Xu, Haitao Fu, Junlin Huang:
Physical-aware Interconnect Testing and Repairing of Chiplets. 1-4 - Manil Dev Gomony
Dependability of Future Edge-AI Processors: Pandora's Box. 1-6 - Asimina Koutra, Vasileios Tenentes
High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications. 1-6 - S. L. Tweehuysen, G. L. A. Adriaans, M. Gomony:
Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model. 1-4 - Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand:
Approximate Communication: Balancing Performance, Power, Reliability, and Safety. 1-6 - Abhishek Kumar Mishra, Anup Das, Nagarajan Kandasamy:
Online Performance Monitoring of Neuromorphic Computing Systems. 1-4 - Ferhat Can Ataman
Mismatch Measurement for MIMO mm-Wave Radars via Simple Power Monitors. 1-6 - Ferhat Can Ataman
Global Tuning for System Performance Optimization of RF MIMO Radars. 1-4 - Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-20 00:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: