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CICC 1998: Santa Clara, CA, USA
- Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998. IEEE 1998, ISBN 0-7803-4292-5
- Byoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung:
MDSP-II: 16-bit DSP with mobile communication accelerator. 5-8 - T. Arivoli, Mark Bickerstaff, Philip J. Ryan, Tom McDermott, Neil Weste, David J. Skellern, Terence M. Percival:
A single chip DMT modem for high-speed WLANS. 9-11 - Wolfgang Wilhelm, A. Kaufmann, Tobias G. Noll:
A new scalable VLSI architecture for Reed-Solomon decoders. 13-16 - Manfred Stadler, Markus Thalmann, Thomas Röwer, Norbert Felber, Wolfgang Fichtner:
An embedded stack microprocessor for SDH telecommunication applications. 17-20 - Behzad Razavi:
CMOS technology characterization for analog and RF design. 23-30 - Rafael Fried, Christian C. Enz:
Nano-amp, active-bulk, weak-inversion analog circuits. 31-34 - Jeff Kotowski, Bill McIntyre, John Parry:
Current sensor IC provides 9 bit+sign result without external sense resister. 35-38 - Qiuting Huang:
On the exact design of RF oscillators. 41-44 - Alper Demir, Amit Mehrotra, Jaijeet Roychowdhury:
Phase noise and timing jitter in oscillators. 45-48 - Ali Hajimiri
, Sotirios Limotyrakis, Thomas H. Lee:
Phase noise in multi-gigahertz CMOS ring oscillators. 49-52 - Bart De Smedt, Georges G. E. Gielen
Nonlinear behavioral modeling and phase noise evaluation in phase locked loops. 53-56 - Tajinder Manku:
Microwave CMOS-devices and circuits. 59-66 - Qiuting Huang, Paolo Orsatti, Francesco Piazza:
Broadband, 0.25 μm CMOS LNAs with sub-2dB NF for GSM applications. 67-70 - Marcial Chua, Ken W. Martin:
1 GHz programmable analog phase shifter for adaptive antennas. 71-74 - Johan Janssens, Jan Crols, Michiel Steyaert
A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications. 75-78 - Marc Borremans, Michiel Steyaert
A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications. 79-82 - Drew Wingard, Alex Kurosawa:
Integration architecture for system-on-a-chip design. 85-88 - Abdelhalim El-Aboudi, El Mostapha Aboulhamid, Eduard Cerny:
Synthesis of interface controllers from timing diagram specifications. 89-92 - Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. 93-96 - Enrica Filippi, L. Licciardi, Archille Montanaro, Maurizio Paolini, Maura Turolla, M. Taliercio:
The virtual chip set: a parametric IP library for system-on-a-chip design. 97-100 - E. Liu, C. Wong, Q. Shami, S. Mohapatra, R. Landy, P. Sheldon, G. Woodward:
Complete mixed-signal building blocks for single-chip GSM baseband processing. 101-104 - Ali Benkhalil, Stanley S. Ipson, William Booth:
A novel CPLD based implementation of a motion detection algorithm for surveillance applications. 105-108 - Marlene Wan, Yuji Ichikawa, David Lidsky, Jan M. Rabaey:
An energy conscious methodology for early design exploration of heterogeneous DSPs. 111-117 - M. Alidina, G. Burns, C. Holmqvist, E. Morgan, Douglas Rhodes, S. Simanapalli, M. Thierbach:
DSP16000: a high performance, low-power dual-MAC DSP core for communications applications. 119-122 - Takashi Shikata, Shinya Kondou, Masanori Nose, Yoshio Kuniyasu, Mutsuhiro Naitoh, Hidetaka Suzuki:
A single-chip low power DSP/RISC CPU with 0.25 μm CMOS technology. 123-126 - Bevan M. Baas:
A 9.5 mW 330 μsec 1024-point FFT processor. 127-130 - Shousheng He, Mats Torkelson:
Design and implementation of a 1024-point pipeline FFT processor. 131-134 - Michele Borgatti, Marco Felici, Alberto Ferrari, Roberto Guerrieri:
A 1 V, 25 μW speech recognizer for portable systems. 135-138 - Hiroshi Iwai:
CMOS-year 2010 and beyond; from technological side. 141-148 - Graham Pugh, John Canning
Impact of high resolution lithography on IC mask design. 149-153 - Kazutaka Mori, Ken'ichi Kikushima, Fumio Ootsuka, Shin'ichiro Mitani:
A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's. 155-158 - Isik C. Kizilyalli, R. Huang, D. Hwang, H. Vaidya, Brittin Kane, Robert Ashton, S. Kuehne, X. Deng, M. Twiford, David Shuttleworth, E. Martin, X. Li, M. J. Thoma:
A merged 2.5 V and 3.3 V 0.25-μm CMOS technology for ASICs. 159-162 - Joseph B. Bernstein, Wei Zhang, Carl H. Nicholas:
Laser formed connections for programmable wiring. 163-165 - Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi:
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. 169-172 - Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda:
Towards one chip HDTV MPEG2 encoder LSI. 173-176 - Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan:
An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution. 177-180 - S. Kamijo, Y. Wakimoto, Tomio Satoh, A. Sakurai, E. Gotoh, M. Nakajima:
A system LSI utilizing media processor core "MMA". 181-184 - R. Yamaguchi, A. Sota, M. Iwasa, M. Meiarashi, H. Ishii, M. Motohama, Dai Kitamoto
A single chip AV decoder for the DVD player adopting the MCP architecture. 185-188 - Christiane Henning, Tobias G. Noll:
Architecture and implementation of a bitserial sorter for weighted median filtering. 189-192 - Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Takao Onoye, Isao Shirakawa:
Implementation of H.324 audiovisual codec for mobile computing. 193-196 - Zhijiang He, Lawrence T. Pileggi:
A simple algorithm for calculating frequency-dependent inductance bounds. 199-202 - Bruno Franzini, Cristiano Forzan, Davide Pandini, Y. Liu, Carlo Guardiani:
Nonlinear macromodels of large coupled interconnect networks. 203-206 - Zhaojun Bai, Peter Feldmann, Roland W. Freund:
How to make theoretically passive reduced-order models passive in practice. 207-210 - Sharad Kapur, David E. Long, Jinsong Zhao:
Efficient full-wave simulation in layered, lossy media. 211-214 - Paolo Miliozzi, Mishel Matloubian, Mark Tennyson:
Systematic calibration of AC MOSFET model parameters including non-quasi-static effect. 215-217 - David R. Pehlke, Michael Schroter, A. Burstein, Mishel Matloubian, M. Frank Chang:
High-frequency application of MOS compact models and their development for scalable RF model libraries. 219-222 - Tao Shui, Richard Schreier, Forrest Hudson:
Modified mismatch-shaping for continuous-time delta-sigma modulators. 225-228 - Arnold R. Feldman, Bernhard E. Boser, Paul R. Gray:
A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applications. 229-232 - Subhajit Sen, Bosco Leung:
A 150 MHz 13b 12.5 mW IF digitizer. 233-236 - David X. D. Yang, Boyd Fowler, Abbas El Gamal:
A Nyquist rate pixel level ADC for CMOS image sensors. 237-240 - Dagnachew Birru, Engel Roza:
Video-rate D/A converter using reduced rate sigma-delta modulation. 241-244 - Nicholas van Bavel:
A 325 MHz 3.3 V 10-bit CMOS D/A converter core with novel latching driver circuit. 245-248 - Anne Van den Bosch, Marc Borremans, Jan Vandenbussche, Geert Van der Plas
A 12 bit 200 MHz low glitch CMOS D/A converter. 249-252 - Schuyler Shimanek, Cesar Maldonado, Victor Ruybalid, Roy Darling:
A low power, high performance, 960 macrocell, SRAM based complex PLD. 255-260 - Alireza Kaviani, Daniel Vranesic, Stephen Dean Brown:
Computational field programmable architecture. 261-264 - Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner:
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. 265-268 - Steven J. E. Wilton:
Implementing logic in FPGA embedded memory arrays: architectural implications. 269-272 - Chiakang Sung, Richard Cliff, Joseph Huang, Bonnie Wang, Khai Nguyen, Xtaobao Wang, Kerry Veenstra, Bruce Pedersen, John Turner:
A silicon efficient FLEX 6000 programmable logic architecture. 273-276 - X. Quan, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
A current-mode based field programmable analog array architecture for signal processing applications. 277-280 - Richard C. Foss, J. Wu, J. Benzreba, G. Valcourt, P. Vlasenko, Y. Wang, Peter Gillingham:
Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power. 283-286 - Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata:
A DRAM module generator with an expandable cell array scheme. 287-290 - Shunzo Yamashita, Naoki Katoh, Yasuhiko Sasaki, Yohei Akita, Hidetoshi Chikata, Kazuo Yano:
Hole filling: a novel delay reduction technique using selector logic. 291-294 - Edoardo Charbon:
Hierarchical watermarking in IC design. 295-298 - John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak:
FPGA fingerprinting techniques for protecting intellectual property. 299-302 - Binay Ackalloor, Dinesh Gaitonde:
An overview of library characterization in semi-custom design. 305-312 - Robert Macys, Steven McCormick:
A new algorithm for computing the "effective capacitance" in deep sub-micron circuits. 313-316 - Daniel Coops, Josef Watts, Charles Windisch Jr:
Timing qualification of a 0.25-μm CMOS ASIC library using BSIM3 FET models. 317-320 - Hans T. Heineken, Jitendra Khare, Manuel d'Abreu:
Manufacturability analysis of standard cell libraries. 321-324 - Satoshi Shibatani, Toshiyuki Sadakane, Hiroomi Nakao, Masayuki Terai, Kaoru Okazaki:
A CMOS cell generation system for two-dimensional transistor placement. 325-328 - Andrew G. Marshall, Tom Schmidt, Bill Grose, Wayne Chen:
Standard cell power IC design. 329-332 - Mehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt:
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers. 335-342 - Joseph N. Babanezhad:
A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication. 343-346 - Keith T. Oshiro, Gregory T. Uehara, Aaron K. Oki, Ben Tang:
A 10-Gbps 83 mW GaAs HBT equalizer/detector for coaxial cable channels. 347-350 - Lionel J. D'Luna, Paul Yang, Dean W. Mueller, Kelly B. Cameron, Huan-Chang Liu, David Gee, Fang Lu, Robert A. Hawley, Steve Tsubota, Charles Reames, Henry Samueli:
A dual-channel QAM/QPSK receiver IC with integrated cable set-top box functionality. 351-354 - Mario Diu-Nava, Sergio Zocchi, Laurent Dugoujon, Didier Belot, Pierre Delerue, Sébastien Dedieu, Mourad Messaou:
1.5 watt 622/155 Mbps single chip for full ATM-SDH/SONET physical layer in 0.5 μm BiCMOS 3.3 V. 355-358 - Ramsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot:
A multistage amplifier topology with embedded tracking compensation. 361-364 - Konstantinos Manetakis, Chris Toumazou, Christos Papavassiliou:
A 120 MHz, 12 mW CMOS current feedback opamp. 365-368 - Christian Menolfi, Qiuting Huang:
A CMOS instrumentation amplifier with 600 nV offset, 8.5 nV/⎷(Hz) noise and 150 dB CMRR. 369-372 - Zeki Sezgin Günay, Eric G. Soenen, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
A 1.8 V pseudo-differential switched-capacitor amplifier. 373-376 - Tristan Reimann, François Krummenacher, Michel J. Declercq:
A high-speed BiCMOS switched-current track-and-hold circuit. 377-380 - Khayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto:
An open-loop full CMOS 103 MHz -61 dB THD S/H circuit. 381-383 - Behzad Razavi:
Architectures and circuits for RF CMOS receivers. 393-400 - Dominique Morche, Denis Pache, Ernesto Perea, Patrice Senn:
A high Q 200 MHz low-power fully integrated bandpass IF filter. 401-404 - Giovanni Calí, Pietro Erratico, Massimo Gimignani, Piero Vita:
A VLSI low power solution for mobile satellite radio receivers. 405-408 - Jan Sevenhans, Bart Verstraeten, Graham Fletcher, Harry Dietrich, Winfried Rabe, Jean Luc Bacq, J. Varin, J. Dulongpont:
Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration. 409-412 - Francesco Piazza, Paolo Orsatti, Qiuting Huang, T. Morimoto:
A 0.25 μm CMOS transceiver front-end for GSM. 413-416 - Maher Kayal, R. T. Lara Sáez, Michel J. Declercq:
An automatic offset compensation technique applicable to existing operational amplifier core cell. 419-422 - Vittorio Comino, Dima Shulman, Susan J. Walker, Sanjay Kasturia, Michael E. Prise:
A baseband integrated circuit for homodyne cordless phones. 423-426 - Yong Wang, Gregory T. Uehara, Min Ren:
A 3-V high-bandwidth integrator for magnetic disk read channel continuous-time filtering applications. 427-430 - Robert E. Jones:
Ferroelectric nonvolatile memories for embedded applications. 431-438 - Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi
An embedded FeRAM macro cell for a smart card microcontroller. 439-442 - Georges G. E. Gielen
Modeling and simulation for low power in mixed-signal integrated systems. 445-449 - Jaijeet Roychowdhury:
MPDE methods for efficient analysis of wireless systems. 451-454 - Supratik Chakraborty
Practical timing analysis of asynchronous circuits using time separation of events. 455-458 - I. Yusim, G. Ionis, Ken Suyama:
Simulator for switched-current integrated circuits. 459-462 - Chuanjin Richard Shi, Xiang-Dong Tan:
Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits. 463-466 - Francky Leyn, Willy Sansen, Georges G. E. Gielen
Transforming small-signal modeling into control system modeling. 469-472 - Jan Vandenbussche, Geert Van der Plas, Georges G. E. Gielen
Behavioral model for D/A converters as VSI virtual components. 473-476 - Ian O'Connor, Andreas Kaiser:
Automated design of switched-current cells. 477-480 - Ravindranath Naiknaware, Terri S. Fiez:
Schematic driven module generation for analog circuits with performance optimization and matching considerations. 481-484 - Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen
Mondriaan: a tool for automated layout synthesis of array-type analog blocks. 485-488 - Frank Herzel, Behzad Razavi:
Oscillator jitter due to supply and substrate noise. 489-492 - Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda:
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. 495-498 - Ram Krishnamurthy, Herman Schmit, L. Richard Carley:
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques. 499-502 - Thierry Melly, Alain-Serge Porret, Christian C. Enz, Maher Kayal:
A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]. 503-506 - Zhanping Chen, Kaushik Roy, Yibin Ye:
Estimation of average switching power under accurate modeling of signal correlations. 507-510 - Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki:
The direct skew detect synchronous mirror delay (Direct SMD) for ASICs. 511-514 - Kamran Iravani, Gary Miller:
VCOs with very low sensitivity to noise on the power supply. 515-518 - Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel:
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. 519-522 - Peng Fang, Jiang Tao, Jone F. Chen, Chenming Hu:
Design in hot-carrier reliability for high performance logic applications. 525-531 - Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu:
Performance and reliability of asymmetric LDD devices and logic gates. 533-536 - Ming-Dou Ker, Jeng-Jie Peng:
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. 537-540 - Ming-Dou Ker, Hun-Hsien Chang:
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection. 541-544 - Shyh-Jye Jou, Wei-Chung Cheng, Yu-Tao Lin:
Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]. 545-548 - Benoit Dufort, Gordon W. Roberts:
On-chip analog signal generator for mixed-signal built-in self-test. 549-552 - A. Kral, Farbod Behbahani, Asad A. Abidi:
RF-CMOS oscillators with switched tuning. 555-558 - Joo Leong Tham, Mihai A. Margarit, Bernd Prégardier, Chris Hull, Rahul Magoon, Frank Carr:
A 2.7 V 900 MHz/1.9 GHz dual-band transceiver IC for digital wireless communication. 559-562 - Wei-Zen Chen, Jieh-Tsorng Wu:
A 2 V 1.6 GHz BJT phase-locked loop. 563-566 - Byeong-Ha Park, Phillip E. Allen:
A 1 GHz, low-phase-noise CMOS frequency synthesizer with integrated LC VCO for wireless communications. 567-570 - Steve Lo, Christian Olgaard, Dennis Rose:
A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications. 571-574 - German Gutierrez, Shyang Kong, Bruce Coy:
2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48). 575-578 - W. Terry Coston:
Issues for fabless design companies moving towards deep submicron system on a chip design. 581-587 - Hema Kapadia, Giovanni De Micheli, Luca Benini:
Reducing switching activity on datapath buses with control-signal gating. 589-592 - Keith M. Carrig, Niel T. Gargiulo, Roger P. Gregor, Daniel R. Menard, Harold E. Reindel:
A new direction in ASIC high-performance clock methodology. 593-596 - Yamin Du, Anthony Vannelli:
A nonlinear programming and local improvement method for standard cell placement. 597-600 - Hiroshi Shirota, Toshiyuki Sadakane, Masayuki Terai, Kaoru Okazaki:
A new router for reducing "antenna effect" in ASIC design. 601-604 - Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim:
Combined transistor sizing with buffer insertion for timing optimization. 605-608
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