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Brad Vest
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2010 – 2019
- 2015
- [c6]Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. CICC 2015: 1-8 - 2014
- [c5]Brad Vest, Sean Atsatt, Mike Hutton:
Design of a high-density SoC FPGA at 20nm. Hot Chips Symposium 2014: 1-24
2000 – 2009
- 2004
- [c4]Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis:
MAX II: A low-cost, high-performance LUT-based CPLD. CICC 2004: 443-446 - 2003
- [c3]Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello:
Cyclone ™: a low-cost, high-performance FPGA. CICC 2003: 49-52
1990 – 1999
- 1999
- [c2]Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello:
A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming. CICC 1999: 187-190 - 1998
- [c1]Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner:
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. CICC 1998: 265-268
Coauthor Index
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