Revisit: Resistance and Capacitance MOSFET Model For Digital Circuits

Revisit: Resistance and Capacitance
MOSFET Model for Digital Circuits

Reference:
Baker (Estimation)
Kang (Analytical)
Noise Margin Revisited
Figure plots the simulated VTC of the inverter, as well as its derivative, the gain.
Effective Switching Resistance Revisited
Long-channel (scale factor is 1 um)
Short-channel (scale factor of 50 nm) CMOS process

Capacitive Effects
Careful about Notation
• NOTE:
We followed the nomenclature for Gate
capacitance . Where is the gate capacitance and is
equal to oxide capacitance per unit area multiplied
by area.
=
• In this slide, gate capacitance is referred whereas
oxide capacitance per unit is denoted by
Miller Capacitance
If, initially, the input node is at 0 V and the output node is at

VDD, the charge on the capacitor is
If the input node changes to VDD and the output node transitions to
ground, the charge on the capacitor is
The total charge supplied by the input or output voltage source to
the capacitor after the transition is then
Here the input source makes a transition from 0 to VDD while,

at the same time, the output source transitions from VDD to 0.
what is the effective capacitance that each source sees?
the input source supplies a charge of
While the output sinks the same amount of charge
The point here is that the input or output capacitance of the

circuits is twice the capacitance value connecting the input to
the output.
Consider the MOSFET circuit
when the input pulse transitions from 0 to VDD, the
output transitions from VDD to 0
The voltage across Cgd changes by 2VDD
As seen through Miller effect , we can break Cgd into a component

from the gate to ground and from the drain to ground of value
2Cgd or Cox.
Capacitance Values
Time Constant: Process Characteristic (Unit Length)
• Long-channel CMOS process,
Effective switching resistance of the PMOS device is three times as

large as the resistance of the NMOS device, we can write
Time Constant: Process Characteristic (Unit Length)
• For the short-channel process

Delay and Transition Times: Definitions
• Propagation delay time, tP = maximum time

from the input crossing 50% to the output
crossing 50%
• Rise time, tr = time for a waveform to rise from
10% to 90% of its steady-state value
• Fall time, tf = time for a waveform to fall from
90% to 10% of its steady-state value
• Edge rate, trf = (tr + tf )/2
Delay and Transition Times
Approach to estimate DELAY
• we can write differential equations for voltage as a function of
time to calculate delay.
• Unfortunately, these equations are too complicated.
• Here we focuses on developing simpler models that offer the

designer more intuition.
• The RC delay model approximates a switching transistor with an

effective resistance and provides a way to estimate delay using
arithmetic rather than differential equations.
Figure shows a simple RC circuit driven from a voltage pulse. If
the input pulse transitions from 0 to V pulse at a time which
we'll call zero, then the voltage across the capacitor (the
output voltage) is given by
The time it takes the output of the RC circuit to reach
50% of Vpulse be (defined as the circuit's delay time) is
determined using
• Every real circuit has some capacitance. In an
integrated circuit, it typically consists of the
1. Gate capacitance of the load
2. Diffusion capacitance of the driver’s own
transistors
3. Cgd Capacitance
RC Delay Model: Inverter
The effective input capacitance of the inverter is
The effective output capacitance of the inverter is
The propagation delays of the inverter are

Example: Estimate the intrinsic propagation delays of the
inverter (having short channel process) shown in Fig. Also
estimate the inverter's input capacitance.
Example : Estimate and simulate the propagation delays for the circuit seen in
Fig. Use the 180 nm CMOS process.
Draw the equivalent RC Series circuit
(a)
(b)
Calculation of Delay Times ( and (
High-to-low ( Transition:
The, input and output voltage waveforms during this high-to-low ( transition are
illustrated in figure.
When the NMOS transistor starts conducting, it initially operates in the saturation region.
When the output voltage falls below (VDD - VT), the NMOS transistor starts to conduct in the
linear region.
First, consider the NMOS transistor operating in saturation
The differential equation describing the discharge event is

Evaluating this simple integral yields
(1)
At t = t1', the output voltage will be equal to (VDD - VTn) and the transistor will be at
the saturation-linear region boundary.
Next, consider the NMOS transistor operating in the linear region.

Evaluating this integral yields
(2)
Combining eq. (1) and (2) as
For VOH = VDD and VOL= 0, as is the case for the CMOS inverter,
Similarly,
All of the delay time derivations in this section were made

under the simplifying assumption that the input signal
waveform is a step pulse with zero rise and fall times.
Reading Assignment
Derive the analytical expressions for low to high

and high to low propagation delay.
Ref: Kang
Logical Effort
• The method of Logical Effort simplifies the
model even further and is a powerful way to
evaluate delay in circuits.

Revisit: Resistance and Capacitance MOSFET Model For Digital Circuits

Uploaded by

Copyright:

Available Formats

Revisit: Resistance and Capacitance MOSFET Model For Digital Circuits

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Revisit: Resistance and Capacitance MOSFET Model For Digital Circuits

Uploaded by

Copyright:

Available Formats

Revisit: Resistance and Capacitance

MOSFET Model for Digital Circuits

Short-channel (scale factor of 50 nm) CMOS process

If, initially, the input node is at 0 V and the output node is at

Here the input source makes a transition from 0 to VDD while,

While the output sinks the same amount of charge

The point here is that the input or output capacitance of the

As seen through Miller effect , we can break Cgd into a component

• Long-channel CMOS process,

Effective switching resistance of the PMOS device is three times as

• For the short-channel process

• Propagation delay time, tP = maximum time

• Unfortunately, these equations are too complicated.

• Here we focuses on developing simpler models that offer the

• The RC delay model approximates a switching transistor with an

The effective output capacitance of the inverter is

The propagation delays of the inverter are

The differential equation describing the discharge event is

Next, consider the NMOS transistor operating in the linear region.

All of the delay time derivations in this section were made

Derive the analytical expressions for low to high

You might also like