Week2 Microprocessor Architecture
Week2 Microprocessor Architecture
Week2 Microprocessor Architecture
What is a Microcomputer
A complete computer based on a particular
microprocessor chip.
So the microprocessor is the most important
component in a microcomputer
So to study a microcomputer system, we
must first understand the microprocessor
What is a Microprocessor
Hard Disk
CD ROM
Keyboard, mouse
Monitor, printer
2
Microprocessor based
system
sensor
Input
uP with
Control program
motor
Output
Structure of a modern
computer system
Model
Year
8086
Max. Clock
frequency at
introduction
Transis Register
tors
Sizes
per Die
Ext.
data
bus
size
Max.
Caches
external
address
space
1978 8 MHz
29K
16GP
16
1MB
None
486
1989 25MHz
1.2M
32GP
80FPU
32
4GB
L1:8KB
Pentium
1993 60MHz
3.1M
32GP
80FPU
64
4GB
L1:16K
B
P3
1999 500MHz
8.2M
32GP
80FPU
64MMX
128 XMM
64
64GB
L1:32K
B
L2:
512KB
64
64GB
L2:
1MB
167 M
8086 Microprocessor
This is a 16-bit microprocessor chip
manufactured by high-performance
metal-oxide semiconductor (HMOS)
technology
Circuitry on chip is approximately
29,000 transistors
Comes in a 40-pin package
Self test
Do you know what does it mean by
16-bit, 32-bit, or 64-bit processor?
How would you describe an Intel
Core2 Duo CPU ?
10
8086 Features
The 8086 has two modes min. and
max.
Min. mode used as a typical
microprocessor
Max. mode use with multiple
processors, usually for floating-point
arithmetic)
The mode selection is via the MN/MX
input
11
memory
CPU
I/O
12
13
14
Terminology
Program is stored in memory and consists of a
sequence of instructions and some data
To execute an instruction it may require some
operands
What is an operand?
Operand is the object that is being operated
upon!
Example, in an instruction ADD A, B (A = A+B)
ADD (addition is the operation)
A and B are the operands
16
17
BIU
There is a full 16-bit bidirectional data bus
and 20-bit address bus
It has the following functions: instruction
fetch, instruction queueing, operand fetch
and storage, and bus control.
It contains the segment registers, internal
communication registers, instruction
pointer, instruction object code queue,
address summer (), and bus control logic.
18
19
BIU EU Pipeline
mechanism
Note: there are 3 components in the pipeline
Information
coming from memory
BIU
Control to access
the memory
EU
executes the instruction
queue that
can store 6 bytes
of instructions
EU requests BIU to get operands
20
Pre-fetch concept
Pre-fetching is similar to what you do when
youre having a buffet dinner.
You collect different kinds of food from the
buffet table, for example, you take the
sashimi, roast beef, soup, and salad etc.
When youre eating the salad, you have
already pre-fetched the sashimi and the
roast beef! If you do not pre-fetch then you
take the salad first, go back to the table, eat
your salad. When you finish the salad then
you go and get some other food.
Why pre-fetching your food??????
21
Pre-fetch
Is pre-fetching in a buffet dinner
exactly the same as the pre-fetching
mechanism in a microprocessor?
The plate is equivalent to which
component?
Is a big plate better than a small
plate?
22
Pre-fetch by BIU
Whats pre-fetch????
When the queue can store at least 2 bytes
EU is not requesting BIU to read or write operands
from memory
BIU will look ahead in the program by prefetching
the next sequential instruction
The prefetched instructions are held in the queue
which is a FIFO (First-in-first-out) device
Two bytes are fetched (16-bit data bus) in a single
memory cycle
EU will read one instruction byte from the output of
the queue
23
Pre-fetch
Int1a
Int1b
Int2a
Int2b
Int2c
Int3a
Int3b
Int4a
Memory
Queue
int1b int1a
EU
int1a
While EU is
processing int1a
Int2a and int2b have
already been
Pre-fetched
24
Instruction sequence
Fetch
Execute
Fetch
Execute
Fetch
Execute
25
Pre-fetching by BIU
If the instruction queue is full and EU is
not requesting access to operands in
memory, the BIU does not perform any
bus cycles this is called idle states
When BIU is in the process of fetching
an instruction when the EU requests its
services then BIU first completes the
instruction fetch bus cycle and then
serves the EU
26
27
28
Segment concept
29
Segment in 8086
Why segment mechanism is needed in
8086?
The address bus size (20-bit) > register size
(16-bit)
Example: if the address bus is 4 bits then you can
access 16 locations
If you can only output a 2-bit address from your
register then what will happen?
Segment concept
Segment analogy
It is similar to an estate
Instead of building a very tall
building, we build smaller blocks
If you live in one of the smaller
blocks then your address will have
two components the block number
(segment) and the floor (offset)
31
Segment concept
A 64k segment
1M
32
Segment Registers
The segment registers are used for accessing the
memory
The 8086 address space is segmented into 64Kbyte segments and just four segments can be
active at a time. Because there are only 4
segment registers
In theory, how many segments can we have????
Total memory 1M and segment is 64K so 1M/64K number
of segment
33
Memory
(a segment)
Offset
Segment concept
For example:
FFFFEH is not divisible by 16
FFFF0H is divisible by 16
12340H is also divisible by 16
35
Segment concept
The maximum value of a 16-bit value is FFFF (Hex), if two 16bit values added together, such as FFFF (segment) + FFFF
(offset), the result is 1FFFE (Hex) (physical) and it is only
a 17-bit value and values from 1FFFFH to FFFFFH
cannot be produced. As for a 20-bit pattern, it represents
values from 00000H - FFFFFH
Segment concept
The segment concept analogy
If you are design the elevator for a
very tall building, for example with
100 levels. How are you going to
arrange the buttons if the elevator
is able to reach all levels?
37
38
Decoding
Instruction
10101100
Decoder
Control
signals
39
Functions of EU
Functions of EU
If the instruction queue is empty, the EU
waits for the next instruction byte to be
fetched and shifted to the top of the
queue.
When the EU executes a branch or jump
instruction, it transfers control to a
location corresponding to another set of
sequential instructions. Whenever this
happens, the BIU automatically resets
the queue and then begins to fetch
instructions from this new location to
refill the queue.
42
43
Summary
What is the pre-fetch concept?
What is a pipeline and its advantage?
What are functions performed by the
BIU and EU
What is a multiplexed address/data
bus
What is the segment concept
44
45
46
Data Registers
4 general purpose data registers
and are used for temporary
storage of frequently used
intermediate results.
This can improve the speed
(why???)
Register can use either as 8-bit or
16-bit
Accumulator Register (AX: AH AL)
Base Register (BX: BH BL)
AX (16-bit)
Count Register (CX: CH CL)
AH (8-bit) AL (8-bit)
Data Register (DX: DH DL)
47
Data Registers
The general purpose data registers can be used
for arithmetic or logic operations
For example, to carry out an addition: add ax, bx
The result is stored in ax and it is equal to the
sum of values in ax and bx (in C, it is similar to
ax+=bx)
For string instruction, the CX register is used to
store a count value representing the number of
bytes to be moved
All I/O operations require data that are to be
input or output to be in the A register, while
register DX holds the address of the I/O port
48
Segment Registers
The segment registers are used for accessing the memory
The 8086 address space is segmented into 64K-byte
segments and just four segments can be active at a time.
In theory, how many segments can we have????
The segment registers are used to select the active segments
49
Segment Registers
(Contd)
Stack Segment (SS) Register
SS register contains a logical address that identifies
the starting location of the current stack segment
in memory. Stack is used for temporary storage
50
51
52
Pointer
CS (code segment)
IP (instruction pointer)
DS (data segment)
DI, SI
SS (Stack segment)
SP (stack pointer)
BP (base pointer)
ES (Extra segment)
DI
53
Flag Register
The flag register is a 16-bit register
within the execution unit. The
status flags in the register indicate
conditions that are produced as
the result of executing an
arithmetic or logic instruction.
What kind of conditions can you
think of???
54
55
Example
If our data is only 8-bit then when we
do FFH + 1H = 1 0000 0000 this is a
9-bit value the 1 is the carry!!!!
Similarly when we do 00H 1H then
result is 1 1111 1111 the 1 is the
borrow bit.
56
Flags
consider using 8-bit values A and B,
determine flag status for C, S, Z and O
If
If
If
If
If
If
A = 0FH, B = 1; A+B
A = 0, B = 1; A-B
A = 7FH, B = 1; A+B
A = 80, B = 0F; A-B
A = FFH, B = 1; A+B
A = 2FH, B = 60, C = -1; (A+C) -B
57
memory
CPU
I/O
58
Bus Cycle
Bus address and data
Bus cycle is used to access memory, I/O
devices, or the interrupt controller.
Bus cycle starts with an address being output
on the system bus followed by a read or write
data transfer.
A series of control signals are produced to
control the direction and timing of the bus
A standard bus cycle consists of 4 clock periods
Understand system bus timing will assist you to
choose the proper memory device
59
Bus cycle
T1 : BIU puts an address on the bus
T2: data are put on the bus (for write
cycle)
T2: bus in High Z mode (for read cycle)
T3: data on the bus
T4: data on the bus
For a 5MHz system, how long does it
take to complete 1 bus cycle????
60
Read cycle
61
Write cycle
62