Chapter I

An Introduction to Microprocessor architecture

Introduction to the Microprocessor and computer
Microprocessor: It is a semiconductor device consisting of electronic logic
circuits manufactured by using either a Large scale (LSI) or Very Large
Scale (VLSI) Integration Technique; it includes the ALU, register arrays and
control circuits on a single chip; it has a set of instructions, designed
internally, to manipulate data and to communicate with peripherals.
Architecture: This process of data manipulation and communication is
determined by the logic design of the microprocessor called the architecture.
The era microprocessors in the year 1971, the Intel introduced the first 4-bit
microprocessor is 4004. Using this first portable calculator is designed.
 The number of instructions on the 4004 microprocessor is 45,
The number of instructions on the 8085 microprocessor is 246,
The number of instructions on the 8086 and 8088 microprocessors is to well
over 20,000 variations.
Figure shows block diagram of a simple microprocessor-based computer
system.
The major parts are
1. the central processing unit or CPU,
2. memory and
3. the input and output circuitry or input/output.
The block diagram of a microprocessor-based computer system.
1. Central processing Unit (CPU): CPU controls the operation of
the computer .In a microcomputer the CPU is a
microprocessor.
The CPU fetches the binary coded instructions from memory,
decodes the instructions into a series of simple actions and carries
out these actions in sequence of steps.

CPU contains
An address counter or instruction pointer register which holds the
address of the next instruction or data item to be fetched from
memory,

General purpose registers, which are used for temporary storage

or binary data and circuitry, which generates the control bus
signals.
(i) Address bus: The address bus consists of 16, 20, 24, or 32
parallel lines.
• On these lines the CPU sends out the address of the memory
locations that are to be written to or read from.
• The number of memory locations that the CPU can address is
determined by the number of address lines n, then it can
directly address 2n memory locations.
• When the CPU reads data from or writes data to a port, it
sends the port address on the address bus.
Ex: CPU has 16 address lines can address 216 or 65536 memory
locations.
 
(ii) Data bus: It consists of 8, 16, 32 parallel signal lines.
The data bus lines are bidirectional. This means that the
CPU can read data from memory or from a port on these
lines, or it can send data out to memory or to port on
these lines.

 (iii) Control bus: The control bus consists of 4 to 10

parallel signals lines. The CPU sends out signals on the
control bus to enable the outputs of addressed memory
devices or port Input/output.
2. Memory: Memory section usually consists of a mixture of RAM
 

and ROM. It may also magnetic floppy disks, magnetic hard

 

disks or optical disks, to store the data.

 
3. Input/output: The input/output are peripherals such as
keyboards, video display terminals, printers, and modem. These
units allow the user and computer to communicate with each
other.
• The actual physical devices used to interface the computer
buses to external systems are often called ports.
• An input port allows data from keyboard, an analog to digital
converter (ADC) or some other source to be read into the
computer under the control of the CPU.
• An output port is used to send data from the computer to some
peripheral, such as a video display terminal, a printer, or a
digital to analog converter (DAC).
Architecture:
The internal architecture 8086 microprocessor is as
shown in the above figure. The 8086 CPU is divided
into two independent functional parts,
1) Bus interface unit (BIU) and
2) Execution unit (EU).

The Bus Interface Unit contains Bus Interface Logic,

Segment registers, Memory addressing logic and a Six
byte instruction object code queue.
The Execution unit contains the Data and Address
registers, the Arithmetic and Logic Unit, the Control
Unit and flags.
The BIU sends out address, fetches the instructions from memory,
read data from ports and memory, and writes the data to ports and
memory. In other words the BIU handles all transfers of data and
addresses on the buses for the execution unit.

The execution unit (EU) of the 8086 tells the BIU where to fetch
instructions or data from, decodes instructions and executes
instruction. The EU contains control circuitry which directs
internal operations.
• A decoder in the EU translates instructions
fetched from memory into a series of actions which the EU carries
out.
• The EU is has a 16-bit ALU which can add, subtract, AND, OR,
XOR, increment, decrement, complement or shift binary
numbers.
• The EU is decoding an instruction or executing an instruction
which does not require use of the buses.
The Queue: The BIU fetches up to 6 instruction bytes for the
following instructions.
• The BIU stores these pre fetched bytes in first-in-first-out
register set called a queue.
• When the EU is ready for its next instruction it simply reads the
instruction byte(s) for the instruction from the queue in the BIU.
• This is much faster than sending out an address to the system
memory and waiting for memory to send back the next
instruction byte or bytes.
• Except in the case of JMP and CALL instructions, where the
queue must be dumped and then reloaded starting from a new
address, this pre fetch-and-queue scheme greatly speeds up
processing.
• Fetching the next instruction while the current instruction
executes is called pipelining.
Word Read
• Each of 1 MB memory address of 8086 represents a byte wide
location.16-bit words will be stored in two consecutive memory
locations.
• If first byte of the data is stored at an even address, 8086 can
read the entire word in one operation.
• For example if the 16 bit data is stored at even address 00520H
is 9634H
MOV BX, [00520H]
• 8086 reads the first byte and stores the data in BL and reads
the 2nd byte and stores the data in BH
BL= (00520H) i.e. BL=34H
BH= (00521H) i.e. BH=96H
• If the first byte of the data is stored at an odd address, 8086
needs two operations to read the 16 bit data.
For example if the 16 bit data is stored at even address 00521H
is 3897H
MOV BX, [00521H]
• In first operation, 8086 reads the 16 bit data from the 00520H
location and stores the data of 00521H location in register BL
and discards the data of 00520H location.
• In 2nd operation, 8086 reads the 16 bit data from the 00522H
location and stores the data of 00522H location in register BH
and discards the data of 00523H location.
BL= (00521H) i.e. BL=97H
BH= (00522H) BH=38H
Byte Read:
MOV BH, [Addr]
For Even Address:
Ex: MOV BH, [00520H]
• 8086 reads the first byte from 00520 location and stores the data
in BH and reads the 2nd byte from the 00521H location and
ignores it
BH =[ 00520H]

For Odd Address

MOV BH, [Addr]
Ex: MOV BH, [00521H]
• 8086 reads the first byte from 00520H location and ignores it and
reads the 2nd byte from the 00521 location and stores the data in
BH
BH = [00521H]
Physical address formation:
• The 8086 addresses a segmented memory. The complete physical address
which is 20-bits long is generated using segment and offset registers each of
the size 16-bit.
• The content of a segment register also called as segment address, and
content of an offset register also called as offset address.
• To get total physical address, put the lower nibble 0H to segment address
and add offset address.
The fig shows formation of 20-bit physical address.

OFFSET VALUE and

SEGMENT REGISTER 0H

ADDER

20 BIT PHYSICAL ADDRESS

Register organization of 8086:
• 8086 has a powerful set of registers containing general purpose
and special purpose registers.
• All the registers of 8086 are 16-bit registers. The general
purpose registers, can be used either 8-bit registers or 16-bit
registers.
• The general purpose registers are either used for holding the
data, variables and intermediate results temporarily or for
other purpose like counter or for storing offset address for
some particular addressing modes etc.
• The special purpose registers are used as segment registers,
pointers, index registers or as offset storage registers for
particular addressing modes.
Fig. shows register organization of 8086. We will categorize the
register set into four groups as follows:
General data registers:
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH,
which can be combined together and used as a 16- bit register AX. AL in this case
contains the low-order byte of the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations, rotate and string manipulation.
BX Register: This register is mainly used as a base register. It holds the starting
base location of a memory region within a data segment. It is used as offset
storage for forming physical address in case of certain addressing mode.
CX Register: It is used as default counter or count register in case of string and
loop instructions.
DX Register: Data register can be used as a port number in I/O operations and
implicit operand or destination in case of few instructions. In integer 32-bit
multiply and divide instruction the DX register contains high-order word of the
initial or resulting number.
AX AH AL CS SP
BX BH BL SS FLAGS/PSW BP
CX CH CL DS IP
DX DH DL ES DI, SI
General data registers Segment registers Pointers and index registers
Segment registers:
To complete 1Mbyte memory is divided into 16 logical segments.
The complete 1Mbyte memory segmentation is as shown in fig 1.5.
Each segment contains 64Kbyte of memory. There are four segment
registers.
Code segment (CS) is a 16-bit register containing address of 64 KB
segment with processor instructions. The processor uses CS segment
for all accesses to instructions referenced by instruction pointer (IP)
register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return
instructions. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
Stack segment (SS) is a 16-bit register containing address of 64KB
segment with program stack. By default, the processor assumes that
all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed
directly using POP instruction. It is used for addressing stack
segment of memory. The stack segment is that segment of memory,
which is used to store stack data.
Data segment (DS) is a 16-bit register containing address of 64KB
segment with program data.
• By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI)
is located in the data segment.
• DS register can be changed directly using POP and LDS
instructions.
• It points to the data segment memory where the data is resided.
Extra segment (ES) is a 16-bit register containing address of 64KB
segment, usually with program data.
• By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions.
ES register can be changed directly using POP and LES
instructions.
• It also refers to segment which essentially is another data
segment of the memory. It also contains data.
Memory segmentation
Pointers and index registers.
• The pointers contain within the particular segments.
• The pointers IP, BP, SP usually contain offsets within the code,
data and stack segments respectively
Stack Pointer (SP) is a 16-bit register pointing to program
stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack
segment. BP register is usually used for based, based indexed or
register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed,
based indexed and register indirect addressing, as well as a source
data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing, as well as
a destination data address in string manipulation instructions.
Flag Register
Flags Register determines the current state of the processor.
They are modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and to
determine conditions to transfer control to other parts of the
program.
The 8086 flag register as shown in the fig. 8086 has 9 active flags
and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags

Carry Flag (CY): This flag indicates an overflow condition for

unsigned integer arithmetic. It is also used in multiple-precision
arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU

generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper
nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to
D4 is AC flag.
• This is not a general-purpose flag
Parity Flag (PF): This flag is used to indicate the parity
of result. If lower order 8-bits of the result contains even
number of 1’s, the Parity Flag is set and for odd number
of 1’s, the Parity flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or

logical operation is zero else it is reset.

Sign Flag (SF): In sign magnitude format the sign of

number is indicated by MSB bit. If the result of operation
is negative, sign flag is set.
Control Flags
Control flags are set or reset deliberately to control the operations of
the execution unit.
Control flags are as follows:
• Trap Flag (TF): It is used for single step control. It allows user
to execute one instruction of a program at a time for debugging.
• When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is
set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
• It can be set by executing instruction sit and can be cleared by
executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set,
string bytes are accessed from higher memory address to lower
memory address.
• When it is reset, the string bytes are accessed from lower memory
address to higher memory address.
There are 16 bits in this Flag register, each bit is called a flag and
can take a value of 1 or 0. 
Carry Flag (CF) - this flag is set to 1 when there is an unsigned
overflow. For example when you add bytes 255 + 1 (result is not in
range 0...255). When there is no overflow this flag is set to 0. 
Parity Flag (PF) - this flag is set to 1 when there is even number
of one bits in result, and to 0 when there is odd number of one bits.
Even if result is a word only 8 low bits are analyzed!
Auxiliary Flag (AF) - set to 1 when there is an unsigned
overflow for low nibble (4 bits). 
Zero Flag (ZF) - set to 1 when result is zero. For none zero result
this flag is set to 0. 
Sign Flag (SF) - set to 1 when result is negative. When result
is positive it is set to 0. Actually this flag take the value of the most
significant bit.
Trap Flag (TF)-when TF = 0, normal program execution occurs.
When TF = 1, it causes a trap interrupt to occur after each
instruction executes. This is why we often call trap a single-step. If
the T flag is logic 1, the trapping (debugging) feature is enabled.
Interrupt enable Flag (IF) - this flag is set to 1 when CPU
reacts to interrupts from external devices. 
Direction Flag (DF) - this flag is used by some instructions to
process data chains; when this flag is set to 0 - the processing is
done forward, when this flag is set to 1 the processing is done
backward. 
Overflow Flag (OF) - set to 1 when there is a signed overflow.
For example, when you add bytes 100 + 50(result is not in range
-128...127).
Figure shows The programming model of the 8086 through the Core2 microprocessor
including the 64-bit extensions.
• Above Figure illustrates the programming model (Internal
microprocessor architecture) of the 8086 through the Core2
microprocessor including the 64-bit extensions.
• The earlier 8086, 8088, and 80286 contain 16-bit internal
architectures, a subset of the registers shown in Figure.
• The shaded areas represent registers that are found in early
versions of the 8086, 8088, or 80286 microprocessors and are
provided on the 80386–Core2 microprocessors for compatibility
to the early versions.
• The programming model contains 8-, 16-, and 32-bit registers.
The Pentium 4 and Core2 also contain 64-bit registers when
operated in the 64-bit mode as illustrated in the programming
model.
• The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL
and are referred to when an instruction is formed using these
two-letter designations. For example, an
ADD AL, AH instruction adds the 8-bit contents of AH to AL. (Only
AL changes due to this instruction.)
The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS,
CS, DS, ES, SS, FS, and GS.
• Note that the first four 16 bit registers contain a pair of 8-bit
registers. An example is AX, which contains AH and AL.
• The 16-bit registers are referenced with the two-letter
designations such as AX.
For example, an
• ADD DX, CX instruction adds the 16-bit contents of CX to DX.
(Only DX changes due to this instruction.)
•  The extended 32-bit registers are EAX, EBX, ECX, EDX, ESP,
EBP, EDI, ESI, EIP, and EFLAGS. These 32-bit extended
registers, and 16-bit registers FS and GS, are available only in the
80386 and above.
• The 16-bit registers are referenced by the designations FS or GS
for the two new 16-bit registers, and by a three-letter designation
for the 32-bit registers.
• For example, an
• ADD ECX, EBX instruction adds the 32-bit contents of EBX to ECX. (Only
ECX changes due to this instruction.)
Some registers are general-purpose or multipurpose registers, while
some have special purposes.
 The multipurpose registers include EAX, EBX, ECX, EDX, EBP,
EDI, and ESI. These registers hold various data sizes (bytes, words,
or doublewords) and are used for almost any purpose, as dictated
by a program.
The 64-bit registers are designated as RAX, RBX, and so forth. In
addition to the renaming of the registers for 64-bit widths, there are
also additional 64-bit registers that are called R8 through R15. The
64-bit extensions have multiplied the available register space by
more than 8 times in the Pentium 4 and the Core2 when compared
to the original microprocessor architecture as indicated in the
shaded area in Figure. An example 64-bit instruction is
ADD RCX, RBX, instruction, which adds the 64-bit contents of
RBX to RCX. (Only RCX changes due to this instruction.)
One difference exists: these additional 64-bit registers (R8 through
R15) are addressed as a byte, word, doubleword, or
quadword, but only the rightmost 8 bits is a byte.
Table shows the overrides used to access
portions of a 64-bit register.

Register Size Override Bits Accessed Example

8 bits B 7–0 MOV R9B, R10B

16 bits W 15–0 MOV R10W, AX

32 bits D 31–0 MOV R14D, R15D

64 bits — 63–0 MOV R13, R12

Segment registers: - pointing at accessible blocks of memory
CS –Code Segment register points at the segment containing the
current program.
DS – Data Segment register generally points at segment where
variables are defined.
ES - Extra Segment register, it's up to a coder to define its usage.
SS –Stack Segment register points at the segment containing the
stack.
Segment registers work together with general purpose register to
access any memory value.
For example if we would like to access memory at the physical
address 12345h (hexadecimal), we should set the DS = 1230h and SI
= 0045h.
This is good, since this way we can access much more memory than
with a single register that is limited to 16 bit values.
CPU makes a calculation of physical address by multiplying the
segment register by 10h and adding general purpose register to it
(1230h * 10h + 45h = 12345h):
By default BX, SI(Source Index) and DI (Destination
Index) registers work with DS (Data Segment) register;
BP and SP work with SS segment register.
Other general purpose registers cannot form an effective
address! 
also, although BX can form an effective
address, BH and BL cannot. 
 
Segment and Offset Addressing Scheme Allows Relocation
A relocatable program is one that can be placed into any area of
memory and executed without change.
Relocatable data are data that can be placed in any area of
memory and used without any change to the program. The
segment and offset addressing scheme allows both programs and
data to be relocated without changing a thing in a program or
data.
 Table Shows Default 16-bit segment and offset
combinations.

Segment Offset Special Purpose

CS IP Instruction address

DS BX, DI, SI, an 8- or 16-bit Data address

ES DI for string instructions String destination address

SS SP or BP Stack address
Table Shows Default 32-bit segment and offset combinations.

Segment Offset Special Purpose

CS EIP Instruction address

DS EAX, EBX, ECX, EDX, ESI, EDI Data address

an 8- or 32-bit number

ES EDI for string instructions String destination address

SS ESP or EBP Stack address

FS No default General address

GS No default General address

Special Purpose Registers:

IP - Instruction Pointer:

IP register always works together with CS (Code Segment) register
and it points to currently executing instruction.

Flags Register - determines the current

state of the microprocessor. Flags register is modified
automatically by CPU after mathematical operations, this allows to
determine the type of the result, and to determine conditions to
transfer control to other parts of the program.
Addressing Modes
There are 3 major memory addressing modes, namely;
1. DATA-ADDRESSING MODES
1) Register
2) Immediate
3) Direct
4) Register indirect
5) Base plus index
6) Register-relative
7) Base relative-plus-index in the 8086 through the 80286
microprocessor
8) Scaled-index mode of addressing memory data in the 80386
and above
2. PROGRAM MEMORY-ADDRESSING MODES
Direct
Relative
Indirect
3. STACK MEMORY-ADDRESSING MODES
PUSH
POP
CALL
RET
Source and Destination in an instruction:
The source and destination in an instruction are often called
operands.
The source never changes, but the destination always changes.1
It is crucial to remember that a MOV instruction always copies
the source data into the destination. Also, note the flag register
remains unaffected by most data transfer instructions.
Figure shows the various DATA ADDRESSING MODES, which is given below.
Register Addressing
Table Shows Examples of register-addressed instructions are shown in the following table.
Assembly Language Size Operation
MOV CH,CL 8 bits Copies CL into CH
MOV R8B,CL 8 bits Copies CL to the byte portion of R8 (64-bit mode)
MOV R8B,CH 8 bits Not allowed
MOV AX,CX 16 bits Copies CX into AX
MOV SP,BP 16 bits Copies BP into SP
MOV DS,AX 16 bits Copies AX into DS
MOV BP,R10W 16 bits Copies R10 into BP (64-bit mode)
MOV SI,DI 16 bits Copies DI into SI
MOV BX,ES 16 bits Copies ES into BX
MOV ECX,EBX 32 bits Copies EBX into ECX
MOV ESP,EDX 32 bits Copies EDX into ESP
MOV EDX,R9D 32 bits Copies R9 into EDX (64-bit mode)
MOV RAX,RDX 64 bits Copies RDX into RAX
MOV DS,CX 16 bits Copies CX into DS
MOV ES,DS — Not allowed (segment-to-segment)
MOV BL,DX — Not allowed (mixed sizes)
MOV CS,AX Not allowed (the code segment register may not be the
destination
register)
 
Immediate Addressing
Table Shows Examples of immediate addressing using the MOV instruction are
shown in the following table.
*Note: This is not an error. The ASCII characters are stored as BA, so exercise
care when using word-sized pairs of ASCII characters.
Assembly Language Size Operation
MOV BL,44 8 bits Copies 44 decimal (2CH) into BL
MOV AX,44H 16 bits Copies 0044H into AX
MOV SI,0 16 bits Copies 0000H into SI
MOV CH,100 8 bits Copies 100 decimal (64H) into CH
MOV AL,’A’ 8 bits Copies ASCII A into AL
MOV AH,1 8 bits Not allowed in 64-bit mode, but allowed in
32- or 16-bit modes
MOV AX,’AB’ 16 bits Copies ASCII BA* into AX
MOV CL,11001110B 8 bits Copies 11001110 binary into CL
MOV EBX,12340000H 32 bits Copies 12340000H into EBX
MOV ESI,12 32 bits Copies 12 decimal into ESI
MOV EAX,100B 32 bits Copies 100 binary into EAX
MOV RCX,100H 64 bits Copies 100H into RCX
Direct Addressing.
Direct addressing with a MOV instruction transfers data between a memory location, located within
the data segment, and the AL (8-bit), AX (l6-bit), or EAX (32-bit) register. A MOV instruction using this
type of addressing is usually a 3-byte long instruction. The MOV AL, DATA instruction,
Assembly Language Size Operation
MOV AL,NUMBER 8 bits Copies the byte contents of data segment memory
location NUMBER into AL
MOV AX,COW 16 bits Copies the word contents of data segment memory location
COW into AX
MOV EAX,WATER* 32 bits Copies the doubleword contents of data segment location
WATER into EAX
MOV NEWS,AL 8 bits Copies AL into byte memory location NEWS
MOV THERE,AX 16 bits Copies AX into word memory location THERE
MOV HOME,EAX* 32 bits Copies EAX into doubleword memory location HOME
MOV ES:[2000H],AL 8 bits Copies AL into extra segment memory at offset address
2000H
MOV AL,MOUSE 8 bits Copies the contents of location MOUSE into AL; in
64-bit mode MOUSE can be any address
MOV RAX,WHISKEY 64 bits Copies 8 bytes from memory location WHISKEY into RAX
 
Table Shows Examples of direct data addressing using a
displacement are shown in the following table.
*This form of addressing is seldom used with most assemblers
because an actual numeric offset address is rarely accessed.
Assembly Language Size Operation
MOV CH,DOG 8 bits Copies the byte contents of data segment memory
location DOG into CH
MOV CH,DS:[1000H]* 8 bits Copies the byte contents of data segment
memory offset address 1000H into CH
MOV ES,DATA6 16 bits Copies the word contents of data segment
memory location DATA6 into ES

MOV DATA7,BP 16 bits Copies BP into data segment memory

location DATA7
MOV NUMBER,SP 16 bits Copies SP into data segment memory location
NUMBER
MOV DATA1,EAX 32 bits Copies EAX into data segment memory location
DATA1
MOV EDI,SUM1 32 bits Copies the doubleword contents of data
segment memory location SUM1 into EDI
 Register Indirect Addressing

*After DS is appended with a 0.

FIGURE Shows The operation of the MOV AX, [BX] instruction
when BX = 1000H and DS = 0100H.
Note that this instruction is shown after the contents of memory
are transferred to AX.
 
Arithmetic and Logic Instruction
The arithmetic instructions include
addition,
subtraction,
multiplication,
division,
comparison,
negation,
increment, and
decrement.
The logic instructions include
AND,
OR,
Exclusive-OR,
NOT,
shifts,
rotates, and
the logical compare (TEST).
These instructions we will study under data manipulation
instructions in chapter V in more detail.
Program Control Instruction
The program control instruction transfers the program execution
control from one part of the program to another part of the
program unconditionally or conditionally. Often flow occurs after a
decision made with the CMP or TEST instruction is followed by a
conditional jump instruction. (More detail under Branch
Instructions).

Flag Manipulation and a Processor Control Instructions

These instructions control the functioning of the available
hardware inside the processor chip. These instructions are
categorized into two types:
1. Flag Manipulation instructions.
2. Machine Control instructions.
Flag Manipulation instructions
The Flag manipulation instructions directly modify
some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
 
Machine Control instructions
The Machine control instructions control
the bus usage and execution
i . WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like
NOP
v. LOCK – Bus lock instruction
prefix.