FPGA Microprocessor: ECE 428 Programmable ASIC Design
FPGA Microprocessor: ECE 428 Programmable ASIC Design
FPGA Microprocessor: ECE 428 Programmable ASIC Design
FPGA Microprocessor
Part 1
ASIC
1. Application specific 2. Less flexible and almost impossible to Update unless the ASIC contains programmable circuits 3. Normally, optimal performance
14-2
First, an instruction is fetched into the microprocessor Second, the instruction is decoded for execution Finally, the instruction is executed.
14-3
FPGA
Data Memory
R1 R0
oeb
Instruction memory
load Rd
ACC Rd
ACC d Rd ACC
loadi d store Rd
Load the accumulator with the immediate data d Store the value in the accumulator into RAM location Rd.
add Rd
ACC ACC+Rd+C Add the content of RAM location Rd and the C flag to the Accumulator.
addi d xor Rd
Add the value d and the C flag to the accumulator. EXCLUSIVE-OR the content of RAM location Rd with the Accumulator.
test Rd
AND the contents of RAM location Rd with the accumulator, but do not store the results in the 14-6 accumulator. Instead, set the Z flag if the result is 0,
clear_c
set_c skipc
C0
C1 PC PC+1+C
skipz
PC PC+1+Z
jump a
PC a
14-7
Instruction Encoding
Instruction Format
Fixed length instructions (8 bits) Each instruction can have one or zero operand
7 0
Opcode
3 0
clear_c
set_c
Opcode
6
Opcode
Operand
0
address
jump a
14-8
Instruction Encoding
Mnemonic load Rd loadi d store Rd add Rd addi d xor Rd test Rd clear_c set_c Encoding 0 1 0 0 d 3 d2 d1 d0 0 0 0 1 d 3 d2 d1 d0 0 0 1 1 d 3 d2 d1 d0 0 1 0 1 d 3 d2 d1 d0 0 0 1 0 d 3 d2 d1 d0 0 1 1 0 d 3 d2 d1 d0 0 1 1 1 d 3 d2 d1 d0 00 0 0 0 0 0 0 00 0 0 0 0 0 1 Comment d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the immediate data d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the immediate data d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the address of RAM location
skipc
00 0 0 0 0 1 0
00 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 a3 a2 a1 a0 is the new instruction address
14-9
skipz
jump a
Fetch
1. Fetch instruction 2. Update PC register
Decoding
1. Decode instruction 2. Fetch operand if it is needed
Execution
1. Execute the instruction
14-10
Fetch
clk rst curr_ir(7:0) clk rst alu_op(2:0) curr_ir(7:0) curr_acc(3:0) inc_pc curr_carry curr_zero jump_pc
curr_pc(6:0)
U5
d(3:0) s(6:0)
addgen s(6:0)
14-11
leddcd
Address Generation
If inc_pc = 1, the adder output goes to the input of the register (for normal instruction address update and skipz and skipc instructions).
the output of the register goes to the input of the register. and inc_pc=1 at the same time.
14-12
14-13
DFF
DFF
DFF
Execution
Decoding
clock
curr_ir
Current state
Curr_zero Curr_carry
Control signals
14-14
14-15
Execution Unit
Accumulator-Based Architecture
B
Cin Cout
ALU operations
Name Operation Encoding
PASS
ACC B
ACCACC+B+Cin ACC ACC B
001
010 011
ACC
ADD XOR
AND
100
101 110
For operations with two operands, one operand is accumulator. The execution result is store in
accumulator
SET_C CLR_C
14-16
ALU Circuit
alu_op[1]
alu_op[0]
Operation
PASS
0
1 1
1
1 0
XOR ADD*
14-18
Machine code
18H 30H 14H 31H 19H 32H 12H 33H 00H 40H 52H 34H 41H 53H 35H
14-19
Fetch
Decoding
14-20