01 Introduction
01 Introduction
01 Introduction
Objectives
After studying the material in this chapter, you will be able to: 1. Describe the current economic state and the technical roots of the semiconductor industry. 2. Explain what is an integrated circuit (IC) and list the five circuit integration eras. 3. Describe a wafer, including how it is layered and describe the essential aspects of the five stages of wafer fabrication. 4. State and discuss the three major trends associated with improvement in wafer fabrication. 5. Explain what is a critical dimension (CD) and how Moores law predicts future wafer fabrication improvement. 6. Describe the different eras of electronics since the invention of the transistor up to modern wafer fabrication. 7. Discuss different career paths in the semiconductor industry.
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Microprocessor Chips
Photo 1.1
Vacuum Tubes
Photo 1.2
Chip Manufacturer
Figure 1.1
Photo courtesy of Lucent Technologies Bell Labs Innovations Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 1.3
Figure 1.2
Integration Eras
From SSI to ULSI 1960 - 2000
Photo 1.4
Figure 1.3
Circuit Integration No integration (discrete components) Small scale integration (SSI) Medium scale integration (MSI) Large scale integration (LSI) Very large scale integration (VLSI) Ultra large scale integration (ULSI)
Table 1.1
ULSI Chip
Photo 1.5
IC Fabrication Silicon
Wafer Wafer Sizes Devices and Layers
Wafer preparation Wafer fabrication Wafer test/sort Assembly and packaging Final test
2001by Prentice Hall
2000
1992 1987
1981
1975
1965
50 mm 100 mm 125 mm
150 mm
200 mm
300 mm
Figure 1.4
drain
Silicon substrate
Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 1.5
Stages of IC Fabrication
1.
Wafer Preparation includes crystal growing, rounding, slicing and polishing. Wafer Fabrication includes cleaning, layering, patterning, etching and doping.
4.
Assembly and Packaging: The wafer is cut along scribe lines to separate each die. Metal connections are made and the chip is encapsulated.
Scribe line A single die Assembly Packaging
2.
3.
Test/Sort includes probing, testing and sorting of each die on the wafer.
Defective die
5.
Figure 1.6
6. Edge Rounding
1. Crystal Growth
Heater
5. Wafer Slicing
Figure 1.7
Wafer Fab
Photo 1.6
Figure 1.8
Semiconductor Trends
Critical Dimension
Common IC Features
Line Width Contact Hole Space
Figure 1.9
Past and Future Technology Nodes for Device Critical Dimension (CD)
1988 CD ( m) 1.0
1992 0.5
1995 0.35
1997 0.25
1999 0.18
2001 0.15
2002 0.13
2005 0.10
Table 1.2
1997 1999
2012
Redrawn from Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1997. Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 1.10
10M
Transistors
80486
1M
80386 80286 8086
25
100K
1.0
10K
8080 4004
.1
1975
1980
1985 Year
1990
1995
.01 2000
Used with permission from Proceedings of the IEEE, January, 1998, 1998 IEEE Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 1.11
Figure 1.12
0 1997 1999 2001 2003 Year Redrawn from Semiconductor Industry Association, National Technology Roadmap, 1997
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
2006
2009
2012
Figure 1.13
1976
1980
1984
1988
1992
1996
2000
Year
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 1.14
10-8
1930 10-10
1940
1950
1960 Year
1970
1980
1990
2000
Redrawn from C. Chang & S. Sze, McGraw-Hill, ULSI Technology, (New York: McGraw-Hill, 1996), xxiii. Figure 1.15 Semiconductor Manufacturing Technology 2001by Prentice Hall
by Michael Quirk and Julian Serda
1950s: Transistor Technology 1960s: Process Technology 1970s: Competition 1980s: Automation 1990s: Volume Production
Cost
$1,000,000,000
$100,000,000
$10,000,000
1970
1980
1990
2000 Year
2010
2020
Used with permission from Proceedings of IEEE, January, 1998 1998 IEEE Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 1.16
Production Supervisor
BS BSET*
AS+ AS HS +
HS Education
Figure 1.17
Rework
9 6 3
Production Equipment
Inspection
Production Equipment
Inspection
Inspection
Wafer Starts
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 5 6 7 8 9 10 11 12 13 14 15 16 17 18 12 13 14 15 16 17 18 19 20 21 22 23 24 25 19 20 21 22 23 24 25 26 27 28 29 30 31 26 27 28 29 30 31
Wafer Moves
Wafer Outs
1 1 2 3 4 5 2 3 4 5 6 6 7 7 8 8 9 10 11 12 13 14 15 9 10 11 12 13 14 15 16 17 18 19 20 21 22 16 17 18 19 20 21 22 23 24 25 26 27 28 29 23 24 25 26 27 28 29 30 31 30 31
Production Equipment
Inspection
Production Equipment
Inspection
Production Equipment
Inspection
Production Cycle Time = (Date and Time of Wafer Start) - (Date and Time of Wafer Out) Wafer Outs = Wafer Starts - Wafers Scrapped Operator Efficiency = Theoretical Cycle Time / Actual Cycle Time
Figure 1.18
Photo 1.7
Photo 1.8
Review Chapter 1
Summary Key Terms Review Questions Selected Industry Web Sites References
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