Data Sheet: TEA1533T TEA1533AT

INTEGRATED CIRCUITS
DATA SHEET
TEA1533T; TEA1533AT
GreenChipTMII SMPS control IC
Product specification 2002 Aug 23
Supersedes data of 2002 May 31
Philips Semiconductors Product specification
GreenChipTMII SMPS control IC TEA1533T; TEA1533AT
FEATURES APPLICATIONS
Distinctive features Besides typical application areas, i.e. adapters and
chargers, the device can be used in TV and monitor
• Universal mains supply operation (70 to 276 V AC)
supplies and all applications that demand an efficient and
• High level of integration, giving a very low external cost-effective solution up to 250 W.
component count.
Green features
• Valley or zero voltage switching for minimum switching
losses
• Efficient quasi-resonant operation at high power levels
• Frequency reduction at low power standby for improved
system efficiency (<3 W)
• Cycle skipping mode at very low loads; Pi <300 mW at 1 14
no-load operation for a typical adapter application

2 13
• On-chip start-up current source.
3 12
Protection features
4 TEA1533T 11
• Safe restart mode for system fault conditions TEA1533AT
• Continuous mode protection by means of 5 10
demagnetization detection (zero switch-on current)

6 9
• Accurate and adjustable overvoltage protection (latched
in TEA1533T, safe restart in TEA1533AT) 7 8
• Short winding protection

• Undervoltage protection (foldback during overload)
• Overtemperature protection (latched in TEA1533T, safe
restart in TEA1533AT)
• Low and adjustable overcurrent protection trip level
• Soft (re)start
• Mains voltage-dependent operation enabling level.
MGU499
Fig.1 Basic application diagram.
2002 Aug 23 2
GENERAL DESCRIPTION The proprietary high voltage BCD800 process makes

direct start-up possible from the rectified mains voltage in
The GreenChip(1)II is the second generation of green
an effective and green way. A second low voltage
Switched Mode Power Supply (SMPS) control ICs
BICMOS IC is used for accurate, high-speed protection
operating directly from the rectified universal mains. A high
functions and control.
level of integration leads to a cost effective power supply
with a very low number of external components. Highly efficient and reliable supplies can easily be
designed using the GreenChipII control IC.
The special built-in green functions allow the efficiency to
be optimum at all power levels. This holds for
quasi-resonant operation at high power levels, as well as
fixed frequency operation with valley switching at medium
power levels. At low power (standby) levels, the system
operates at a reduced frequency and with valley detection.
(1) GreenChip is a trademark of Koninklijke Philips

Electronics N.V.
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TEA1533T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TEA1533AT
2002 Aug 23 3
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book, full pagewidth

2002 Aug 23
BLOCK DIAGRAM
Philips Semiconductors
GreenChipTMII SMPS control IC
VCC 2 SUPPLY START-UP 14
DRAIN
MANAGEMENT CURRENT SOURCE
Iprot(DEM)
DEMAG OCP
internal UVLO start VALLEY
supply SHORT clamp
M-level PROTECTION 12, 13 HVS
S1 n.c.
3
GND
VOLTAGE 7
DEM
CONTROLLED LOGIC 50
OSCILLATOR mV
100
mV
OVER-
FREQUENCY UP/DOWN
VOLTAGE
CONTROL COUNTER
PROTECTION
11
LOGIC DRIVER DRIVER
Iprot(CTRL)
6 Iss
4
CTRL −1
POWER-ON LEB 0.5 V
RESET S Q soft
start
blank
S2
UVLO R Q
2.5 V 9
Isense
burst OCP
S Q
detect
OVER-
TEA1533T; TEA1533AT
VCC < 4.5 V
TEMPERATURE
or UVLO R Q
PROTECTION
(TEA1533AT)
short
MAXIMUM winding 0.88 V
ON-TIME
TEA1533T PROTECTION
Product specification
OVERPOWER
TEA1533AT PROTECTION
MGU500
Fig.2 Block diagram.

PINNING FUNCTIONAL DESCRIPTION
SYMBOL PIN DESCRIPTION The TEA1533 is the controller of a compact flyback

converter, and is situated at the primary side. An auxiliary
n.c. 1 not connected
winding of the transformer provides demagnetization
VCC 2 supply voltage detection and powers the IC after start-up.
GND 3 ground
The TEA1533 can operate in multi modes (see Fig.4).
CTRL 6 control input
DEM 7 input from auxiliary winding for f
MGU508
demagnetization timing, overvoltage (kHz)
handbook, halfpage
VCO fixed quasi resonant
and overpower protection 175
Isense 9 programmable current sense input
DRIVER 11 gate driver output 25
HVS 12 high voltage safety spacer, not P (W)

connected
HVS 13 high voltage safety spacer, not Fig.4 Multi modes operation.
connected
DRAIN 14 drain of external MOS switch, input for
start-up current and valley sensing
The next converter stroke is started only after
demagnetization of the transformer current (zero current
switching), while the drain voltage has reached the lowest
voltage to prevent switching losses (green function). The
primary resonant circuit of the primary inductance and
drain capacitor ensures this quasi-resonant operation. The
design can be optimized in such a way that zero voltage
handbook, halfpage switching can be reached over almost the universal mains
n.c. 1 14 DRAIN
range.
VCC 2 13 HVS
To prevent very high frequency operation at lower loads,
GND 3 12 HVS the quasi-resonant operation changes smoothly in fixed
n.c. 4 TEA1533T 11 DRIVER frequency PWM control.
TEA1533AT At very low power (standby) levels, the frequency is
n.c. 5 10 n.c.
controlled down, via the VCO, to a minimum frequency of
CTRL 6 9 Isense
approximately 25 kHz.
DEM 7 8 n.c.
Start-up, mains enabling operation level and
MGU501
undervoltage lock-out
Initially, the IC is self supplying from the rectified mains
voltage via pin DRAIN (see Figs 11 and 12). Supply
capacitor CVCC is charged by the internal start-up current
source to approximately 4 V or higher, depending on the
Fig.3 Pin configuration. voltage on pin DRAIN.
2002 Aug 23 5
Once the drain voltage exceeds the M-level

(mains-dependent operation-enabling level), the start-up MGU233
V sense(max)
current source will continue charging capacitor CVCC handbook, halfpage
(switch S1 will be opened); see Fig.2. The IC will activate

the converter as soon as the voltage on pin VCC passes 0.52 V
the VCC(start) level. The IC supply is taken over by the
auxiliary winding as soon as the output voltage reaches its
intended level and the IC supply from the mains voltage is
subsequently stopped for high efficiency operation (green
function).
1V 1.5 V VCTRL
The moment the voltage on pin VCC drops below the (typ) (typ)
undervoltage lock-out level, the IC stops switching and
enters a safe restart from the rectified mains voltage. Fig.5 Vsense(max) voltage as function of VCTRL.
Inhibiting the auxiliary supply by external means causes
the converter to operate in a stable, well defined burst
mode.
Supply management
MGU509
f
All (internal) reference voltages are derived from a handbook, halfpage
(kHz)
temperature compensated, on-chip band gap circuit. 175 kHz
175
Current mode control

Current mode control is used for its good line regulation
25
behaviour.
The ‘on-time’ is controlled by the internally inverted control VCO2 VCO1 Vsense(max) (V)
level level
voltage, which is compared with the primary current
information. The primary current is sensed across an
Fig.6 VCO frequency as function of Vsense(max)
external resistor. The driver output is latched in the logic,
preventing multiple switch-on.
The internal control voltage is inversely proportional to the Cycle skipping
external control pin voltage, with an offset of 1.5 V. This At very low power levels, a cycle skipping mode will be
means that a voltage range from 1 to 1.5 V on pin CTRL activated. A high control voltage will reduce the switching
will result in an internal control voltage range from frequency to a minimum of 25 kHz. If the voltage on the
0.5 to 0 V (a high external control voltage results in a low control pin is raised even more, switch-on of the external
duty cycle). power MOSFET will be inhibited until the voltage on the
control pin has dropped to a lower value again (see Fig.7).
Oscillator
For system accuracy it is not the absolute voltage on the
The maximum fixed frequency of the oscillator is set by an control pin that will trigger the cycle skipping mode, but a
internal current source and capacitor. The maximum signal derived from the internal VCO will be used.
frequency is reduced once the control voltage enters the
VCO control window. Then, the maximum frequency Remark 1: If the no-load requirement of the system is such
changes linearly with the control voltage until the minimum that the output voltage can be regulated to its intended
frequency is reached (see Figs 5 and 6). level at a switching frequency of 25 kHz or above, the
cycle skipping mode will not be activated.
Remark 2: As switching will stop when the voltage on the
control pin is raised above a certain level, the burst mode
has to be activated by a microcontroller or any other circuit
sending a 30 µs, 16 mA pulse to the control input
(pin CTRL) of the IC.
2002 Aug 23 6
handbook, full pagewidth

fosc
1.5 V − VCTRL current

comparator fmax
CTRL DRIVER
DRIVER
fmin
Isense
X2
dV2 dV1
Vx (mV)
Vx cycle 150
skipping
V
OSCILLATOR
I
150 mV 1
0
Vx (mV)
MGU510
The voltage levels dV1 and dV2 are fixed in the IC to 50 mV (typical) and 18 mV (typical) respectively.
Fig.7 The cycle skipping circuitry.
Demagnetization Minimum and maximum ‘on-time’

The system will be in discontinuous conduction mode all The minimum ‘on-time’ of the SMPS is determined by the
the time. The oscillator will not start a new primary stroke Leading Edge Blanking (LEB) time. The IC limits the
until the secondary stroke has ended. ‘on-time’ to 50 µs. When the system desires an ‘on-time’
longer than 50 µs, a fault condition is assumed (e.g.
Demagnetization features a cycle-by-cycle output
removed Ci in Fig.11), the IC will stop switching and enter
short-circuit protection by immediately lowering the
the safe restart mode.
frequency (longer off-time), thereby reducing the power
level.
Demagnetization recognition is suppressed during the first
tsuppr time. This suppression may be necessary in
applications where the transformer has a large leakage
inductance, at low output voltages and at start-up.
If pin DEM is open-circuit or not connected, a fault
condition is assumed and the converter will stop operating
immediately. Operation will recommence as soon as the
fault condition is removed.
If pin DEM is shorted to ground, again a fault condition is
assumed and the converter will stop operating after the
first stroke. The converter will subsequently enter the safe
restart mode. This situation will persist until the
short-circuit is removed.
2002 Aug 23 7
OverVoltage Protection (OVP) Valley switching

An OVP mode is implemented in the GreenChip series. A new cycle starts when the power MOSFET is switched
This works for the TEA1533 by sensing the auxiliary on (see Fig.8). After the ‘on-time’ (which is determined by
voltage via the current flowing into pin DEM during the the ‘sense’ voltage and the internal control voltage), the
secondary stroke. The auxiliary winding voltage is a switch is opened and the secondary stroke starts. After the
well-defined replica of the output voltage. Any voltage secondary stroke, the drain voltage shows an oscillation
spikes are averaged by an internal filter. 1
with a frequency of approximately -----------------------------------------------
If the output voltage exceeds the OVP trip level, an internal 2 × π × ( Lp × Cd )
counter starts counting subsequent OVP events. The
counter has been added to prevent incorrect OVP where Lp is the primary self inductance of the transformer
detections which might occur during ESD or lightning and Cd is the capacitance on the drain node.
events. If the output voltage exceeds the OVP trip level a As soon as the oscillator voltage is high again and the
few times and not again in a subsequent cycle, the internal secondary stroke has ended, the circuit waits for the
counter will count down with twice the speed compared lowest drain voltage before starting a new primary stroke.
with counting up. However, when typical 10 cycles of This method is called valley detection. Figure 8 shows the
subsequent OVP events are detected, the IC assumes a drain voltage together with the valley signal, the signal
true OVP and the OVP circuit switches the power indicating the secondary stroke and the oscillator signal.
MOSFET off. Next, the controller waits until the UVLO
level is reached on pin VCC. When VCC drops to UVLO, In an optimum design, the reflected secondary voltage on
capacitor CVCC will be recharged to the Vstart level. the primary side will force the drain voltage to zero. Thus,
zero voltage switching is very possible, preventing large
Regarding the TEA1533T, this IC will not start switching
capacitive switching losses  P = --- × C × V × f and
1 2
again. Subsequently, VCC will drop again to the UVLO  
2
level, etc. Operation only recommences when the VCC
voltage drops below a level of approximately 4.5 V allowing high frequency operation, which results in small
(practically when Vmains has been disconnected for a short and cost effective inductors.
period).
Regarding the TEA1533AT, switching starts again (safe
restart mode) when the Vstart level is reached. This
process is repeated as long as the OVP condition exists.
The output voltage Vo(OVP) at which the OVP function trips,
can be set by the demagnetization resistor, RDEM:
V o ( OVP ) =
Ns
----------- { I (OVP)(DEM) × R DEM + V clamp(DEM)(pos) }
N aux
where Ns is the number of secondary turns and Naux is the

number of auxiliary turns of the transformer.
Current I(OVP)(DEM) is internally trimmed.
The value of RDEM can be adjusted to the turns ratio of the
transformer, thus making an accurate OVP possible.
2002 Aug 23 8
handbook, full pagewidth primary secondary secondary

stroke stroke ringing
drain
valley
secondary
stroke
B A
oscillator
MGU235
A: Start of new cycle at lowest drain voltage.

B: Start of new cycle in a classical PWM system at high drain voltage.
Fig.8 Signals for valley switching.
OverCurrent Protection (OCP) N aux

where: N = -----------
-
The cycle-by-cycle peak drain current limit circuit uses the Np
external source resistor to measure the current accurately.
This allows optimum size determination of the transformer The current information is used to adjust the peak drain
core (cost issue). The circuit is activated after the leading current, which is measured via pin Isense. The internal
edge blanking time, tleb. The OCP circuit limits the ‘sense’ compensation is such that an almost mains independent
voltage to an internal level. maximum output power can be realized.
The OPP curve is given in Fig.9.
OverPower Protection (OPP)
During the primary stroke, the rectified mains input voltage
is measured by sensing the current drawn from pin DEM.
This current is dependent on the mains voltage, according
V aux N × V mains
to the following formula: I DEM ≈ --------------- ≈ --------------------------
R DEM R DEM
2002 Aug 23 9
Control pin protection

If pin CTRL is open-circuit or not connected, a fault
MGU236
handbook, halfpage Vsense(max)
condition is assumed and the converter will stop switching.
Operation will recommence as soon as the fault condition
0.52 V is removed.
(typ)
Burst mode standby

0.3 V
(typ)
Pin CTRL is also used to implement the burst mode
standby. In burst mode standby, the power supply enters
a special low dissipation state. Figure 11 shows a flyback
converter using the burst mode standby function. The
−100 µA −24 µA
(typ) (typ)
system enters burst mode standby when the
IDEM
microcontroller activates NPN transistor T1 on the
secondary side.
Fig.9 OPP correction curve. When the voltage on Cmicro exceeds a certain voltage,
measured by the microcontroller, the opto-coupler is
activated by T1, sending a large current signal to
pin CTRL. In response to this signal, the IC stops switching
Short winding protection and enters a ‘hiccup’ mode. This burst activation signal
should be present for longer than the ‘burst blank’ period
After the leading edge blanking time, the short winding (typically 30 µs): the blanking time prevents false burst
protection circuit is activated. If the ‘sense’ voltage triggering due to spikes. Figure 12 shows the burst mode
exceeds the short winding protection voltage Vswp, the standby signals. The hiccup mode during burst mode
converter will stop switching. Once VCC drops below the standby operation does not differ from the hiccup mode at
UVLO level, capacitor CVCC will be recharged and the safe restart during a system fault condition (e.g. output
supply will restart again. This cycle will be repeated until short-circuit). The power is reduced during soft restart
the short-circuit is removed (safe restart mode). mode.
The short winding protection will also protect in case of a Burst mode standby operation continues until the
secondary diode short-circuit. microcontroller stops activating transistor T1. The system
then enters the start-up sequence and begins normal
OverTemperature Protection (OTP) switching behaviour.
An accurate temperature protection is provided in the
V th
circuit. When the junction temperature exceeds the -+I
I burstmode = ---------------
thermal shutdown temperature, the IC will stop switching. R CTRL th(on)
When VCC drops to UVLO, capacitor CVCC will be
recharged to the Vstart level.
Regarding the TEA1533T, this IC will not start switching
again. Subsequently, VCC will drop again to the UVLO
level, etc. Operation only recommences when the VCC
voltage drops below a level of approximately 4.5 V
(practically when the Vmains has been disconnected for a
short period).
Regarding the TEA1533AT, when the Vstart level is
reached, switching starts again (safe restart mode). This
process is repeated as long as the OTP condition exists.
2002 Aug 23 10
Soft start-up Driver

To prevent transformer rattle during hiccup, the The driver circuit to the gate of the power MOSFET has a
transformer peak current is slowly increased by the soft current sourcing capability of 170 mA typical and a current
start function. This can be achieved by inserting a resistor sink capability of 700 mA typical. This permits fast turn-on
and a capacitor between pin Isense and the sense resistor and turn-off of the power MOSFET for efficient operation.
(see Fig.10). An internal current source charges the
A low driver source current has been chosen to limit the
capacitor to V = ISS × RSS, with a maximum of
∆V/∆t at switch-on. This reduces Electro Magnetic
approximately 0.5 V.
Interference (EMI) and also limits the current spikes
The start level and the time constant of the increasing across Rsense.
primary current level can be adjusted externally by
changing the values of RSS and CSS.
V ocp – ( I SS × R SS )
I primary(max) = ----------------------------------------------
-
R sense
τ = R SS × C SS
The charging current ISS will flow as long as the voltage on

pin Isense is below approximately 0.5 V. If the voltage on
pin Isense exceeds 0.5 V, the soft start current source will
start limiting the current ISS. At the VCC(start) level, the ISS
current source is completely switched off.
Since the soft start current ISS is subtracted from pin VCC
charging current, the RSS value will affect the VCC charging
current level by a maximum of 60 µA (typical value).
handbook, halfpage
ISS
0.5 V
start-up
RSS
9 Isense
Vocp CSS Rsense
MGU502
Fig.10 Soft start.
2002 Aug 23 11
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Voltages
VCC supply voltage continuous −0.4 +20 V
VCTRL voltage on pin CTRL −0.4 +5 V
VDEM voltage on pin DEM current limited −0.4 − V
Vsense voltage on pin Isense current limited −0.4 − V
VDRAIN voltage on pin DRAIN −0.4 +650 V
Currents
ICTRL current on pin CTRL d < 10% − 50 mA
IDEM current on pin DEM −250 +250 µA
Isense current on pin Isense −1 +10 mA
IDRIVER current on pin DRIVER d < 10% −0.8 +2 A
IDRAIN current on pin DRAIN − 5 mA
General
Ptot total power dissipation Tamb < 70 °C − 0.75 W
Tstg storage temperature −55 +150 °C
Tj operating junction temperature −20 +145 °C
Vesd electrostatic discharge voltage
pins 1 to 13 HBM class 1; note 2 − 2000 V
pin DRAIN HBM class 1; note 2 − 1500 V
any pin MM; note 3 − 400 V
Notes
1. All voltages are measured with respect to ground; positive currents flow into the IC; pin VCC may not be current
driven. The voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the
maximum power rating is not violated.
2. Human Body Model (HBM): equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
3. Machine Model (MM): equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω resistor.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air; note 1 100 K/W
Note
1. With pin GND connected to sufficient copper area on the printed-circuit board.
QUALITY SPECIFICATION
In accordance with ‘SNW-FQ-611-D’.
2002 Aug 23 12
CHARACTERISTICS
Tamb = 25 °C; VCC = 15 V; all voltages are measured with respect to ground; currents are positive when flowing into
the IC; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Start-up current source (pin DRAIN)
IDRAIN supply current drawn from VCC = 0 V; VDRAIN > 100 V 1.0 1.2 1.4 mA
pin DRAIN with auxiliary supply; − 100 300 µA
VDRAIN > 100 V
BVDSS breakdown voltage 650 − − V
M-level mains-dependent operation 60 − 100 V
enabling level
Supply voltage management (pin VCC)
VCC(start) start-up voltage on VCC 10.3 11 11.7 V
VCC(UVLO) under voltage lock-out on VCC 8.1 8.7 9.3 V
VCC(hys) hysteresis voltage on VCC VCC(start) − VCC(UVLO) 2.0 2.3 2.6 V
ICC(h) pin VCC charging current, high VDRAIN > 100 V; VCC < 3V −1.2 −1 −0.8 mA
ICC(l) pin VCC charging current, low VDRAIN > 100 V; −1.2 −0.75 −0.45 mA
3 V < VCC < VCC(UVLO)
ICC(restart) pin VCC restart current VDRAIN > 100 V; −650 −550 −450 µA
VCC(UVLO) < VCC < VCC(start)
ICC(oper) supply current under normal no load on pin DRIVER 1.1 1.3 1.5 mA
operation
ICC(burstmode) supply current while not switching − 0.85 − mA
Demagnetization management (pin DEM)
Vth(DEM) demagnetization comparator 50 100 150 mV
threshold voltage on pin DEM
Iprot(DEM) protection current on pin DEM VDEM = 50 mV −50(1) − −10 nA
Vclamp(DEM)(neg) negative clamp voltage on IDEM = −150 µA −0.5 −0.25 −0.05 V
pin DEM
Vclamp(DEM)(pos) positive clamp voltage on IDEM = 250 µA 0.5 0.7 0.9 V
pin DEM
tsuppr suppression of transformer 1.1 1.5 1.9 µs
ringing at start of secondary
stroke
Pulse width modulator
ton(min) minimum on-time − tleb − ns
ton(max) maximum on-time latched 40 50 60 µs
Oscillator
fosc(l) oscillator low fixed frequency VCTRL > 1.5 V 20 25 30 kHz
fosc(h) oscillator high fixed frequency VCTRL < 1 V 145 175 205 kHz
Vvco(start) peak voltage on pin Isense, where see Figs 6 and 7 − VCO1 − mV
frequency reduction starts
2002 Aug 23 13

Vvco(max) peak voltage on pin Isense, where − VCO1 − 25 − mV
the frequency is equal to fosc(l)
Duty cycle control (pin CTRL)
VCTRL(min) minimum voltage on pin CTRL for − 1.0 − V
maximum duty cycle
VCTRL(max) maximum voltage on pin CTRL for − 1.5 − V
minimum duty cycle
Iprot(CTRL) protection current on pin CTRL VCTRL = 1.5V −1(1) −0.8 -0.5 µA
Burst mode standby (pin CTRL)
Vth(burst)(on) burst mode standby active Iburst = 6 mA 3.3 3.8 4.3 V
threshold voltage
Ith(burst)(on) burst mode standby active current 16 − − mA
Ith(burst)(off) burst mode standby inactive − − 6 mA
current
tburst-blank burst mode standby blanking time 25 30 35 µs
Valley switch (pin DRAIN)
∆V/∆tvalley valley recognition voltage change −85 − +85 V/µs
tvalley-swon delay from valley recognition to − 150(1) − ns
switch-on
Overcurrent and short winding protection (pin Isense)
Vsense(max) maximum source voltage OCP ∆V/∆t = 0.1 V/µs 0.48 0.52 0.56 V
tPD propagating delay from detecting ∆V/∆t = 0.5 V/µs − 140 185 ns
Vsense(max) to switch-off
Vswp short winding protection voltage 0.83 0.88 0.96 V
tleb blanking time for current and 300 370 440 ns
short winding protection
ISS soft start current Vsense < 0.5 V 45 60 75 µA
Overvoltage protection (pin DEM)
IOVP(DEM) OVP current on pin DEM set by resistor RDEM, see 54 60 66 µA
Section “OverVoltage
Protection (OVP)”
Overpower protection (pin DEM)
IOPP(DEM) OPP current on pin DEM to start set by resistor RDEM, see − −24 − µA
OPP correction, set by the Section “OverPower
demagnetization resistor RDEM Protection (OPP)”
IOPP50%(DEM) OPP current on pin DEM, where − −100 − µA
maximum source voltage is
limited to 0.3 V
2002 Aug 23 14

Driver (pin DRIVER)
Isource source current capability of driver VCC = 9.5 V; VDRIVER = 2 V − −170 −88 mA
Isink sink current capability of driver VCC= 9.5 V; VDRIVER = 2 V − 300 − mA
VCC = 9.5 V; 400 700 − mA
VDRIVER = 9.5 V
Vo(max) maximum output voltage of the VCC > 12 V − 11.5 12 V
driver
Overtemperature protection
Tprot(max) maximum temperature protection 130 140 150 °C
level
Tprot(hys) hysteresis for the temperature − 8(1) − °C
protection level
Note
1. Guaranteed by design.
2002 Aug 23 15
APPLICATION INFORMATION
A converter with the TEA1533 consists of an input filter, a transformer with a third winding (auxiliary), and an output stage
with a feedback circuit.
Capacitor CVCC (at pin VCC) buffers the supply voltage of the IC, which is powered via the high voltage rectified mains
during start-up and via the auxiliary winding during operation.
A sense resistor converts the primary current into a voltage at pin Isense. The value of this sense resistor defines the
maximum primary peak current.
Vmains
Do
Vi
Vo
Ci
Np Ns Co
DRAIN
1 14
CVCC
VCC HVS
2 13 n.c.
GND HVS
3 12 n.c.
power
DRIVER MOSFET
4 TEA1533T 11
TEA1533AT
CCTRL 5 10 RSS
CTRL Isense
RCTRL 6 9
DEM Dmicro VµC

7 8 CSS
Rsense
RDEM
standby
MICRO- pulse
Naux Cmicro CONTROLLER
Rreg1
T1
Rreg2
MGU503
Fig.11 Flyback configuration with secondary sensing using the burst mode standby.
2002 Aug 23 16
Vi
VD Vi
(power
MOSFET)
Vo
VCC
Vgate
M-level
burst mode
VµC
start-up normal overvoltage output burst mode standby normal

sequence operation protection short-circuit operation
(TEA1533AT)
MGU504
Fig.12 Typical waveforms.
2002 Aug 23 17
PACKAGE OUTLINE
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
D E A
X
y HE v M A
14 8
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 7 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
97-05-22
SOT108-1 076E06 MS-012
99-12-27
2002 Aug 23 18
SOLDERING If wave soldering is used the following conditions must be

observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
This text gives a very brief insight to a complex technology. turbulent wave with high upward pressure followed by a
A more in-depth account of soldering ICs can be found in smooth laminar wave.
our “Data Handbook IC26; Integrated Circuit Packages”
• For packages with leads on two sides and a pitch (e):
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
There is no soldering method that is ideal for all surface longitudinal axis is preferred to be parallel to the
mount IC packages. Wave soldering can still be used for
transport direction of the printed-circuit board;
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is – smaller than 1.27 mm, the footprint longitudinal axis
recommended. must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied • For packages with leads on four sides, the footprint must
to the printed-circuit board by screen printing, stencilling or be placed at a 45° angle to the transport direction of the
pressure-syringe dispensing before package placement. printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor During placement and before soldering, the package must
type oven. Throughput times (preheating, soldering and be fixed with a droplet of adhesive. The adhesive can be
cooling) vary between 100 and 200 seconds depending applied by screen printing, pin transfer or syringe
on heating method. dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the Typical dwell time is 4 seconds at 250 °C.
packages should preferable be kept below 220 °C for A mildly-activated flux will eliminate the need for removal
thick/large packages, and below 235 °C for small/thin of corrosive residues in most applications.
packages.
Manual soldering
Wave soldering Fix the component by first soldering two
Conventional single wave soldering is not recommended diagonally-opposite end leads. Use a low voltage (24 V or
for surface mount devices (SMDs) or printed-circuit boards less) soldering iron applied to the flat part of the lead.
with a high component density, as solder bridging and Contact time must be limited to 10 seconds at up to
non-wetting can present major problems. 300 °C.
To overcome these problems the double-wave soldering When using a dedicated tool, all other leads can be
method was specifically developed. soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Aug 23 19
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3) suitable
HVSON, SMS
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Aug 23 20
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1) DEFINITIONS
STATUS(2)
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information  Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.
2002 Aug 23 21
NOTES
2002 Aug 23 22
NOTES
2002 Aug 23 23
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002 SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 613502/02/pp24 Date of release: 2002 Aug 23 Document order number: 9397 750 10262

Data Sheet: TEA1533T TEA1533AT

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INTEGRATED CIRCUITS

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

no-load operation for a typical adapter application

demagnetization detection (zero switch-on current)

• Short winding protection

Fig.1 Basic application diagram.

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

GENERAL DESCRIPTION The proprietary high voltage BCD800 process makes

(1) GreenChip is a trademark of Koninklijke Philips

book, full pagewidth

Fig.2 Block diagram.

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

PINNING FUNCTIONAL DESCRIPTION

SYMBOL PIN DESCRIPTION The TEA1533 is the controller of a compact flyback

HVS 12 high voltage safety spacer, not P (W)

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

Once the drain voltage exceeds the M-level

(switch S1 will be opened); see Fig.2. The IC will activate

Current mode control

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

handbook, full pagewidth

1.5 V − VCTRL current

Fig.7 The cycle skipping circuitry.

Demagnetization Minimum and maximum ‘on-time’

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

OverVoltage Protection (OVP) Valley switching

where Ns is the number of secondary turns and Naux is the

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

handbook, full pagewidth primary secondary secondary

A: Start of new cycle at lowest drain voltage.

Fig.8 Signals for valley switching.

OverCurrent Protection (OCP) N aux

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

Control pin protection

Burst mode standby

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

Soft start-up Driver

The charging current ISS will flow as long as the voltage on

Vocp CSS Rsense

Fig.10 Soft start.

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

SYMBOL PARAMETER CONDITIONS VALUE UNIT

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

DEM Dmicro VµC

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

handbook, full pagewidth

start-up normal overvoltage output burst mode standby normal

Fig.12 Typical waveforms.

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT

SOLDERING If wave soldering is used the following conditions must be

GreenChipTMII SMPS control IC TEA1533T; TEA1533AT