TEA1755T Datasheet
TEA1755T Datasheet
TEA1755T Datasheet
1. General description
The GreenChip is the latest generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1755T combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration enables cost-effective power supply
design using a very low number of external components.
The specially built-in green functions provide high efficiency at all power levels. At high
power levels the flyback operates in QR mode or DCM with valley detection. At medium
power levels, the flyback controller switches to Frequency Reduction (FR) mode and limits
the peak current to an adjustable minimum value. In low power mode, the PFC switches
off to maintain high efficiency. At very low power levels, when the flyback switching
frequency drops below 25 kHz, the flyback converter switches to burst mode. During the
non-switching phase of burst mode, the internal IC supply current is minimized to further
optimize efficiency. Valley switching is used in all operating modes.
The advanced burst mode ensures high-efficiency at low power and good standby power
performance while minimizing audible transformer noise.
The TEA1755T is a Multi-Chip Module, (MCM), containing two chips. The proprietary
high-voltage BCD800 process makes direct start-up possible from the rectified universal
mains voltage in an effective and green way. The second low voltage Silicon-On-Insulator
(SOI) is used for accurate, high-speed protection functions and control.
The TEA1755T enables easy design of highly efficient and reliable supplies up to 250 W.
These power supply designs are cost-effective, requiring the minimum number of external
components.
Remark: All values in this document are typical values unless otherwise stated.
NXP Semiconductors TEA1755T
HV start-up DCM/QR flyback and DCM/QR PFC controllers
3. Applications
The device can be used in all applications requiring an efficient and cost-effective
power supply solution for up to 250 W. Notebook adapters in particular benefit from the
high level of integration
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
TEA1755T/1 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
5. Block diagram
PFCDRIVER FBDRIVER
12 13 Ven(PFC)FBCTRL
PFC driver flyback driver
3.5 V PFC gate low power 30.5 μA
driver driver PFC(swon)
PFC(swoff) 5 LATCH
external
CONTROL
power protection
down flyback gate
494 V
low Vin
VINSENSE 7 dual protection
boost PFC R R
MAXIMUM
latch protection protection Q Q frequency 5.5 V 7.0 V
PFCCOMP 6 reset S S enable flyback reduction
enable PFC
burst mode
clamp 29 μA
Ven(PFC)FBCTRL
3.75 V
PFC FLYBACK
OSCILLATOR OSCILLATOR time-out 3 FBCTRL
ton(max)
2.5 V PFC clamp
dual
boost frequency burst mode
VCC good
VOSENSE 9 8.1 μA ton reduction
low power delay
REDUCTION SMPS MINIMUM
1.92 V 3.32 V burst mode OPP
NEAR OVP
Vth(burst) CONTROL start flyback
dual boost external protection start stop PFC OCP
low Vin PFC clamp
Vo OVP clamp
PFC
external protection S flyback driver BLANK
Vth(VOSENSE) protection
OTP S LATCHED 10 FBSENSE
OVP flyback S PROTECTION low power
latch reset R delay
OCP time-out S
SAFE protection
ton max S
PFC driver RESTART enable flyback 60 μA 2.1 μA
BLANK VUVLO R PROTECTION
495 mV Vth(VOSENSE)
PFCSENSE 11
enable PFC power down S START
start flyback
SOFT
60 μA power down
SOFT START start stop PFC VCC good
protection
SOFT STOP CHARGE
external protection charge
CONTROL
Vstartup OPP OPP
Vth(UVLO)
TIMER 4.2 μs VALLEY
VALLEY DETECT OVP
OVP
DETECT COUNTER
OTP internal supply flyback
PFCAUX 8 4 FBAUX
charge flyback
ZERO Vstartup ZERO CURRENT gate
PFC gate CURRENT SIGNAL
SIGNAL
Vth(burst)
TIMER 48 μs
90 mV
Vth(UVLO) TEMPERATURE OTP
-90 mV
low power low power
DELAY
delay
14 16 1 2
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
6. Pinning information
6.1 Pinning
DDD
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
7. Functional description
D2
Tr1
RDRV1 R4 Cbulk
S1 Tr2
RCOMP D4
C6 VOUT
D1 CSS1 RSS1 RSENSE1 R5 (1)
C1 S2
RAUX1 RDRV2
Z1
RS1
PFCDRIVER
OPTO-
PFCSENSE
FBDRIVER
VOSENSE
Vmains FEEDBACK
CSS2
HV
CTIMEOUT
OPTO-FEEDBACK
aaa-002624
(1) The HV pin can either be connected to the center tap of the flyback transformer or to the drain of MOSFET S2.
Fig 3. A typical TEA1755T configuration
When VCC is less than Vtrip, the charge current is Ich(low). This low current protects the IC if
the VCC pin is shorted to ground. To ensure a short start-up time, the charge current above
the Vtrip level is increased to Ich(high), until VCC reaches Vth(UVLO). When VCC is between
Vth(UVLO) and Vstartup, the charge current goes low again to ensure a low safe restart duty
cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when VCC passes the Vstartup level. First, the LATCH pin current source is activated and
the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. Also the
clamp circuit on the PFCCOMP pin is activated.
The PFC circuit is activated when the following conditions are met:
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
If during start-up, the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
Vth(UVLO), the LATCH pin output is deactivated. The charge current is switched on again.
When the flyback converter is started, VFBCTRL is monitored. If the output voltage does not
reach its intended regulation level within a specified time, VFBCTRL reaches the Vto(FBCTRL)
level. An error is then assumed and a safe restart is initiated.
When one of the safe restart or latched protection functions are triggered, both converters
stop switching and the VCC voltage drops to Vth(UVLO). A latched protection recharges
capacitor CVCC using the HV pin, but does not restart the converters. To provide safe
restart protection, the capacitor is recharged using the HV pin and the device restarts (see
block diagram, Figure 1).
If OVP is triggered on the PFC circuit (VVOSENSE > VOVP(VOSENSE)), the PFC controller
stops switching until the VVOSENSE < VOVP(VOSENSE). If a mains UVP is detected,
VVINSENSE < Vstop(VINSENSE), the PFC controller stops switching until
VVINSENSE > Vstart(VINSENSE) again.
When the VCC pin voltage drops under the UVLO level, both controllers stop switching and
enter safe restart mode. In the safe restart mode, the VCC pin capacitor is recharged using
the HV pin.
At very low burst mode repetition rates, VCC can drop under the UVLO level. The UVLO
protection feature Vprot(UVLO) prevents the decrease when the IC is in burst mode.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
IHV
Vstartup
Vth(UVLO)
VCC Vtrip
Vstart(VINSENSE)
VINSENSE
Ven(PFCCOMP)
PFCCOMP
Ven(LA TCH)
LATCH
PROTECTION
soft start
PFCSENSE
PFCDRIVER
soft start
FBSENSE
FBDRIVER
Vto(FBCTRL)
FBCTRL
Vstart(fb)
VOSENSE
VO
charging VCC
capacitor starting normal protection restart
converters operation 014aaa744
During Power-down mode, all internal circuitry is disabled except for a voltage detection
circuit on the VINSENSE pin. This circuit is supplied by the HV pin and draws 12 A from
the HV pin for biasing.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
At initial start-up, switching is prevented until the capacitor on the LATCH pin is charged
above 582 mV. No internal filtering is performed on this pin. An internal 1.75 V clamp
protects the pin from excessive voltages.
When the VINSENSE voltage drops below 750 mV and is then raised to 860 mV, the
latched protection is reset.
The latched protection is also reset by removing both the voltage on the VCC and HV pins.
OTP is a latched protection. It is reset by removing the voltage from both the VCC and HV
pins or by the fast latch reset function (see Section 7.1.5).
VPFCAUX is used to detect transformer demagnetization and the minimum voltage across
the external PFC MOSFET switch.
VPFCCOMP determines the on-time of the PFC. The VVOSENSE is the transconductance
amplifier input which outputs current to the PFCCOMP pin. The regulation
VVOSENSE = 2.5 V. The network connected to the PFCCOMP pin and the
transconductance amplifier determine the dynamic behavior of the PFC control.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Operating near the PFC OVP level causes the PFC stage on-time to decrease rapidly to
zero.
To reduce the response time, in case of load variation, the PFCCOMP pin is clamped to a
minimum level of 2 V during PFC operation. Clamping prevents the on-time increasing too
much and improves the PFC response time when the load decreases again.
If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a
Zero-Current Signal (ZCS) 48 s after the last PFC MOSFET gate signal.
If valley signal is not detected on the PFCAUX pin, the controller generates a valley signal
4.2 s after demagnetization is detected.
To protect the internal circuitry during, for example, lightning events, add a 5 k series
resistor to the PFCAUX pin. To prevent incorrect switching due to external interference,
place the resistor close to the IC on the PCB.
To compensate for the influence of the mains input voltage, the TEA1755T contains a
correction circuit. The average input voltage is measured using the VINSENSE pin and
the information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
feature gives a fast transient response on load steps while still complying with class-D
MHR requirements.
In a typical application, a resistor and two capacitors connected to the PFCCOMP pin set
the regulation loop bandwidth.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
The start level and time constant of the increasing primary current level is externally
adjusted by changing the RSS1 and CSS1 values.
The charging current Istart(soft)PFC flows while the PFCSENSE pin voltage is < 0.5 V. If
VPFCSENSE exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC.
When the PFC starts switching, the Istart(soft)PFC current source is switched off; see
Figure 5.
S1 Istart(soft)PFC ≤ 60 μA
SOFT-START
SOFT-STOP
CONTROL
RSS1 11
OCP
PFCSENSE
CSS1
495 mV
RSENSE1
014aaa756
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.32 V or 1.92 V and a maximum voltage of 3.75 V. The lower clamp voltage depends on
VVINSENSE. This voltage limits the maximum power that is delivered when the PFC is
switched on again. The upper clamp voltage ensures that the PFC returns from low-power
mode to its normal regulation point in a limited time.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
A switch discharges the PFCTIMER pin capacitor when the flyback controller operating
frequency is > fsw(fb)swon(PFC) (73 kHz). At the same moment, the PFC stage is also
switched on.
Connect a capacitor to the PFCTIMER pin (see Section 7.2.7) to prevent the PFC from
switching off due to a dynamic load that leads to repetitive crossing of fsw(fb)swoff(PFC) and
fsw(fb)swon(PFC). A 1 nF minimum capacitor value is recommended to prevent noise
influencing the PFC switch on/ switch off behavior.
The PFCTIMER pin capacitor is also discharged when the flyback maximum switching
frequency is higher than 53 kHz. This feature prevents PFC on/off toggling during
dynamic loads causing the flyback to operate repetitively near fsw(fb)swoff(PFC) and
fsw(fb)swon(PFC).
It is also possible to control PFC switch-on and switch off externally. When VPFCTIMER is
driven below 1.03 V, the PFC stage is on. When the PFCTIMER pin voltage is driven
above 4.4 V, the PFC stage is switched off. The external control overrides the PFC stage
control by the flyback controller (see Figure 6).
The PFCTIMER pin has an internal clamp circuit starting around 10 V with a current
capability of 0.1 mA
14
PFCTIMER aaa-002670
Fig 6. PFC switch on and switch off using the PFCTIMER pin
At low VINSENSE input voltages, the output current is 8.1 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current is switched to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure a correct switch-off of the application, the VOSENSE current switches to its
maximum value of 8.1 A when VVOSENSE drops below 2.1 V.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
VVINSENSE
2.08 V 2.28 V
-8.1 μA
II(VOSENSE) aaa-004486
When VVOSENSE exceeds the VOVP(VOSENSE) level, switching of the PFC circuit is
prevented. Switching of the PFC restarts when the VOSENSE pin voltage drops below the
VOVP(VOSENSE) level again.
OVP is also triggered when the resistor between the VOSENSE pin and ground is open.
flyback
switching
frequency
130 kHz
Ipmin
frequency adjust
reduction
73 kHz
discontinuous
PFC off PFC on with valley quasi-resonant
53 kHz switching
36.5 kHz
25 kHz
burst mode
output power
aaa-002671
At high output power the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnetization of the transformer and detection of the valley. In
quasi-resonant mode switching losses are minimized. This minimization is achieved by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see Section 7.3.2).
To prevent high frequency operation at lower loads, the quasi-resonant operation switches
to discontinuous mode operation with valley skipping. When the frequency limit is
reached, the quasi-resonant operation changes to DCM with valley skipping. The
frequency limit reduces the MOSFET switch-on losses and conducted EMI.
At medium power levels, the controller enters Frequency Reduction (FR) mode. A Voltage
Controlled Oscillator (VCO) controls the frequency. The minimum frequency in this mode
is reduced to approximately 25 kHz. During frequency reduction mode, the primary peak
current is kept at an adjustable minimal level to maintain a high efficiency. Valley switching
is also active in this mode.
At very low power and standby levels, for which the switching frequency would drop below
25 kHz, the converter enters the burst mode. In burst mode, the switching frequency is
36.5 kHz. The primary peak current is fixed in burst mode.
In frequency reduction mode, the PFC controller switches off as soon as the flyback
switching frequency drops below 53 kHz. The flyback maximum frequency changes
linearly with the control VFBCTRL (see Figure 9). Hysteresis is added to ensure a stable
PFC switch-on and switch-off. In no-load operation, the switching frequency is reduced to
(almost) zero.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
FR DCM QR
fsw(fb)max
flyback
switching
frequency
PFC off PFC on
1
f = --------------------------------------------------- (3)
2 Lp Cd
When the secondary stroke ends and the internal oscillator voltage is high again, the
circuit waits for the lowest drain voltage before starting a new primary stroke.
Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation because capacitive switching losses are
reduced (see Equation 4). High frequency operation makes small and cost-effective
magnetic components possible.
1 2
P = --- C d V f (4)
2
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
drain
valley
secondary
stroke
(2) (1)
oscillator
014aaa027
The FBSENSE pin senses the primary current across an external resistor and compares it
to an internal control voltage. The internal control voltage is proportional to VFBCTRL (see
Figure 11).
The FBSENSE pin outputs a current of 2.1 A. This current runs through the resistors
from the FBSENSE pin to the sense resistor RSENSE and creates an offset voltage. The
minimum flyback peak current is adjusted using this offset voltage. Adjusting the minimum
peak current level, changes the frequency reduction slope (see Figure 8).
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Vsense(fb)max
545 mV
FBSENSE
PFC off PFC on offset voltage
SENSE resistor
peak voltage
flyback flyback
FBSENSE FR mode DCM or QR
peak voltage
232 mV
burst mode
0.77 2.8 4.0 4.9 VFBCTRL (V)
aaa-002673
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2.2 s.
This suppression can be necessary at low output voltages, during start-up and in
applications where the transformer has a large leakage inductance.
If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the
converter immediately stops. Operation restarts when the fault condition is removed.
If a capacitor and resistor are connected in series to the pin, a time-out function is created
which protects against open control loop situations. See Figure 12 and Figure 13. The
time-out function is disabled by connecting a resistor (200 k) to ground on the FBCTRL
pin.
Under normal operating conditions, the converter regulates the output voltage. VFBCTRL
varies between 0.77 V at minimum output power and 4.9 V at maximum output power.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
5.5 V 7V 29 μA
7.75 V
13.2 kΩ
time-out FBCTRL
aaa-002674
7.75 V
5.5 V
VFBCTRL
output
voltage
intended output restart intended output
voltage not reached voltage reached
within time-out time within time-out time
aaa-002675
In burst mode, the internal IC supply current is reduced to improve the no-load and
low-load input power.
The burst mode is exited and normal operation resumes when the VFBCTRL > 2.8 V (see
Figure 14).
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
load
Vout
2.8 V
FBCTRL 2.4 V
25 kHz = flyback frequency
0.77 V
flyback active
burst mode
FBDRIVER
aaa-002676
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of RSS2 and CSS2.
The soft-start current Istart(soft)fb switches on when VCC reaches Vstartup. When the
VFBSENSE reaches 0.55 V, the flyback converter starts switching.
The charging current Istart(soft)fb flows when the VFBSENSE is < 0.55 V. If VFBSENSE exceeds
0.55 V, the soft-start current source starts limiting the current. After the flyback converter
has started, the soft-start current source is switched off.
When the IC is operating in the burst mode, the soft-start function is switched off.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
SOFT START
CONTROL
RSS2
FBSENSE 10 OCP
CSS2 ocp level
RSENSE2
aaa-002677
An internal up-down counter prevents false OVP detection which can occur during ESD or
lightning events. The internal counter counts up by one when the output voltage exceeds
the OVP trip level within one switching cycle. The internal counter counts down by two
when the output voltage has not exceeded the OVP trip level in one switching cycle.
When the counter has reached six, the IC assumes a true overvoltage, sets the latched
protection and switches off both converters.
The converter only restarts after the OVP latch is reset. In a typical application, the
internal latch is reset when the VINSENSE voltage drops below 750 mV and is then raised
to 860 mV. The latched protection is also reset by removing both the VCC and VHV.
The demagnetization resistor, RFBAUX sets the output voltage Vo(OVP) at which the OVP
function trips:
Ns
V o OVP = ----------- I ovp FBAUX R FBAUX + V clamp FBAUX (7)
N aux
where Ns is the number of secondary winding and Naux is the number of auxiliary winding
of the transformer. Current Iovp(FBAUX) is internally trimmed.
Accurate OVP detection is made possible by adjusting the value of RFBAUX to the turns
ratio of the transformer.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
tleb
OCP level
VFBSENSE
t
014aaa022
The current information is used to limit the maximum flyback converter peak current and is
measured using the FBSENSE pin. The internal compensation is such, that a maximum
output power is obtained which is almost independent of the input voltage.
VFBSENSE
(mV)
545
400
-360 -100 0
IFBAUX (μA)
aaa-002678
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
8. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Voltages
VCC supply voltage 0.4 +38 V
VLATCH voltage on pin LATCH current limited 0.4 +10 V
VFBCTRL voltage on pin FBCTRL 0.4 +9 V
VPFCCOMP voltage on pin PFCCOMP 0.4 +5 V
VVINSENSE voltage on pin VINSENSE current limited 0.4 +10 V
VVOSENSE voltage on pin VOSENSE current limited 0.4 +10 V
VPFCAUX voltage on pin PFCAUX 25 +25 V
VFBSENSE voltage on pin FBSENSE current limited 0.4 +5 V
VPFCSENSE voltage on pin PFCSENSE current limited 0.4 +5 V
VPFCTIMER voltage on pin PFCTIMER current limited 0.4 +10 V
VHV voltage on pin HV 0.4 +650 V
Currents
IFBCTRL current on pin FBCTRL 3 0 mA
IFBAUX current on pin FBAUX 1 +1 mA
IPFCSENSE current on pin PFCSENSE 1 +10 mA
IFBSENSE current on pin FBSENSE 1 +10 mA
IFBDRIVER current on pin FBDRIVER < 10 % 0.8 +2 A
IPFCDRIVER current on pin PFCDRIVER < 10 % 0.8 +2 A
IHV current on pin HV during start-up - 8 mA
and restart
= 3 % due to 15 +30 mA
dV/dt on HV pin
General
Ptot total power dissipation Tamb < 75 C - 0.6 W
Tstg storage temperature 55 +150 C
Tj junction temperature 40 +155 C
ESD
VESD electrostatic discharge human body
voltage model
pins 1 to 14 [1] 2 2 kV
pin 16 (HV) [1] 1.5 1.5 kV
charged device 500 500 V
model
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
9. Thermal characteristics
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air; JEDEC test board 127 K/W
Rth(j-c) thermal resistance from junction to case in free air; JEDEC test board 36 K/W
10. Characteristics
Table 5. Characteristics
Tamb = 25 C; VCC = 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Start-up current source (HV pin)
IHV current on pin HV VHV > 75 V
VCC < Vtrip 0.9 1.1 1.3 mA
Vth(UVLO) < VCC < Vstartup 0.8 1 1.2 mA
Vtrip < VCC < Vth(UVLO) 4 5 6 mA
with auxiliary supply - - 1.5 A
in Power-down mode; VCC = 0 V 5 12 25 A
VBR breakdown voltage 650 - - V
Supply voltage management (VCC pin)
Vtrip trip voltage 0.5 0.6 0.7 V
Vstartup start-up voltage 21.3 22.3 23.3 V
Vth(UVLO) undervoltage lockout 12.4 13.4 14.4 V
threshold voltage
Vhys hysteresis voltage Vstartup Vth(UVLO) 8.3 8.9 9.5 V
Vprot(UVLO) undervoltage lockout - Vth(UVLO) - V
protection voltage + 0.8
Ich(low) low charging current VHV > 75 V
VCC < Vtrip 1.15 1 0.85 mA
Vth(UVLO) < VCC < Vstartup 1.05 0.9 0.75 mA
Ich(high) high charging current VHV > 75 V; Vtrip < VCC < Vth(UVLO) 5.8 4.9 4 mA
ICC(oper) operating supply no-load on pins FBDRIVER and 2.45 2.7 2.95 mA
current PFCDRIVER; VFBCTRL = 5 V;
fFB = fPFC = 100 kHz; = 30 %
IC in burst mode; no-load on pins 1.75 1.95 2.15 mA
FBDRIVER and PFCDRIVER;
flyback switching; VFBCTRL = 1.6 V;
VPFCSENSE = 0 V
IC in burst mode; flyback not 1.24 1.35 1.46 mA
switching; VFBCTRL = 0 V;
VPFCSENSE = 0 V
ICC(prot) protection supply time-out protection triggered; 0.3 0.45 0.6 mA
current VHV = 0 V
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
[1] A typical application with a compensation network on the PFCCOMP pin, such as the example in Figure 3.
[2] The clamp voltage on the PFCCOMP pin is dependent on the VINSENSE voltage. When the VVINSENSE rises above
Vth(sel)clmp + Vth(sel)clmp(hys), the high clamp level is active. When the voltage on the VINSENSE pin drops below the Vth(sel)clmp level
again, the low clamp level is active.
[3] Guaranteed by design.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Capacitor CVCC buffers the IC supply voltage. The IC supply voltage is powered using the
high voltage rectified mains during start-up and the auxiliary winding of the flyback
converter during operation. Sense resistors RSENSE1 and RSENSE2 convert the current
through the MOSFETs S1 and S2 into a voltage on the PFCSENSE and FBSENSE pins.
The RSENSE1 and RSENSE2 values define the maximum primary peak current in MOSFETs
S1 and S2.
In the example, the LATCH pin is connected to a Negative Temperature Coefficient (NTC)
resistor. The protection is activated when the resistance drops below a value as calculated
in Equation 8:
V prot LATCH
------------------------------- = 16.2 k (8)
I O LATCH
A capacitor CTIMEOUT is connected to the FBCTRL pin. RLOOP ensures that the time-out
capacitor does not interfere with the normal regulation loop.
RS1 and RS2 are added to prevent the soft-start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor RAUX1 is added to protect the IC from damage during lightning events.
RS3 and RCOMP are added to compensate for input voltage variations. The (stray)
capacitance on the drain of MOSFET S2 affects the frequency reduction slope and
therefore, the PFC switch-on and switch-off levels. Choosing the proper values for RS3
and RCOMP results in an input voltage independent PFC switch-on and switch-off power
level.
RDRV1 and RDRV2 prevent the output drivers from being damaged due to, for example,
power MOSFET avalanche.
In the application, the HV pin of the IC can either be connected to the center tap of the
flyback transformer or to the drain of MOSFET S2
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
D2
Tr1
RDRV1 R4 Cbulk
S1 Tr2
RCOMP D4
C6 VOUT
D1 CSS1 RSS1 RSENSE1 R5 (1)
C1 S2
RAUX1 RDRV2
Z1
RS1
PFCDRIVER
OPTO-
PFCSENSE
FBDRIVER
VOSENSE
Vmains FEEDBACK
CSS2
HV
PFCAUX 12 11 9 16 13 FBSENSE RS2 RSS2 RS3
8 10
C3 R3 PFCCOMP
6
RSENSE2 RFBAUX
IC D3
R1 C4 VINSENSE FBAUX
7 4
VCC
FBCTRL 1
R2 C2 3 LATCH
2 14 5
GND PFCTIMER
RNTC CVCC
CPFCTIMER C5
RLOOP
CTIMEOUT
OPTO-FEEDBACK
aaa-002624
(1) In the application, the HV pin of the IC can either be connected to the center tap of the flyback transformer or to the drain of
MOSFET S2.
Fig 18. TEA1755T typical application diagram
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
99-12-27
SOT109-1 076E07 MS-012
03-02-19
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
14.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any
may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and
authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for
the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy
in accordance with automotive testing or application requirements. NXP between the translated and English versions.
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in 14.4 Trademarks
automotive applications to automotive specifications and standards, customer
Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
are the property of their respective owners.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond GreenChip — is a trademark of NXP B.V.
NXP Semiconductors’ specifications such use shall be solely at customer’s
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 7.3.10 Overcurrent protection (FBSENSE pin) . . . . . 20
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 7.3.11 Overpower protection. . . . . . . . . . . . . . . . . . . 20
2.1 Distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 7.3.12 Driver (FBDRIVER pin) . . . . . . . . . . . . . . . . . 20
2.2 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 PFC green features . . . . . . . . . . . . . . . . . . . . . 2 9 Thermal characteristics . . . . . . . . . . . . . . . . . 22
2.4 Flyback green features . . . . . . . . . . . . . . . . . . . 2 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Protection features . . . . . . . . . . . . . . . . . . . . . . 2
11 Application information . . . . . . . . . . . . . . . . . 29
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
14 Legal information . . . . . . . . . . . . . . . . . . . . . . 33
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Functional description . . . . . . . . . . . . . . . . . . . 5 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 General control . . . . . . . . . . . . . . . . . . . . . . . . . 5 15 Contact information . . . . . . . . . . . . . . . . . . . . 34
7.1.1 Start-up and UnderVoltage LockOut (UVLO) . . 5 16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 7
7.1.3 Supply management. . . . . . . . . . . . . . . . . . . . . 8
7.1.4 Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1.5 Fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1.6 Overtemperature protection . . . . . . . . . . . . . . . 8
7.2 Power factor correction circuit . . . . . . . . . . . . . 8
7.2.1 ton control (PFCCOMP pin). . . . . . . . . . . . . . . . 8
7.2.2 Valley switching and demagnetization
(PFCAUX pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.3 Frequency limitation . . . . . . . . . . . . . . . . . . . . . 9
7.2.4 Mains voltage compensation (VINSENSE pin). 9
7.2.5 Soft-start (PFCSENSE pin). . . . . . . . . . . . . . . . 9
7.2.6 PFC switch on/switch off control. . . . . . . . . . . 10
7.2.7 PFC switch off delay (PFCTIMER pin) . . . . . . 10
7.2.8 Dual-boost PFC . . . . . . . . . . . . . . . . . . . . . . . 11
7.2.9 Overcurrent protection (PFCSENSE pin) . . . . 12
7.2.10 Mains undervoltage lockout/brownout
protection (VINSENSE pin) . . . . . . . . . . . . . . 12
7.2.11 Overvoltage protection (VOSENSE pin) . . . . . 12
7.2.12 PFC open-loop protection (VOSENSE pin) . . 12
7.2.13 Driver (PFCDRIVER pin) . . . . . . . . . . . . . . . . 12
7.3 Flyback controller . . . . . . . . . . . . . . . . . . . . . . 12
7.3.1 Multimode operation . . . . . . . . . . . . . . . . . . . . 13
7.3.2 Valley switching (HV pin) . . . . . . . . . . . . . . . . 14
7.3.3 Current mode control (FBSENSE pin) . . . . . . 15
7.3.4 Demagnetization (FBAUX pin) . . . . . . . . . . . . 16
7.3.5 Flyback control/time-out (FBCTRL pin) . . . . . 16
7.3.6 Burst mode operation (FBCTRL pin) . . . . . . . 17
7.3.7 Soft-start (FBSENSE pin) . . . . . . . . . . . . . . . . 18
7.3.8 Maximum on-time . . . . . . . . . . . . . . . . . . . . . . 19
7.3.9 Overvoltage protection (FBAUX pin) . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.