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TPS81256
SLVSAZ9D – JUNE 2012 – REVISED FEBRUARY 2018

TPS81256 3-W, High Efficiency Step-Up Converter In MicroSiP™ Packaging

1 Features 3 Description
•
1 91% Efficiency at 4MHz Operation The TPS81256 device is a complete MicroSiP DC/DC
step-up power solution intended for battery-powered
• Wide VIN Range From 2.5V to 5.5V portable applications. Included in the package are the
• IOUT ≥550mA at VOUT = 5.0V, VIN ≥3.3V switching regulator, inductor and input/output
• Fixed Output Voltage 5.0V capacitors. Only a tiny additional output capacitor is
• ±2% Total DC Voltage Accuracy required to finish the design.
• 43µA Supply Current The TPS81256 is based on a high-frequency
synchronous step-up DC/DC converter optimized for
• Best-in-Class Line and Load Transient
battery-powered portable applications.
• VIN ≥ VOUT Operation
The DC/DC converter operates at a regulated 4-MHz
• Low-Ripple Light-Load PFM Mode
switching frequency and enters power-save mode
• True Load Disconnect During Shutdown operation at light load currents to maintain high
• Thermal Shutdown and Overload Protection efficiency over the entire load current range.
• Sub 1-mm Profile Solution The PFM mode extends the battery life by reducing
• Total Solution Size <9mm2 the supply current to 43μA (typical) during light load
• 9-Pin MicroSiP Packaging operation. Intended for low-power applications, the
TPS81256 supports more than 3W output power over
a full Li-Ion battery voltage range. Input current in
2 Applications shutdown mode is less than 1µA (typical), which
• Cell Phones, Smart-Phones, Tablet PCs maximizes battery life.
• Mono and Stereo APA Applications The TPS81256 offers a very small solution size of
• USB-OTG, HDMI Applications less than 9mm2 due to minimum amount of external
• USB Charging Port (5V) components. The solution is packaged in a compact
(2.6mm x 2.9mm) and low profile (1.0mm) BGA
package suitable for automated assembly by
standard surface mount equipment.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS81256 µSIP (9) 2.925 mm × 2.575 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
TPS81256SIP
Efficiency vs Load Current
L DC/DC Converter VOUT = 5.0 V
L VOUT VO = 5.0 V
100

VIN
VIN 90
2.5 V .. 4.85 V
CO 4.7µF
80
CI EN GND 16V X5R (0603)

70

60
Efficiency - %

ENABLE 50

40
.
GND 30

20

10
397.9
199.4

0
100.0
50.1
5.5

25.1
5.5
5.3

12.6
5.1

6.3
4.9

mA
4.7

nt -
3.2
4.5

urre
4.3

1.6

VI -
4.1

Inp ut C
0.8
3.9

ut V
Outp
3.7

0.4

olta
IO -
3.5

ge -
3.3

0.2
3.1

V
0.1
2.9

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS81256
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Table of Contents
1 Features .................................................................. 1 9 Application and Implementation ........................ 12
2 Applications ........................................................... 1 9.1 Application Information............................................ 12
3 Description ............................................................. 1 9.2 Typical Application ................................................. 12
4 Revision History..................................................... 2 9.3 System Examples .................................................. 15
5 Device Options....................................................... 3 10 Power Supply Recommendations ..................... 17
6 Pin Configuration and Functions ......................... 3 11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
7 Specifications......................................................... 4
11.2 Layout Example .................................................... 17
7.1 Absolute Maximum Ratings ...................................... 4
11.3 Surface Mount Information ................................... 18
7.2 ESD Ratings ............................................................ 4
11.4 Thermal and Reliability Information ...................... 18
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 20
7.5 Electrical Characteristics........................................... 5 12.1 Device Support...................................................... 20
7.6 Typical Characteristics .............................................. 6 12.2 Community Resources.......................................... 20
12.3 Trademarks ........................................................... 20
8 Detailed Description .............................................. 9
12.4 Electrostatic Discharge Caution ............................ 20
8.1 Overview ................................................................... 9
12.5 Glossary ................................................................ 20
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes........................................ 11
Information ........................................................... 21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (February 2016) to Revision D Page

• Updated package drawing .................................................................................................................................................... 22

Changes from Revision B (February 2015) to Revision C Page

• Reversed D & E dimensions in to match MECHANICAL DATA drawing; and, changed "8-bump" to "9-bump" in the
description. ........................................................................................................................................................................... 21
• Added Community Resources section ................................................................................................................................ 21

Changes from Revision A (August 2013) to Revision B Page

• Added Device Information and ESD Ratings tables, Feature Description section, Device Functional Modes,
Application and Implementation section, System Examples, Power Supply Recommendations section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
• Changed the pinout drawing to match the device orientation shown on the MECHANICAL DATA drawing. ...................... 3
• Changed SIP Package "Top View" image orientation to correctly match "YML LSB" symbolization with pin A1. .............. 21

Changes from Original (June 2012) to Revision A Page

• Added animated performance characteristics table ............................................................................................................... 6

• Deleted MLCC capacitor B1 life documentation................................................................................................................... 19

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5 Device Options

PACKAGE MARKING
PART NUMBER OUTPUT VOLTAGE
CHIP CODE
TPS81256 5.0V TT

6 Pin Configuration and Functions

SIP Package
9-Pin µSIP
SIP-9 SIP-9
(TOP VIEW) (BOTTOM VIEW)

VIN C1 B1 A1 GND GND A1 B1 C1 VIN

VIN C2 B2 A2 GND GND A2 B2 C2 VIN
VOUT C3 B3 A3 VOUT VOUT A3 B3 C3 VOUT

EN EN

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
EN B2 I mode. Pulling this pin high enables the device. This pin must not be left floating and must be
terminated.
GND A1, A2, B1 Ground pin.
VIN C1, C2 I Power supply input.
VOUT A3, B3, C3 O Boost converter output.

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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage Voltage at VIN (2), VOUT (2), EN (2) –0.3 6 V
(3)
Continuous average current into VIN 1.05 A
Input current
Pulsed current into VIN (4) 1.3 A
Power dissipation Internally limited
Operating temperature, TA (3) (4) (5) –40 85 °C
Operating virtual junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Limit the junction and the (top side) inductor case temperature to 110°C, limit the (top side) capacitor case temperature to 85°C for
2000h operation at maximum output power. Contact TI for more details on lifetime estimation.
(4) Limit the (top side) inductor case temperature to 140°C and the (top side) capacitor temperature to 115°C for 100h operation. Contact TI
for more details on lifetime estimation.
(5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 125°C, a maximum inductor case temperature of 125°C
and a maximum capacitor case temperature of 85°C.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all ±2000
pins (1)
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification ±1000 V
JESD22-C101, all pins (2)
Machine Model - (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage range 2.5 5.5 V
RL Minimum resistive load for start-up (VI ≤ 4.8V) 65 Ω
CEXT Output capacitance 2 30 µF
TA Ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
TCASE_IND Operating inductor case temperature 125 °C
TCASE_CAP Operating capacitor case temperature 85 °C

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7.4 Thermal Information

TPS81256
THERMAL METRIC (1) UNIT
µSIP (SIP) – 9 PINS
RθJA Junction-to-ambient thermal resistance 62
ψJB Junction-to-board characterization parameter 31 °C/W
ψJT Junction-to-case (top) thermal resistance –

(1) Thermal data have been simulated with high-K board (per JEDEC standard).

7.5 Electrical Characteristics

Minimum and maximum values are at VIN = 2.5V to 5.5V, VOUT = 5.0V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to
85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT
= 5.0V, EN = 1.8V, TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
(1)
Operating quiescent current into VIN IOUT = 0mA, VOUT = 5.0V, VIN = 3.6V 30 50 µA
IQ (1)
EN = VIN
Operating quiescent current into VOUT Device not switching 7 20 µA
(1)
ISD Shutdown current EN = GND 0.85 5.0 μA
Falling 2.0 2.1 V
VUVLO Under-voltage lockout threshold
Hysteresis 0.1 V
ENABLE
VIL Low-level input voltage 0.4 V
VIH High-level input voltage 1.0 V
Ilkg Input leakage current Input connected to GND or VIN 0.5 µA
OUTPUT
2.5V ≤ VIN ≤ 4.85V, IOUT = 0mA
4.92 5 5.08 V
PWM operation. Open Loop
3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 550mA
VOUT Regulated DC output voltage 4.85 5 5.2 V
PFM/PWM operation
2.9V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 450mA
4.85 5 5.2 V
PFM/PWM operation
Power-save mode output ripple voltage PFM operation, IOUT = 1mA 35 mVpk
ΔVOUT
PWM mode output ripple voltage PWM operation, IOUT = 200mA 8 mVpk
POWER SWITCH
rDS(on) Input-to-output On-resistance VI = 5.25 V. Device not switching 320 mΩ
Ilkg Reverse leakage current into VOUT (1) EN = GND 5 µA
ILIM Average input current limit EN = VIN. VIN = 3.3V 1180 mA
Overtemperature protection 140 °C
Overtemperature hysteresis 20 °C
OSCILLATOR
fOSC Oscillator frequency VIN = 3.6V, VOUT = 5.0V, IOUT = 500mA 4 MHz
TIMING
IOUT = 0mA
70 µs
Time from active EN to start switching
Start-up time
IOUT = 0mA
400 µs
Time from active EN to VOUT

(1) Maximum values can vary over lifetime due to intrinsic capacitor ageing effects. For more details, refer to Thermal and Reliability
Information section.

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7.6 Typical Characteristics

Table 1. Table of Graphs
FIGURE
vs Output current Figure 1, Figure 3
η Efficiency
vs Input voltage Figure 2
vs Output current Figure 4, Figure 5,
VO DC output voltage Figure 6
vs Input voltage Figure 7
IO Maximum output current vs Input voltage Figure 8
ΔVO Peak-to-peak output ripple voltage vs Output current Figure 8
ICC Supply current vs Input voltage Figure 10
ILIM Input current vs Output current Figure 11

Table 2. Table of Animated Performance Characteristics

VIDEO
AC Load Response vs. Input Voltage Video 1
Load Transient Response (10mA to 400mA) vs. Input Voltage Video 2
vs. Base Load Current (2.9VIN) Video 3
Load Transient Response (to 400mA) vs. Base Load Current (3.6VIN) Video 4
vs. Base Load Current (4.2VIN) Video 5
vs. Delay to Load Current (2.9VIN) Video 6
Start-Up Response vs. Delay to Load Current (3.6VIN) Video 7
vs. Delay to Load Current (4.2VIN) Video 8
Start-Up Response (200mA IOUT) vs. Input Voltage Video 9
Overload Response vs. Input Voltage Video 10

100 100
VO = 5 V,
98
95 VI = 3.6 V PFM/PWM Operation
VI = 4.2 V 96 IO = 300 mA
90 VI = 4.5 V 94
92 IO = 100 mA
85
90
Efficiency - %
Efficiency - %

80 VI = 3.3 88
VI = 2.9 V 86
75 VI = 2.7 V
84 IO = 10 mA
70 82
IO = 1 mA
80
65 IO = 500 mA
78
60 76
VO = 5 V, 74
55
PFM/PWM Operation 72
50 70
0.1 1 10 100 1000 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
IO - Output Current - mA VI - Input Voltage - V
Figure 1. Efficiency vs Output Current Figure 2. Efficiency vs Input Voltage

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100 5.15
VI = 3.6 V, VO = 5 V,
PFM/PWM Operation
95 VO = 5 V,
PFM/PWM Operation TA = -40°C
VI = 5.1 V
90 5.1

VO - DC Output Voltage - V
85 TA = 25°C
Efficiency - %

TA = 85°C
80 5.05 VI = 4.5 V
VI = 3.6 V
75

70 5

VI = 2.7 V
65

60 4.95
0.1 1 10 100 1000 0.1 1 10 100 1000
IO - Output Current - mA IO - Output Current - mA
Figure 3. Efficiency vs Output Current Figure 4. DC Output Voltage vs Output Current
5.05 VI = 3.2 V, TA = 85°C VI = 4.3 V,
5.05
TA = 85°C
VO = 5 V,
VI = 3.6 V, TA = 85°C
PWM Operation
5
5.03 VI = 4.3 V,
VI = 3.2 V, TA = 25°C
TA = 25°C
VO - DC Output Voltage - V

VI = 3.6 V, TA = 25°C VO - DC Output Voltage - V

4.95 VI = 2.7 V
5.01 VI = 2.9 V
VI = 4.3 V, TA = -40°C
VI = 3.2 V
VI = 3.6 V, TA = -40°C 4.9
VI = 3.3 V
4.99 VI = 3.6 V
VI = 3.2 V, TA = -40°C
4.85 VI = 4.2 V
VI = 4.5 V
4.97
4.8
VO = 5 V,
PFM/PWM Operation
4.95 4.75
0.1 1 10 100 1000 200 300 400 500 600 700 800 900 1000 1100
IO - Output Current - mA IO - Output Current - mA
Figure 5. DC Output Voltage vs Output Current Figure 6. DC Output Voltage vs Output Current
5.55 1200
VO = 5 V, VO = 5 V,
5.5 PFM/PWM Operation 1100 PWM Operation
5.45
IO - Maximum Output Current - mA

1000
5.4
VO - DC Output Voltage - V

IO = 500 mA 900
5.35

5.3 IO = 100 mA 800

TA = -40°C
5.25 700
IO = 10 mA
5.2 600 TA = 25°C

5.15
500
5.1 TA = 85°C
400
5.05

5 300

4.95 200
2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5
VI - Input Voltage - V VI - Input Voltage - V
Figure 7. DC Output Voltage vs Input Voltage Figure 8. Maximum Output Current vs Input Voltage

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50 75
VO = 5 V,
VO - Peak-to-Peak Output Ripple Voltage - mV VO = 5 V, 70
45 IO = 0 mA
PFM/PWM Operation 65
40 60 TA = 85°C

55 TA = 25°C

Supply Current - mA
35
50
30 45
40
25 VI = 3.6 V
35
VI = 3.3 V TA = -40°C
20 30
VI = 2.7 V
25
15
20
10 15
VI = 4.2 V 10
5
5
0 0
0 100 200 300 400 500 600 700 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
VI - Input Voltage - V

Figure 9. Peak-To-Peak Output Ripple Voltage vs Output Figure 10. Supply Current vs Input Voltage
Current
1.3
VO = 5 V,
1.2
PFM/PWM Operation
1.1
VI = 2.6 V
1
VI = 3 V
IIN - Input Current - mA

0.9
VI = 3.3 V
0.8
VI = 3.6 V
0.7
VI = 4.2 V
0.6 VI = 4.5 V
0.5
0.4
0.3
0.2
0.1
0
0 100 200 300 400 500 600 700 800 900 1000

Figure 11. Input Current vs Output Current

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8 Detailed Description

8.1 Overview
The TPS81256 is a stand-alone, synchronous, step-up converter module. The converter operates at a quasi-
constant 4-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load
currents, the TPS81256 converter operates in power-save mode with pulse frequency modulation (PFM).

8.2 Functional Block Diagram

VIN

CI

2.2µF
L
1µH

DC/DC CONVERTER

VOUT
CO
NMOS PMOS
Gate Driver

2.2µF x2
Valley
Current
Sense

Modulator
Amplifier
Error

Softstart VREF

Thermal
Control Shutdown
EN
Logic
Undervoltage
Lockout

GND

8.3 Feature Description

8.3.1 Operation
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time.
At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps
up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer
has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally,
the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

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Feature Description (continued)

In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain
amount above the input voltage. The TPS81256 device operates differently as it can smoothly transition in and
out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits
even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the
output current capability of the regulator is limited to ca. 150mA. Refer to the typical characteristics section (DC
Output Voltage vs. Input Voltage) for further details.
The current mode architecture with adaptive slope compensation provides excellent transient load response
while requiring only one external tiny capacitor for output filtering and loop stability purposes. Internal soft-start
and loop compensation simplifies the application design process.

8.3.2 Power-Save Mode

The TPS81256 integrates a power-save mode to improve efficiency at light load. In power-save mode the
converter only operates when the output voltage trips below a set threshold voltage.
It ramps up the output voltage with several pulses and goes into power save mode when the output voltage
exceeds the set threshold voltage.
PFM mode is exited and the PWM mode entered in case the output current can no longer be supported in PFM
mode.

Figure 12. Power-Save Example

8.3.3 Current Limit Operation, Maximum Output Current

The TPS81256 directly and accurately controls the average input current through intelligent adjustment of the
valley current limit. The current limit circuit employs a valley current sensing scheme. Current limit detection
occurs during the off-time by sensing of the voltage drop across the synchronous rectifier.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by
Equation 1.

VOUT
IOUT(DC) = IIN(CL) g g h
VIN
(1)
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the
current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).
When the current limit is reached the output voltage decreases during further load increase.

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8.4 Device Functional Modes

8.4.1 Softstart, Enable
The TPS81256 device starts operation when EN is set high and starts up with the soft-start sequence. For proper
operation, the EN pin must be terminated and must not be left floating.
The TPS81256 device has an internal softstart circuit that limits the inrush current during start-up. The first step
in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output
capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approx. 200mA)
during this phase. This mechanism is used to limit the output current under short-circuit condition.
Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start
system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the
output voltage is reached, the regulation loop takes control and full current operation is permitted.
Pulling the EN pin low forces the device in shutdown, with a shutdown current of typically 1µA. In this mode, true
load disconnect between the battery and load prevents current flow from VIN to VOUT, as well as reverse flow
from VOUT to VIN.

8.4.2 Load Disconnect and Reverse Current Protection

Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will
be discharge during shutdown. The advantage of TPS81256 is that this converter is disconnecting the output
from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected
battery it prevents it from being discharge during shutdown of the converter.

8.4.3 Undervoltage Lockout

The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery
from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage
lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO
threshold plus its hysteresis of 100 mV at typically 2.1V.

8.4.4 Thermal Regulation

The TPS81256 device contains a thermal regulation loop that monitors the die temperature during the pre-charge
phase. If the die temperature rises to high values of about 110°C, the device automatically reduces the current to
prevent the die temperature from increasing further. Once the die temperature drops about 10°C below the
threshold, the device will automatically increase the current to the target value. This function also reduces the
current during a short-circuit condition.

8.4.5 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 140°C (typically) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the
thermal shutdown minus its hysteresis, the device continuous the operation.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS81256 device is a complete MicroSiP™ DC/DC step-up power solution intended for battery-powered
portable applications.

9.2 Typical Application

TPS81256
L DC/DC Converter
L VOUT VOUT

VIN VIN Co
CI CEXT
EN GND

ENABLE

GND
Figure 13. 5-V Power Supply

9.2.1 Design Requirements

The following design guidelines provide a component selection process for the typical application circuit shown to
operate the device within the Recommended Operating Conditions.

9.2.2 Detailed Design Procedure

9.2.2.1 Output Capacitor Selection CEXT

Because of the pulsating output current nature of the boost converter, a low ESR output capacitor is required to
maintain control loop stability, to enhance the converter's transient response and to reduce the output voltage
ripple. For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible
to the VOUT and GND pins of the IC. The minimum capacitance is 2μF.
To get an estimate of the steady ripple due to charging and discharging the output capacitance, Equation 2 can
be used.
IOUT g (VOUT - VIN )
DV =
C g VOUT g f
(2)
Where f is the switching frequency which is 4MHz (typically.) and C is the effective output capacitance. Notice
the TPS81256 device already incorporates ca. 1.2μF effective output capacitance.
In practice, the total ripple is larger due to the ESR of the output capacitor. This additional component of the
ripple can be calculated using Equation 3:
VESR = IOUT g RESR (3)

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Typical Application (continued)

An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. The
output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their
wide variation in capacitance over temperature, become resistive at high frequencies. There are no additional
requirements regarding minimum ESR. Larger capacitors cause lower output voltage ripple as well as lower
output voltage drop during load transients but the total output capacitance value should not exceed ca. 30µF.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 4.7µF X5R 16V 0603 MLCC capacitor would typically show an
effective capacitance of less than 2.5µF (under 5V bias condition, high temperature and ageing effects).
Because the damping factor in the output path is directly related to several resistive parameters (e.g. inductor
DCR, power-stage rDS(on), PWB DC resistance, load switches rDS(on) …) that are temperature dependant, the
converter small and large signal behavior must be checked over the input voltage range, load current range and
temperature range.
The easiest sanity test is to evaluate, directly at the converter’s output, the following aspects:
• PFM/PWM efficiency
• PFM/PWM and PWM load transient response
During the recovery time from a load transient, the output voltage can be monitored for settling time, overshoot or
ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase
margin.

Table 3. Recommended Capacitor CEXT

REFERENCE DESCRIPTION PART NUMBER, MANUFACTURER (1)
CEXT 4.7μF, 16V, 0603, X5R ceramic GRM188R61C475KAAJ, muRata

(1) See Third-Party Products Disclaimer

9.2.2.2 Input Capacitor Selection
In a dc/dc boost converter, since the input current is continuous, only minimum input capacitance is required. The
TPS81256 device integrates a low ESR decoupling capacitor to prevent large voltage transients that can cause
misbehavior of the device or interference in other circuits in the system.
For most applications, the input capacitor that is integrated into the TPS81256 should be sufficient. If the
application exhibits a noisy or erratic switching frequency, experiment with additional input capacitance to find a
remedy. Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as
they have extremely low ESR and are available in small footprints. Additional input capacitors should be located
as close as possible to the device.
The TPS81256 uses a tiny ceramic input capacitor. When a ceramic capacitor is combined with trace or cable
inductance, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing
can couple to the output and be mistaken as loop instability or can even damage the part. In this circumstance,
additional "bulk" capacitance, such as electrolytic or tantalum, should be placed between the input of the
converter and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CI.

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9.2.3 Application Curves

VI = 3.6 V,
VO = 5.0 V

VI = 2.7 V

VI = 4.5 V

VI = 3.6 V

830mA
670mA

Load Sweep, up to 830mA

VO = 5.0 V,
IO = 0 mA

Figure 14. Start-Up Figure 15. Overload Recovery Response

VI = 3.6 V, VI = 3.6 V,
VO = 5.0 V VO = 5.0 V

0 to 500mA Load Sweep

40 to 400 mA Load Step

Figure 16. AC Load Transient Figure 17. Load Transient Response

In PFM/PWM Operation

VI = 2.7 V, VI = 4.5 V,
VO = 5.0 V VO = 5.0 V

40 to 400 mA Load Step 40 to 400 mA Load Step

Figure 18. Load Transient Response Figure 19. Load Transient Response In PFM/PWM
In PFM/PWM Operation Operation

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VO = 5.0 V

40mA to 400mA
Load Step

3.2V to 3.8V Line Step

Figure 20. Combined Line/Load Transient Response

9.3 System Examples

TPS81256SIP

L DC/DC Converter
5.0 V, up to 550mA
L VOUT
(1)
CDECOUPLING
VIN
VIN 4.7µF
3.3 V .. 4.8 V
CO CLASS-D APA
CI EN GND Audio Input
Audio Input

EN APA
EN DC/DC

GND

(1)
The capacitor is not only required to decouple the audio power amplifier,
but is also required to stable operation of the SMPS converter.
The SMPS converter should be located in the close vicinity of the audio power amplifier.

Figure 21. "Boosted" Audio Power Supply

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System Examples (continued)

TPS81256SIP

L DC/DC Converter
VUSB
L VOUT
5V, 500mA
VIN USB-DCP Port
VIN
3.0 V .. 4.35 V 4.7µF
CO
16V X5R (0603)
CI EN GND

ENABLE

GND

bq24156A
VBUS = +5V LO 1.0 mH RSNS VBAT
VBUS SW
CIN 68mW CO CO
CBOOT
1 mF 10 mF 47 mF
10 nF
PMID BOOT PACK+
CIN CCSIN
PGND
4.7 mF 0.1 mF
CSIN

CSOUT PACK–
SCL CCSOUT
SDA
0.1 mF
STAT
OTG VREF
CVREF
CD
1 mF

Figure 22. Battery Powered USB-DCP Power Supply

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10 Power Supply Recommendations

The TPS81256 has no special requirements for its input power supply. The input power supply's output current
needs to be rated according to the supply voltage, output voltage and output current of the TPS81256

11 Layout

11.1 Layout Guidelines

In making the pad size for the µSiP LGA balls, it is recommended that the layout use non-solder-mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 23 shows the appropriate diameters for a MicroSiP
layout.

11.2 Layout Example

Copper Trace Width

Solder Pad Width

Solder Mask Opening

Solder Mask Thickness Copper Trace Thickness

M0200-01

Figure 23. Recommended Land Pattern Image and Dimensions

(5)
SOLDER PAD SOLDER MASK COPPER STENCIL (6)
COPPER PAD STENCIL THICKNESS
DEFINITIONS (1) (2) (3) (4) OPENING THICKNESS OPENING
Non-solder-mask
0.30mm 0.360mm 1oz max (0.032mm) 0.34mm diameter 0.1mm thick
defined (NSMD)

(1) Circuit traces from non-solder-mask defined PWB lands should be 75μm to 100μm wide in the exposed area inside the solder mask
opening. Wider trace widths reduce device stand off and affect reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5mm to avoid a reduction in thermal fatigue
performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
(6) For best solder stencil performance use laser cut stencils with electro polishing. Chemically etched stencils give inferior solder paste
volume control.

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11.3 Surface Mount Information

The TPS81256 MicroSiP DC/DC converter uses an open frame construction that is designed for a fully
automated assembly process and that features a large surface area for pick and place operations. See the "Pick
Area" in the package drawings.
Package height and weight have been kept to a minimum thereby to allow the MicroSiP device to be handled
similarly to a 0805 component.
See JEDEC/IPC standard J-STD-20b for reflow recommendations.

11.4 Thermal and Reliability Information

The TPS81256 output current may need to be de-rated if it is required to operate in a high ambient temperature
or deliver a large amount of continuous power. The amount of current de-rating is dependent upon the input
voltage, output power and environmental thermal conditions. Care should especially be taken in applications
where the localized PWB temperature exceeds 65°C.
The TPS81256 die and inductor temperature should be kept lower than the maximum rating of 125°C, so care
should be taken in the circuit layout to ensure good heat sinking. Sufficient cooling should be provided to ensure
reliable operation.
To estimate the junction temperature, approximate the power dissipation within the TPS81256 by applying the
typical efficiency stated in this datasheet to the desired output power; or, by taking a power measurement if you
have an actual TPS81256 device or a TPS81256EVM evaluation module. Then calculate the internal
temperature rise of the TPS81256 above the surface of the printed circuit board by multiplying the TPS81256
power dissipation by the thermal resistance.
The thermal resistance numbers listed in the Thermal Information table are based on modeling the MicroSiP
package mounted on a high-K test board specified per JEDEC standard. For increased accuracy and fidelity to
the actual application, it is recommended to run a thermal image analysis of the actual system. Figure 24 and
Figure 25 are thermal images of TI’s evaluation board with readings of the temperatures at specific locations on
the device.

Figure 24. VIN=3.6v, VOUT=5v, IOUT=300ma Figure 25. VIN=3.6v, VOUT=5v, IOUT=600ma
150mw Power Dissipation At Room Temperature 600mw Power Dissipation At Room Temperature

The TPS81256 is equipped with a thermal shutdown that will inhibit power switching at high junction
temperatures. The activation threshold of this function, however, is above 125°C to avoid interfering with normal
operation. Thus, it follows that prolonged or repetitive operation under a condition in which the thermal shutdown
activates necessarily means that the components internal to the MicroSiP™ package are subjected to high
temperatures for prolonged or repetitive intervals, which may damage or impair the reliability of the device.
MLCC capacitor reliability/lifetime is dependant on temperature and applied voltage conditions. At higher
temperatures, MLCC capacitors are subject to stronger stress. On the basis of frequently evaluated failure rates
determined at standardized test conditions, the reliability of all MLCC capacitors can be calculated for their actual
operating temperature and voltage.

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Thermal and Reliability Information (continued)

10000
VBias=5V
VBias=4.35V
VBias=3.6V
1000 VBias=3V

Time (Thousand Hours)

100

10

0.1

0.01
20 40 60 80 100 120 140
Capacitor Case Temperature ( °C)
G000

Figure 26. Capacitor Lifetime vs Capacitor Case Temperature

Failures caused by systematic degradation can be described by the Arrhenius model. The most critical
parameter (IR) is the Insulation Resistance (i.e. leakage current). The drop of IR below a lower limit (e.g. 1 MΩ)
is used as the failure criterion, see Figure 26. It should be noted that the wear-out mechanisms occurring in the
MLCC capacitors are not reversible but cumulative over time.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
MicroSiP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
MicroSiP DC/DC Module Package Dimensions
The TPS81256 device is available in a 9-bump ball grid array (BGA) package. The package dimensions are:
• D = 2.925 ±0.05 mm
• E = 2.575 ±0.05 mm
TOP VIEW BOTTOM VIEW

YML
LSB
CC
A1 B1 C1

D A2 B2 C2

A3 B3 C3

Code:
• CC — Package marking Chip Code (see Package Option Addendum for more details)
• YML — Y: Year, M: Month, L: Lot trace code
• LSB — L: Lot trace code, S: Site code, B: Board locator

Figure 27. µSIP 9-Pin Dimensions and Markings

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PACKAGE OUTLINE
SIP0009A SCALE 5.500
MicroSiP TM - 1 mm max height
MICRO SYSTEM IN PACKAGE

2.975 A
B
2.875

PIN A1
INDEX AREA

2.625
2.525

PICK AREA
NOTE 3

1 MAX
C

SEATING PLANE

0.10 0.05 C
0.06

2 TYP

1 TYP

1
TYP

B 2
TYP
0.35
9X
0.25
0.015 C A B
A

1 2 3

4218355/A 06/2014
MicroSiP is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. For pick and place nozzle recommendation, see product datasheet.
4. Location, size and quantity of each component are for reference only and may vary.

www.ti.com

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EXAMPLE BOARD LAYOUT

SIP0009A MicroSiPTM - 1 mm max height
MICRO SYSTEM IN PACKAGE

SYMM

9X ( 0.3)
1 2 3 SEE DETAILS

SYMM
B

(1)
TYP

(1) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.05 MAX ( 0.3) 0.05 MIN

METAL ( 0.3)
SOLDER MASK
OPENING

SOLDER MASK
OPENING METAL UNDER MASK

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4218355/A 06/2014

NOTES: (continued)

5. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

www.ti.com
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EXAMPLE STENCIL DESIGN

SIP0009A MicroSiP TM - 1 mm max height
MICRO SYSTEM IN PACKAGE

SYMM
( 0.34) TYP
1 3 SEE DETAIL
2

B SYMM

(1)
TYP

(1) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:20X

METAL ( 0.34)
UNDER PASTE

SOLDER PASTE DETAIL

TYPICAL

4218355/A 06/2014

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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 PACKAGE OPTION ADDENDUM

www.ti.com 17-Feb-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS81256SIPR ACTIVE uSiP SIP 9 3000 RoHS (In OSP Level-2-260C-1 YEAR -40 to 85 TT
Work) & Green
(In Work)
TPS81256SIPT ACTIVE uSiP SIP 9 250 RoHS (In OSP Level-2-260C-1 YEAR -40 to 85 TT
Work) & Green
(In Work)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Feb-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS81256SIPR uSiP SIP 9 3000 178.0 9.0 2.83 3.18 1.2 4.0 8.0 Q2
TPS81256SIPT uSiP SIP 9 250 178.0 9.0 2.83 3.18 1.2 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS81256SIPR uSiP SIP 9 3000 223.0 194.0 35.0
TPS81256SIPT uSiP SIP 9 250 223.0 194.0 35.0

Pack Materials-Page 2
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