Design for Test

Scan Test
Smith Text: Chapter 14.6
Mentor Graphics Documents:
“Scan and ATPG Process Guide”
“DFTAdvisor Reference Manual”
“Tessent Common Resources Manual for ATPG Products
Top-down test design flow

Source: Scan and APTG Process Guide

Sequential circuit testing problem
 Access limited to PIs/POs
 Internal state is changed PIs POs
Combinational
indirectly Logic
 For N PIs and K state
variables, must test 2N+K
combinations
 Some states difficult to
reach, so even more test Flip
State flops
vectors are needed

Clock
Design for Test (DFT)

Flip flop states difficult to set from PIs A & B

DFT: Scan Design

• Flip flops replaced with “scan” flip flops

• Scan flip flops form a shift register in “scan mode”
• Flip flop states set via “scan input” sc_in
• Flip flop states examined via “scan output” sc_out
 Scan-based test procedure
 Combinational logic inputs = {X1…Xk,Q1…Qn}
 X1…Xk = primary inputs (PI’s)
 Q1…Qn = flop-flop outputs

 Combinational logic outputs = {Z1…Zm, D1…Dn}

 Z1…Zm= primary outputs (PO’s)
 D1…Dn= flop-flop inputs

 Test procedure:
1. Apply pattern to combinational logic inputs:
a) Set scan enable sc_en = 1 and shift pattern into Q1…Qn via scan input sc_in
b) Apply a pattern to PI’s X1…Xk
2. Check combinational logic outputs:
a) Check PO’s Z1…Zm
b) Set sc_en = 0 and clock the circuit to capture D1…Dn in the flip-flops
c) Set sc_en = 1 and shift out Q1…Qn via scan output sc_out for verification
 Scan type: mux_scan
Standard D flip flop with a mux to select system data vs scan data

BICMOS8HP library “mux_scan” components:

SDFF_x, SDFFR_x, SDFFS_r, SDFFSR_x, SLATSRLV_x
Replacements for:
DFF_x, DFFR_x, DFFS_x, DFFSR_x, LATSRLV_x
Scan type: clocked_scan

Separate clocks to load system data and scan data

BICMOS8HP & ADK libraries: no “clocked_scan” components

 Scan type: LSSD
(Level-sensitive scan design – IBM)
Three clocks:
1. sys_clock loads system data into the master latch (normal mode)
2. Aclk loads scan data into the master latch
3. Bclk captures master data in the slave latch to drive scan output

BICMOS8HP library: no “lssd” components

ADK library “lssd” components:
lssd_latch/latchsr/latchr/latchs/latchs_ni/latchsr_ni
 Full vs. partial scan

Full Scan:
All FFs in scan chains.

Partial Scan:
Some FFs not in scan chains.
Increase testability,
without affecting critical
timing/areas
Scan chain groups
Group 1

Group 2

• Scan chains operate in parallel from separate scan inputs

• Reduces number of clock cycles to load/unload the chain
• Control from one procedure file
• Can use separate clocks or a common clock
DFT test point insertion
Choosing a DFT solution
DFTadvisor/FastScan Design Flow

Source: ATPG Manual

DFT test flow and commands

DFTAdvisor
Commands
(insert test logic)

FastScan
Commands
(generate patterns)
-verilog

Source: DFTadvisor Reference

 bicmos8hp.atpg
(adk.atpg)

Basic scan
insertion flow
 DFTAdvisor supported test structures

Sequential ATPG-based: choose cells with a sequential ATPG algorithm

SCOAP: Sandia Controllability Observability Analysis Program (#’s for each ff)
Automatic: combine scan selection methods using several techniques
Structure-based: look at loop breaking, limiting sequential depth, etc.
Sequential Transparent: cut all sequential loops and evaluate
Clocked Sequential: cut sequential loops and limit sequential depth
 Example DFTadvisor session
 Invoke:
 dftadvisor modulo6_1.v –lib bicmos8hp.atpg
 Implement scan with defaults (full scan, mux-DFF elements):
 set system mode setup (analyze the circuit)
 analyze control signals (find clocks, resets, etc.)
 add clocks 0 CLK (identify CLK off state)
 add clocks 1 CLEARbar (likewise async set/reset)
 set scan type mux_scan (use scan ffs with mux inputs)
 set system mode dft (design for testability)
 run (identify where to insert scan/test pts)
 insert test logic –scan on (insert scan/tp’s into netlist)
 write netlist mod6_scan.v -replace (Verilog netlist of modified ckt)
 write atpg setup mod6_scan -replace (dofile & test procedure for FastScan)
Options:
 insert test logic –scan on –number 3 (create 3 scan chains)
 insert test logic –scan on –max_length 20 (no scan chain > 20 ffs)
DFT options
 set scan type mux_scan
 Others: lssd, clocked_scan
 Find indicated scan flip flop type in the ATPG library
 setup scan identification “type”, where “type” =
 full_scan (default)
 sequential atpg –percent 50
 clock_sequential [-depth integer]
 etc.
 insert test logic
 -scan on/off (insert scan elements; default=on)
 -test_point on/off (insert test points; default=on)
 - maxlength n (max scan chain length = n)
 - number n (divide ffs into n scan chains)
Modulo-6 counter: Synthesized by Synopsys DC
Modulo-6 counter: Converted to full-scan (BICMOS8HP)
count4 – without scan design (TSMC 180nm)
Binary
counter
(4-bit)

Synthesized by
Leonardo

DFTAdvisor
Changed to
Scan Design
count4 – scan inserted by DFTadvisor
 FastScan ATPG session for a circuit
containing scan chains
 Invoke:
fastscan count4_scan.v –lib $ADK/technology/adk.atpg

 Generate test pattern file:

 dofile count4_scan.dofile (defines scan path & procedure)
 set system mode atpg
 create patterns (generate the test patterns)
 save patterns count4_patterns.v –verilog (write patterns & test bench)
 write faults count4_faults.txt (write fault information to file)
 write procfile count4.proc (write test procedure & timing data)
 count4_scan.dofile
// Generated by DFTAdvisor at Wed Nov 30 17:01:33 2014
//
// define group “grp1” of scan chains and their test procedure
add scan groups grp1 count4_scan.do.testproc
// define sc_in and sc_out of scan “chain1” in group “grp1”
add scan chains chain1 grp1 scan_in1 output[3]
// define “clocks” controlling the scan chain
add clocks 0 clear
add clocks 0 clock
Notes:
• Can have multiple scan chains in a group – with a common test procedure
• Can have multiple groups – each with its own test procedure
 Test file: scan chain definition and
load/unload procedures
scan_group "grp1" =
scan_chain "chain1" =
scan_in = "/scan_in1";
scan_out = "/output[3]"; # shifts
length = 4;
end;
procedure shift "grp1_load_shift" = procedure load "grp1_load" =
force_sci "chain1" 0; force "/clear" 0 0;
force "/clock" 1 20; (each shift) force "/clock" 0 0;
force "/clock" 0 30; force "/scan_en" 1 0;
period 40; apply "grp1_load_shift" 4 40;
end; end;
procedure shift "grp1_unload_shift" = procedure unload "grp1_unload" =
measure_sco "chain1" 10; force "/clear" 0 0;
force "/clock" 1 20; force "/clock" 0 0;
force "/clock" 0 30; (each shift) force "/scan_en" 1 0;
period 40; apply "grp1_unload_shift" 4 40;
end; end;
end;
 Test file: scan chain test
// send one pattern through the scan chain
CHAIN_TEST =
pattern = 0; (pattern #)
apply "grp1_load" 0 = (use grp1_load proc.)
chain "chain1" = "0011"; (pattern to scan in)
end;
apply "grp1_unload" 1 = (use grp1_unload proc.)
chain "chain1" = "1100"; (expected pattern scanned out)
end;
end;
 Test file: sample test pattern
// one of 14 patterns for the counter circuit
pattern = 0; (pattern #)
apply "grp1_load" 0 = (load scan chain)
chain "chain1" = "1000"; (scan-in pattern)
end;
force "PI" "00110" 1; (apply PI pattern)
measure "PO" "0010" 2; (expected POs)
pulse "/clock" 3; (one normal op. cycle)
apply "grp1_unload" 4 = (read scan chain)
chain "chain1" = "0110"; (expected pattern)
end;
 Alternate format (4)
set time scale 1.000000 ns ;
(3)
timeplate gen_tp1 =
(1) (2) clock
force_pi 0 ; (1)
0 10 20 30 40
measure_po 10 ; (2)
pulse clock 20 10; (3) Timing of op’s within each cycle
period 40 ; (4)
end; procedure load_unload =
procedure shift = scan_group grp1 ;
scan_group grp1 ; timeplate gen_tp1 ;
timeplate gen_tp1 ; cycle =
cycle = force clear 0 ;
Initial
force_sci ; Each
force clock 0 ; values
measure_sco ; shift force scan_en 1 ;
pulse clock ; cycle end ;
end; apply shift 4; Execute shift
proc. 4 times
end; end;
DFTAdvisor example (Chao Han)
//dofile for dftadvisor
analyze control signals -auto_fix
set scan type mux_scan
set system mode dft
setup scan identification full_scan
run
//specify # scan chains to create
insert test logic -scan on -number 3
//alternative: specify maximum scan chain length
//insert test logic -scan on -max_length 30
write netlist s1423_scan.v -verilog -replace
//write dofile and procedure file for fastscan
write atpg setup s1423_scan -procfile -replace
exit