SNS COLLEGE OF TECHNOLOGY

Coimbatore-35
An Autonomous Institution

Accredited by NBA – AICTE and Accredited by NAAC – UGC with ‘A+’ Grade
Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

16EC303–VLSI DESIGN
III YEAR/ V SEMESTER

UNIT 4 –VLSI TESTING

TOPIC 6 –BIST
 OUTLINE

• INTRODUCTION
• BASIC CONCEPT OF TESTING
• PRINCIPLE OF TESTING
• DIFFICULTIES IN TESTING
• HOW TO DO TESTING
• CIRCUIT MODELING
• AUTOMATIC TEST PATTERN GENERATION (ATPG)
• DIFFICULTIES IN TEST GENERATION-2 TYPES
• TESTABLE DESIGN
• ACTIVITY
• BUILT-IN-SELF TEST (BIST)
• RANDOM NUMBER GENERATOR (RNG)
• SIGNATURE ANALYZER (SA)
• MEMORY BIST ARCHITECTURE
• CPU TEST CONTROL ARCHITECTURE
• TESTING METHODS
• ASSESSMENT
• SUMMARY & THANK YOU
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 BASIC CONCEPT OF TESTING
Testing: To tell whether a circuit is good or bad
VDD

0 0
0
0 0 0/1

Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault

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 PRINCIPLE OF TESTING
-1011 1-001
Circuit
11-00 0011-
under
-0-1- -1101
Test
01--0 1001-
(CUT)
0-101 01-11
Stored Comparator
Correct
Response
Test Result

• Testing typically consists of

– Applying set of test stimuli (input patterns, test vectors) to inputs of circuit
under test (CUT), and
– Analyzing output responses
• The quality of the tested circuits will depend upon the thoroughness of the test
vectors

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 DIFFICULTIES IN TESTING
• Fault may occur anytime
- Design
- Process
- Package
- Field

• Fault may occur at any place

Vss

• VLSI circuit are large

- Most problems encountered in testing are NP-complete
• I/O access is limited

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 HOW TO DO TESTING

From designer’s point of view:

• Circuit modeling
• Fault modeling Modeling

• Logic simulation
• Fault simulation
• Test generation ATPG

• Design for test

• Built-in self test Testable design
• Synthesis for testability

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 CIRCUIT MODELING

• Functional model--- logic function

- f(x1,x2,...)=...
- Truth table
• Behavioral model--- functional + timing
- f(x1,x2,...)=... , Delay = 10

• Structural model--- collection of interconnected components or

elements

A E
B 1
0
G
1
C 0
D F
0

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 AUTOMATIC TEST PATTERN GENERATION

ATPG: Given a circuit, identify a set of test vectors to detect all faults under consideration.

Input circuit

Form fault list

No
More faults? Exit

Yes
Select a fault
Fault
dropping
Test generation

Fault simulation

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 TEST GENERATION

• Given a fault, identify a test to detect this fault

Example:

A
1
0 1/0 To detect D s-a-0, D must be set to 1.
1
D
1/0
Thus A=B=1.
B F
1 To propagate fault effect to the primary
C E
output
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0

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 DIFFICULTIES IN TEST GENERATION

1. Reconvergent fan-out

0/1 Cannot detect the fault

A
0 s-a-1
D 1
B 1 0 F
0/1
1 1
C
Fault detected
0E

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 DIFFICULTIES IN TEST GENERATION (CONT.)

2. Sequential test generation

PIs Combinati POs

onal part

Y J
K
Y CK clk

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 TESTABLE DESIGN

• Design for testability (DFT)

• ad hoc techniques
• Scan design
• Boundary Scan

• Built-In Self Test (BIST)

• Random number generator (RNG)
• Signature Analyzer (SA)

• Synthesis for Testability

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 CLASS ROOM ACTIVITY
Tell about yourself-any four students
To analyze how confident you are and how you present yourself.
The best way to answer this common interview question is to tell the hiring manager about
your education and family background.
However, this should not look like your life’s story and you should quickly concentrate
on sharing a bit about your strengths that build the platform for further discussion about your suitability
for the job opening.
Bonus Tips:
## Don’t narrate what is already mentioned in your CV
## Focus more on talking about your achievements and learning
## Keep it short

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 BUILT-IN-SELF TEST (BIST)

Places the job of device testing inside the device itself

Generates its own stimulus and analyzes its own response

from system circuit to system

mux
under test

Response
generator

Analyzer
pattern
BIST good/fail
Controller

biston bistdone

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 BUILT-IN-SELF TEST (BIST) (CONT.)
• Two major tasks
- Test pattern generation
- Test result compaction
• Usually implemented by linear feedback shift register

F/F F/F F/F

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 RANDOM NUMBER GENERATOR (RNG)

0001 0110 1111

1000 1011 0111
0100 010 0011
F/F · F/F · F/F · F/F ·
0010 1 0001
1001 101 (repeat)
1100 0
1101
1110
1. Generate “pseudo” random patterns

2. Period is 2n - 1

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 SIGNATURE ANALYZER (SA)

Input sequence 10101111 (8 bits) + 1 2 + 3 4 + 5 Z

G x   1  x 2  x 4  x5  x6  x7 P x   1  x 2  x 4  x 5
Time Input stream Register contents Output stream
0 10101111 00000 Initial state
1 1010111 10000
. . .
. . .
5 101 01111
6 10 00010 1
7 1 00001 01
8 00101 101

Remainder Quotient
R x   x 2  x 4 1 x2

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 SIGNATURE ANALYZER (SA) (CONT.)

• A LFSR performs polynomial division

P x : x5  x4  x2 1
 Q x : x2 1
x 7  x 6  x 4  x 2  x5  x 4  x 2  1
 x 7  x 6  x5  1

P x Q x  R x  x7  x6  x5  x4  x2 1  G x

• Probability of aliasing error = 1/2n (n: # of FFs)

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 MEMORY BIST ARCHITECTURE

After
Before
sys_di
data
di sys_addr
sys_wen
clk
data hold_l q
addr Memory Memory
Module rst_l Module
test_h
wen si so
se

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 MEMORY BIST ARCHITECTURE (CONT.)

Pattern Generator
sys_addr di

Algorithm-Based
data
sys_di addr Memory
Module
sys_wen rst_l wen

Compressor
clk q
hold_l compress_clk
h rst
test_h si so
se

BIST Circuitry

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 CPU TEST CONTROL ARCHITECTURE

Scan_i
Scan_o
Scan path
Scan_en

logic

rst_l
clk
BIST Memory
hold_l
control
test_h

MUX
bist_se
compressor bist_so TDO
bist
decoder
int_scan mbist

bist_si
scan
decoder
decoder
TDI

TCK IR
TAP Controller
TMS

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 TESTING METHODS

• A 32-bit adder --- ATPG

• A 32-bit counter --- Design for testability + ATPG

• A 32MB Cache memory --- BIST

• A 107-transistor CPU --- All test techniques

• An SOC

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 ASSESSMENT

1. How can you make test generation?

2. How can you generate random number?
3. Why we use Signature Analyser in BIST?
4. Match all correctly
A 32-bit adder --- BIST
A 32-bit counter --- All test techniques
A 32MB Cache memory --- ATPG
A 107-transistor CPU --- Design for testability + ATPG

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 SUMMARY & THANK YOU

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