Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Designing of Low-Power Full Adder by Submicron

Ultra Deep Technology
T Srujana Dr B Bharathi
Assistant Professor, Department of ECE Assistant Professor, Department of ECE
Sree Dattha Institute of Engineering and Science, Sree Dattha Institute of Engineering and Science,
Ibrahimpatnam, Ranga Reddy District, India Ibrahimpatnam, Ranga Reddy District, India

Abstract:- Power consumption has emerged as a main under different load conditions and balanced output to avoid
feature of consent in today’s widely used electronic glitches is also an important virtue. Several logic styles have
circuits. The consumption of data path is nearly 30% of been proposed in the literature [1-12] to design 1-bit full
the total power of high performance microprocessor. The adder cell. Each design has its own merits and demerits in
key components used in the data paths are Adders and terms of output signal swings, driving capabilities, speed,
hence, careful design and analysis is required for these power, switching activity, noise immunity and so on.
units to obtain optimum performance. In this paper we Generally, the focus in deep submicron technology is to
presented a design for low power, energy efficient full reduce the static power by replacing nMOS with pMOS
adder circuit by ultra-deep sub- micron technology. The transistors [12] or by stacking effect or by reducing the
main focus in low power design is targeted to reduce the transistor count [11]. In designing so, the designers often
static power while trading other vital requirements such trade for other vital requirements such as area, driving
as driving capability, delay, total power, power delay capability, delay, total power and noise immunity. The
product and noise. Based on the fact that transmission performance of such a full adder cell as a single unit is good
logic has good driving capability and full signal swing but when these cells are used as a building block of complex
than pass transistor logic, a new full adder cell is circuits, the performance degrades drastically.
proposed to reduce delay and power-delay product
(PDP).The simulations have been carried out with
TANNER EDA simulation tool using PTM 65nm
technology files. The Simulation has been carried out for
different supply voltages, loading conditions. The MEMORY 15% CONTROL 10%
performance of the proposed circuit was compared with CLOCK 45%
respect to the existing ones.
DATAPATH30%
Keywords:- Novel, Low-Power, Energy-Efficient, Full Adder,
ultra deep-Submicron.

I. INTRODUCTION
Fig 1:
The demand and popularity of portable electronics is
driving designers to strive for smaller silicon area, higher In this paper, we presented an optimized design for a
speeds, longer battery life, and more reliability. Power is one full adder cell craved for low power, low energy, reliable
of the premium resources a designer tries to save when operation at low supply voltage, avoiding degradation in the
designing a system. Full adders are fundamental units in output voltage, good driving capability under different
various circuits, especially in circuits used for performing loading conditions. The rest of the paper is organized as
arithmetic operations such as compressors, comparators, follows. In section II, a survey of contemporary literature on
parity checkers, and so on [1]. Full adders are often used in full adders designs is presented. In section III, general
the critical paths of complex arithmetic circuits for overview of full adder with its sub modules is presented. In
multiplication and division. These in turn form the core of section IV, the circuit for module II is proposed and
any system and thereby influence the overall performance of combination of module II and III is presented. Using the
the entire system. Enhancing the performance of the full proposed combination in Section IV, we build a new full
adder can significantly affect the system performance. Figure adder cell in Section V. Simulation results are presented in
1 shows the power consumption breakdown in a modern day Section VI. Section VII concludes the paper.
high performance microprocessor [2]. The data path
consumes roughly 30% of the total power of the system. II. LITERATURE REVIEW
Adders are an extensively used component in data paths and,
therefore, careful design and analysis is required for these A survey of contemporary literature reveals a wide
units to obtain optimum performance. At the circuit level, an spectrum of adder designs over the past few decades. Several
optimized design is desired to avoid any degradation in the logic styles have been used in the past to design full adder
output voltage, consume less power, have less delay in cells. Each design style has its own merits and demerits.
critical path, and be reliable even at low supply voltage as we Classical designs of full adders normally use only one logic
scale towards deep sub micrometer. Good driving capability style for the whole full-adder design. One example of such

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Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
design is the standard static CMOS full adder [3]. This full performance as a single unit or in small chains is good but
adder is based on regular CMOS structure with conventional when large adders are built by cascading these 1-b full-adder
pull-up and pull-down transistors providing full-swing output cells, the performance degrades drastically.
and good driving capabilities. The main drawback of static
CMOS circuits is the existence of the pMOS block, because III. FULL ADDER COMPONENTS
of its low mobility compared to the nMOS devices.
Therefore, the pMOS devices need to be sized up to attain the A full adder can be broken down into three modules by
desired performance. The input capacitance of a static CMOS extracting the logical expression for the outputs SUM and
gate is large because each input is connected to the gate of at Cout using the binary inputs A, B and Cin [1-12] as shown in
least a pMOS and a nMOS device This is another reason for figure 2. Module I essentially perform the XOR(H) and
speed degradation of static CMOS gates. Another XNOR(~H) functions in terms of the inputs A and B. In [6],
conventional adder is the complementary pass-transistor logic the circuit for module I uses ten transistors and performs well
(CPL) [3]. It provides high-speed, full-swing operation and at low supply voltages. We consider this circuit for module I
good driving capability due to the output static inverters and in our design. Module II and III generates SUM, Cout
the fast differential stage of cross-coupled pMOS transistors. respectively using three signals Cin, H and ~H as inputs.
But due to the presence of a lot of internal nodes and static
inverters, there is large power dissipation. The layout of a IV. PROPOSED CIRCUIT FOR MODULE II
CPL cell is also not as straightforward as a static CMOS cell
due to its irregular transistor arrangement. The dynamic The expression for output of module II can be
CMOS logic style provides a high speed of operation because expressed as SUM = Cin·H+ ~Cin · ~H. The proposed circuit
the logic is constructed with only high mobility nMOS for module II is shown in Figure 2(a). A transmission gate
transistors. Also, due to the absence of the pMOS transistors, followed by a static inverter at the output is used to
the input capacitance is also low, thus enhancing the speed of implement Cin·H. A transmission gate preceded and
operation. However, it has several inherent problems such as succeeded by static inverter implements ~Cin· ~H. Only one
charge sharing and high clock load. It has higher switching among the two transmission gates is ON and the other is OFF
activity and lower noise immunity. It consumes a large at any time. The inverter (enclosed in circle in Figure 2) can
portion of the power in driving the clock lines. Moreover, be shared between proposed module II and module III in
dynamic logic style is more susceptible to leakage. Due to [10], as shown in Figure 2(b).
these reasons, we do not include dynamic logic style in our
discussions in this paper.

Some other full-adder designs include transmission-

function full adder (TFA) [4] and transmission-gate full adder
(TGA) [5].These designs are based on transmission-function
theory and transmission gates, respectively. These adders are
inherently low power consuming. These logic styles are good
for designing XOR or XNOR gates. The main disadvantage
of these logic styles is that they lack driving capability. This
is attributed to the fact that the inputs are coupled to the
outputs. When TGA or TFA are cascaded, their performance
degrades significantly.
Fig 2:- (a) Proposed module II (b) Combination of module
The remaining adder designs use more than one logic
II and III with shared inverter
style for their implementation. We call this the hybrid-CMOS
logic design style. Examples of adders built with this design
style are DB cell [6], NEW14-T adder [7], and hybrid pass V. PROPOSED FULL ADDER CELL
logic with static CMOS output drive full adder [8] (we will
In this section, we will present the new full adder
use HPSC as an abbreviation) and new-HPSC [9] adder.
These designs exploit the features of different logic styles to design based on the circuits discussed in Section II and III .In
improve upon the performance of the designs using single our proposed circuit, a single static inverter is shared to drive
logic style. All hybrid designs use the best available modules the transmission gates of both the modules II and III. At any
implemented using different logic styles or enhance the point of time, only one among the two transmission gates
driven by the inverter common to modules II and III are ON
available modules in an attempt to build a low power full-
and the other is OFF. The complement of Cin is propagated
adder cell. Generally, the main focus in such attempts is to
reduce the numbers of transistors in the adder cell and, in module III when H is at logic ‘1’ and ~H is at logic ‘0’. In
consequently, reduce the number of power dissipating nodes. the other case, when H is at logic ‘0’ and ~H is at logic ‘1’,
the complement of Cin is propagated in module II. The
This is achieved by utilizing intrinsically low power
additional inverter for module II reduces the loading effect on
consuming logic styles like TFA or TGA or simply passes
H and ~H signals and speeds up the circuit in module II to
transistors. In doing so, the designers often trade off other
vital requirements such as driving capability, noise immunity, generate the SUM output.
and layout complexity. Most of these adders lack driving
capabilities as the inputs are coupled to the outputs. Their

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Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165

Fig 3:-t Proposed Full Adder Fig 5:

VI. SIMULATION RESULTS Table I and Table II shows the comparison of full
adders at different supply voltages and for different values of
All the circuits are simulated in TANNER EDA using load capacitance CL. The proposed adder full adder showed a
PTM [13] 65nm technology model files. The simulation test good improvement in terms of power and delay when
bench along with transistor sizes of each buffer is shown in compared to adder in [9] and [10] at the cost of increase in
Figure 4. The performance of the circuit is evaluated in terms static power
of the worst-case delay, power consumption and PDP for
supply voltages 1.1V and 0.9V at 250 MHz frequency. A CL=1.5fF Adder in [9] Adder in [10] Proposed
change in the input may or may not lead to change at the Adder
output. As a result, some internal node may be switching Freq=250Hz
even if there is no switching at the output, this leads to some 1.1V 0.9V 1.1V 0.9V 1.1V 0.9V
power consumption. All the possible input combinations are
taken in to account for an accurate result. Power (µw) 4.30 2.72 5.081 3.1073 3.961 2.149

Delay (pS) 303.1 567.37 420.19 1254.8 230.1 280.3

PDP (aJ) 1304 1543.5 2135 3899 911 602

Table 1.Comparison of Full adders fort
different supply voltages

Vdd=1.1V Adder in [9] Adder in [10] Proposed

F=250MHz Adder
Fig 4:- 2.5fF 3.5 fF 2.5fF 3.5fF 2.5fF 3.5f
F
Figure 5 shows input stimulus for a full-adder cell. The Power (µw) 4.674 5.044 5.479 5.8587 4.139 4.31
first two are outputs and the remaining three are inputs. 2
Frequency of the inputs is 250 MHz with a supply voltage of Delay (pS) 320.2 336.5 438.6 453.48 240.4 260.
1.1 V and output load CL=2.5fF.The value of worst case 7
delay and average power dissipated is evaluated under PDP (aJ) 1496 1697 2403 2657 995 1124
different supply voltages and different load conditions. The
PDP is a quantitative measure of the efficiency of the tradeoff Table 2.Comparison oft Full adders fort
between power dissipation and speed, and is particularly different values oft CL
important when low-power operation is needed. The values
of PDP is evaluated under different supply voltages and We embedded our full adder cell in carry ripple
different output loads and the proposed adder showed a huge (RCA) 4-bit full adder circuit to evaluate it in a realistic
improvement as suggested by the simulation results. operating conditions. The 4-bit full adder test circuit is shown
in Figure 6.

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Volume 3, Issue 6, June – 2018 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
and loading conditions, making it suitable building block for
complex circuits to be used in a dynamic voltage and
frequency scaling (DVFS) scenario.

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