Low Power Shift and Add Multiplier Design: June 2010
Low Power Shift and Add Multiplier Design: June 2010
Low Power Shift and Add Multiplier Design: June 2010
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ABSTRACT
Today every circuit has to face the power consumption issue for both portable device aiming at large
battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It
is generally accepted that during logic synthesis power tracks well with area. This means that a larger
design will generally consume more power. The multiplier is an important kernel of digital signal
processors. Because of the circuit complexity, the power consumption and area are the two important
design considerations of the multiplier. In this paper a low power low area architecture for the shift and
add multiplier is proposed. For getting the low power low area architecture, the modifications made to
the conventional architecture consist of the reduction in switching activities of the major blocks of the
multiplier, which includes the reduction in switching activity of the adder and counter. This architecture
avoids the shifting of the multiplier register. The simulation result for 8 bit multipliers shows that the
proposed low power architecture lowers the total power consumption by 35.25% and area by 52.72 %
when compared to the conventional architecture. Also the reduction in power consumption increases with
the increase in bit width.
KEYWORDS
Low power multiplier, low power ring counter, sources of switching activities
1. INTRODUCTION
The power consumption in digital CMOS circuit can be described by
Pavg=Pdynamic+Pshortcircuit+Pleakage+Pstatic (1)
The dynamic power dissipation is caused by charging and discharging of capacitances in the
circuit. The short circuit power consumption is caused by the current flow through the direct
path existing between the power supply and the ground during the transition phase. The n-MOS
and p-MOS transistors used in a CMOS logic circuit commonly have non zero reverse leakage
and sub threshold current. The computation of a multiplier manipulates two input data to
generate many partial products for subsequent addition operations, which in the CMOS circuit
design require many switching activities. The switching activities within the functional unit of a
multiplier accounts for the majority of the power dissipation of a multiplier, as given in the
following equation
Pswitching = C Vdd2 fclk (2)
Where is the switching activity parameter, C is the loading capacitance, Vdd is the operating
voltage and fclk is the operating frequency.
10.5121/ijcsit.2010.2302 12
International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
Figure 1 Architecture of conventional shift and add multiplier with major source of switching
activity
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
partial product is required to be shifted in every cycle. The counter is for checking whether the
required number of operations has been performed. The major sources of switching activities
are summarized as below
• Shifting of the ‘B’ register
• Activity in the counter
• Activity in the adder
• Switching between ‘0’ and ‘A’ in the multiplexer
• Activity in the multiplexer select
• Shifting of the partial product register
By eliminating or reducing the switching activity described above, low power architecture can
be derived.
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
Figure 8. Clock gating logic with flip flop’s input and output
The clock gating logic in the Figure 8. OR’s the value of flip flop’s input and output on
Positive clock edges stores the result in latch. The output of the latch determines whether or
not to gate the clock signal .This clock gator is positive edge triggered. If we want to avoid
all the unnecessary transitions raised by the clock signal we should provide each flip-flop with
the clock gating circuitry of above figure. 8 ,but this solution ends up with a large area overhead
plus due to transitions in clock gator themselves the resulting ring counter will not have fewer
switching activity. A better solution is used in the low power multiplier architecture.
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
One of the important properties of the ring counter is that its output is one hot encoded. This
property of the ring counter makes its output wide especially as the counter size increases. To
reduce the switching activity of the counter the counter is partitioned in to a number of blocks
which are clock gated with a special clock gating structure whose power and area overheads are
independent of the block size, controlling with the low power ring counter helps to get a low
power low area architecture,thus avoids the trade off between power and area([6],[9],[5]). The
clock gating structure is shown below Figure10
Figure 9. Low power architecture for ring counter with block of size 4
.
Figure 10. Clock gating structure for the low power ring counter
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
Figure 12. Simulation results for 8 bit multiplier using proposed architecture
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
800 662
600
Area(slices)
400 313
Power(mW)
200 151.11
52.07 97.85
48.812 Delay(ns)
0
Conventional Proposed
Figure 15. Power Area and Delay comparison for conventional and Proposed 8 bit multiplier
40
35.25
30
10 Power reduction( %)
8
4
0
Conventional proposed
Figure 16. Relationship between Power reduction and Bit size of Multiplier
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
TABLE 3
Synthesis report for two multipliers
Conventional
Multiplier proposed
shift and add
Type architecture
multiplier
Vendor Xilinx Xilinx
Device
and Spartan 2 Spartan 2
Family
Estimated
662 slices 313 slices
area
Power
151.11mW 97.85mW
dissipation
TABLE 4
Increase in power reduction with bit width
Reduction in power
Bit width
consumption
4 20.51%
8 35.25%
6. CONCLUSION
The proposed architecture lowers the power dissipation and area when compared to a
conventional shift and add multiplier shown in Figure 15 . A multiplexer with one hot encoded
bus selector is used for avoiding the switching activity due to the shifting of the multiplier
register. Feeder and bypass registers are used for avoiding the unnecessary additions. The
proposed architecture makes use of bit width control logic and a low power ring counter .The
design can be verified using Modelsim 6.5 with VHDL code and power consumption is analyzed
using Xilinx software. From Table 3 and Figure 15 , proposed architecture can attain 35.25%
power reduction and 52.75% area saving when compared to the conventional shift and add
multipliers. Also from Table 4 and Figure 16 reduction of power consumption in multipliers
can be increases with the increase in bit width of operands, whereas in design [5] reduction in
power consumption decreases with the increase in bit width.
REFERENCES
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Circuits, Vol.27, no.4, pp 473-484, Apr 1992
[2] N.Y.Shen and O.T.C.Chen."Low power multipliers by minimizing switching activities of partial
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designing low power multipliers" IEEE Trans. Very Large Scale Integer .(VLSI)Syst. , Vol .11,
No-3, pp418-433, June 2003
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International Journal of Computer Science and Information Technology, Volume 2, Number 3, June 2010
[4] B.Parhami Computer arithmetic algorithms and Hardware designs 1 st ed.Oxford U.K. Oxford
Univ, Press 2000.
[5] K.H.Chen and Y.S.Chu , "A low power multiplier with spurious power suppression technique" ,
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[8] Ercegovac M.D. and Huang Z. (March 2006) “High performance low power left to right array
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