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Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module
based on PTL and GDI Logic

Article in International Journal of Computer Applications · November 2013

DOI: 10.5120/14150-2316

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Area Efficient 1-Bit Comparator Design by using

Hybridized Full Adder Module based on PTL
and GDI Logic
Anjali Sharma Richa Singh Pankaj Kajla
Assistant Professor Assistant Professor Assistant Professor
Department of ECE Department of ECE Department of ECE
APG Shimla University Virendra Swarup Institution APG Shimla University

ABSTRACT concern in CMOS Comparator design which often conflict

In this paper an area efficient 17T 1-bit hybrid comparator with the design methodology and act as constrain on the
design has been presented by hybridizing PTL and GDI design of comparator circuits. These performance criteria’s
techniques. The proposed 1-bit comparator design consist of 9 should be individually investigated, analyzed for the various
NMOS and 8 PMOS. A PTL and GDI full adder module has designs of the comparator by different logic styles.
been used which consume less area at 120 nm as compared Due to the growth of CMOS technology the VLSI industry
with the previous full adder designs. The proposed Hybrid 1- has been driven toward the design of system on chip. Demand
bit comparator design is based on this area efficient 9T full of the area efficient devices has been increased due to the
adder module. To improve area and power efficiency a explosive growth of VLSI industry. As Comparator is one of
cascade implementation of XOR module has been avoided in the basic circuitry used in arithmetic unit of various portable
the used full adder module. Full adder modules outputs have devices so area efficient comparator can help in the
been used for the generation of three different output of 1-bit fulfillment of these demands. Due to this area efficient design
comparator designs. The proposed 1-bit comparator has been of comparator has become essential for the researchers. Area
designed and simulated using DSCH 3.1 and Microwind 3.1 of the circuit mainly depends on three things: Number of
on 120nm. Also the simulation of layout and parametric transistors in the circuit, Feature size of the transistor and
analysis has been done for the proposed 1-bit comparator Wiring complexity. No of transistors is of course the primary
design. Power and current variation with respect to the supply concern in the area efficient design because it affects the
voltage has been performed on BSIM-4 and LEVEL-3 on complexity of any circuit.
120nm. Results show that area consumed by the proposed
hybrid adder is 329.3µm2 on 120nm technology. At 1.4V Power dissipation in any full adder circuit depends on two
input supply voltage the proposed 1-bit hybrid comparator components: One is static dissipation which occurs due to the
consume 0.367mW power at BSIM-4 and 0.411mW power at leakage current or other current drawn continuously from the
LEVEL-3 and 2.313mA current at BSIM-4 and 3.047mA power supply and second is dynamic dissipation which occurs
current at LEVEL-3 model due to switching of transient current, and charging and
discharging of load capacitances. The static power dissipation
Keywords is the product of the leakage current and supply voltage. The
BSIM, CMOS, Gate Diffusion Input, NMOS, PMOS, Pass total static power dissipation Ps is given by
transistor logic, VLSI
n
1. INTRODUCTION Ps   Leakage current × Supply voltage (1)
Comparator is a basic building block in the arithmetic unit of 1

digital signal processors and application specific integrated Where n= no of devices and the leakage current is described
circuits used in various digital electronic devices. In the world by the equation
of technology the demand of portable devices are increasing io  is (eqV / kT  1) (2)
day by day. Demand and popularity of these devices depends
on the small silicon area, higher speed, longer battery life and Where is is reverse saturation current, V is diode voltage, q is
reliability. The system performance can be affected by electronic charge, k is Boltzmann’s constant and T is
enhancing the performance of the comparator circuit used in temperature.
these systems. Power and area consumption is a key limitation
in many electronic devices such as mobile phone and portable The majority of the power dissipated in CMOS VLSI circuits
computing systems etc. So far several logic styles have been is due to dynamic power. Thus for performance estimation of
developed to improve area and power consumption [1]-[4]. comparator only dynamic power is of interest. Average
Several new logic styles have been developed that have better dissipated dynamic power is proportional to energy required
performance as compared to the traditional CMOS logic to charge and discharge the circuit capacitance and switching
styles. The performance estimation of full adder is based on frequency.
the design criteria for specific application. The main issues in 2
CLVDD
performance estimation are Area Consumption, Power Pd  (3)
dissipation, Propagation delay and Power –Delay Product. tp
Area, speed and power consumption are the main criteria of

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Total power dissipation is given by the sum of these three From the truth table it can be observed that
power dissipation i.e. static power dissipation, dynamic power
dissipation and short circuit dissipation. E  A B
Ptotal  PS  Pd  Psc (4)
L  AB
The average propagation delay of the inverter is given by  P G  AB
which is defined as the average time required for the input Therefore, we can construct the logic circuit of the single-bit
signal to propagate through the inverter. magnitude comparator as shown in Fig 2 where glowing LED
 PHL   PLH shows high output.
P  (5)
2
The propagation delay times  PLH and  PHL determine the
input-to-output signal delay during the high-to-low and low-
to-high transitions of the output respectively. Power delay
product is also defined as
PDP  2 Pavg  P (6)

Where the average switching is power dissipation at Fig. 2 Logic Diagram Of Single Bit Comparator
maximum operating frequency and  P is the average
propagation delay. The factor 2 in above equation accounts 3. COMPARATOR DESIGNS
for two transition of the output, from low to high and from In the recent past various approaches of CMOS Comparator
high to low. Putting equation (3) in equation (6) PDP can be design by using various different logic styles has presented
written as and unified into an integrated design methodology. Circuit
area, speed and power consumption are the main criteria of
PDP  2(Cload  VDD
2
 f max ) P concern in CMOS Comparator design which often conflict
(7) with the design methodology and act as a constrain on the
design of comparator circuits. These performance criteria’s
2. 1-BIT MAGNITUDE COMPARATOR are individually investigated, analyzed and their interaction to
Digital Comparator "also called Magnitude Comparator" is a develop both quantitative and qualitative understanding of the
combinational circuit that compares two inputs binary various designs have been presented in literature.
quantities (A and B) and generates outputs to indicate whether
the inputs are equal or which input is greater than the other,
therefore, the circuit has three outputs to indicate whether
A=B, A>B or A<B. At any given input quantities, only one
output should be equal to logic '1'.

Fig. 1 Block Diagram of n-Bit Magnitude Comparator

Fig. 1 shows a block diagram of the magnitude comparator.

The circuit, for comparing two n-Bit numbers, has 2n inputs Fig 3: 2-Bit Comparator using CMOS logic style [5]
& 22n entries in the truth table, for 2-Bit numbers, 4-inputs &
16-rows in the truth table, similarly, for 3-Bit numbers 6- Different 2 bit Comparator designs by using different logic
inputs & 64-rows in the truth table. styles and their comparison have been presented in [5]. A
CMOS and TG 2 bit comparator design provides full voltage
Table 1. Truth table of 1-bit Comparator swing between 0 and VDD. But disadvantage of these designs
is that they consume large power and area as compare to other
Inputs Outputs designs. Also 2 bit comparator design by using pseudo NMOS
logic style and by using pass transistor logic has been
B A G(A > B) E(A = B) L(A < B) presented which consumes less area as compare to the two
0 0 0 1 0 previous designs but does not provide full voltage swing at
the output. Pass transistor logic consume less power and area
0 1 1 0 0 as compared to other propose designs. But CMOS and TG
1 0 0 0 1 show full voltage swing at the output as compare to the Pass
transistor based comparator.
1 1 1 0 1 0
The truth table for the single bit comparator is shown in table
1.

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Fig 4: 2-Bit Comparator using Transmission Gate logic [5]

In recent years reversible logic has received great attention to

reduce the power dissipation. A Novel low power comparator Fig 6: 64-Bit CMOS Binary Comparator [9]
design using reversible logic has been presented in [6] which
have ability to reduce the power dissipation. The proposed A high speed 64 bit CMOS binary comparator has been
design full fills the requirement of less power consumption in proposed in [9] which have been implemented to improve the
various applications like ultra low power digital circuit and speed of the digital circuit. The proposed circuit shows better
quantum computers. results as compared to the other existing designs in terms of
speed. The proposed design maintains its superiority for high
temperature. But disadvantage of this circuit is that the speed
has been improved after sacrificing power consumption and
area. The proposed design can be implemented for high speed
circuits.

Fig 5: 2-Bit Comparator using Pass transistor logic style

[5]

In recent years reversible logic has received great attention to

reduce the power dissipation. A Novel low power comparator
design using reversible logic has been presented in [6]-[8] Fig 5: 8-Bit Comparator [10]
which have ability to reduce the power dissipation. The
proposed design full fills the requirement of less power A hybridized low power 8 bit magnitude comparator has been
consumption in various applications like ultra low power proposed in [10] by hybridizing PTL and CMOS logic. The
digital circuit and quantum computers. proposed design shows less power and area consumption as
compared to other designs at different voltages. This hybrid
comparator design shows less power consumption as
compared to PTL and CMOS based comparator design. The
proposed design also consumes less area as compared to other
designs.

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

4. FULL ADDER DESIGNS TG Full adder design by using 22 transistors has been shown
Full adder is a basic building block used in arithmetic unit of in Fig 7 [12]. As transmission gate based full adder designs
digital signal processors and ASIC’s used in various digital are low power designs and consume less transistors as
electronic devices. There are various possible designs of full compared to the complementary CMOS design. This paper
adder using different logic styles. Area consumption, speed presents an area and power efficient technique to design a full
and power consumption are the main criteria of concern in adder, using TG and multiplexer in order to reduce transistor
full adder design which often conflict with the design count. Most of the conventional CMOS adders have been
methodology and act as a constrain on the design of full adder designed using 28 transistors which are very high and cause
circuits. These performance criteria’s must be individually high power consumption. To overcome this existing problem,
investigated and analyzed for the efficient performance of the the TG full adder has been presented to improve the power
digital circuits. The simultaneous generation of the sum and and area simultaneously as compared to conventional CMOS.
carry output are required in 1 bit comparator in which
comparative outputs are obtained by using 1-bit full adder
design. Various full adder designs have been presented in
[11], [12], [11], [23]-[26].

Fig 8: PTL Full Adder Design By 2x1 Mux [13]

If a logic style shows good performance in terms of one

estimation criteria it can give degraded performance in other.
Fig 6: CMOS Full Adder Design By 2x1 Mux [11] The majority of the power dissipated in CMOS VLSI circuits
is by dynamic power dissipation which is the power
In Fig. 6 a 36T full adder design has been shown by using dissipated during charging or discharging of the load
complementary CMOS design. This design has been capacitance of a given circuit [13]-[15]. PTL based 10T full
implemented by using 12T complementary CMOS XOR and adder design by using 4T XOR and 2T Mux has been shown
12T 2x1 Mux design. In this design cascade operation of the in Fig. 8 which consists less transistors as compared to CMOS
XOR module has been done to implement the SUM output. and TG full adder designs. This design consumes less area as
Carry output has been generated by using 2x1 Mux for which compared to CMOS and TG design but can’t give full voltage
the XOR output act as a select line. This design give the full swing at the output.
voltage swing at the output by disadvantage is the large area
consumption.

Fig 9: GDI Full Adder Design By 2x1 Mux [18]

In [16]-[20] full adder function has been achieved by using

GDI technique shown in Fig.9. Circuit by using this technique
uses 10 transistors to generate balanced SUM and Carry
output. In this circuit simultaneously generation of XOR and
Fig 7: TG Full Adder Design by using 2xl MUX [12] XNOR output has been implemented which further acts as a
input for the SUM and CARRY Module. Sum and Carry
output has been obtained by using 2x1 MUX.

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Fig 12: Timing Simulation of Hybrid Full adder

The full adder module has been compared with other

Fig 10: Hybrid Full Adder Design By 2x1 Mux [12] discussed full adder in terms of area in microwind 3.1
designing tool. Microwind deals with both front end and back
In [12] a hybrid full adder has been implemented by using end designing of the VLSI circuits. In front end it has DSCH
only 9 transistors shown in Fig.10. This full adder design in which both transistor level and gate level designing can be
consists five transistors in module 1and module 2and 3 has done and also have ability to generate a verilog file which can
been implemented by using 2T GDI cell. Sum is obtained by be compiled by the microwind back end designing tool to get
using XOR-XNOR Module and 2x1 GDI Mux and an another power and area consumption. Full adder module is compared
2x1 Mux is used for carry generation. Output of XOR-XNOR with the other discussed full adder design in terms of area on
cell is used to drive the selection lines and control signal lines 120nm technologies.
of the multiplexer. XOR-XNOR module has been designed by
the PTL logic and consist only 5 transistors. So this design Table 2. Comparative Analysis of hybrid full adder
has been implemented by using only 9 transistors. Module in terms of area with other full adder design by
different logics on 120nm technology
5. PROPOSED COMPARATOR
SCHEMATIC Full adder CMOS TG PTL GDI Hybrid
The design of proposed comparator consist Full Adder as a
Modules
basic building block. To obtain the three comparative output
inverted input at the B input terminal is given to the full adder
design and C input is connected to the ground. Carry output
NMOS 18 11 5 5 5
directly act as A>B output of the one bit comparator. For the
generation of A=B and B>A different input combinations for
PMOS 18 11 5 5 4
AND gate has been used. For generation of B>A input
combination for the AND gate is B and A1 and for the
generation of A=B input combinations for AND gate are Area (μm2 ) 577.4 408.2 179.6 190.5 156.8
SUM and VDD.

Before the actual layout design of one bit comparator it

necessary to validate the schematic of logic circuit. To
overcome this problem DSCH and MICROWIND designing
tools works parallel. Firstly the design is simulated in DSCH
designing tools to know the exact functionality of the circuit
and then implemented on the layout in microwind [21].
Timing simulation of proposed one bit comparator has been
Fig 11: Logic Block Diagram of Proposed Full Adder shown in Fig.13.In order to simulate the comparator design at
logic level the design has been made in the DSCH tool and
Proposed one bit comparator has been implemented by using after launching the simulation the timing waveform can be
only 17 transistors which consists hybrid full adder by using 9 obtained by chronogram icon. As shown in Fig. 13 the
transistors [12]. In full adder Sum is realized by XOR – waveform the comparator output is according to required one
XNOR module and GDI Mux and carry is realized XOR – bit comparator operation. Timing simulation shows the exact
XNOR module and GDI Mux by using different input functionality of comparator for all three outputs.
combinations as compared Sum module. XOR-XNOR
module has been implemented by 5 transistors. In Full Adder
output of XOR-XNOR cell is used to drive the selection lines
for Sum generation and control signal lines for Carry
Generation. One bit Comparator has been designed by 9T full
adder module shown in Fig.10. This full adder has been
designed by hybridizing the PTL and GDI logic and consist
only 9 transistors which is least as compared to all previous
discussed full adder designs. Proposed one bit comparator
design has been shown in Fig. 14.e. Fig 13: Timing Simulation of Hybrid one bit Comparator

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Fig 14.a: CMOS 1-Bit Comparator Design Fig 14.b: TG 1- Bit Comparator Design

Fig 14.c: GDI 1- Bit Comparator Design Fig 14.d: PTL 1- Bit Comparator Design Fig 14.e: Hybrid 1- bit comparator Design

Fig 14: 1- Bit Comparator Design by using different logic

Different one Bit comparator designs has been proposed by

using conventional CMOS, TG, GDI, PTL and hybrid logic
styles as shown in Fig 14.a, 14.b,14.c, 14.d and 14.e
respectively. One bit comparator by conventional CMOS consist
42 transistors, TG comparator consists 36 transistors, GDI
comparator consists 16 transistors, PTL comparator consists 18
transistors and Hybrid comparator consists 17 transistors
respectively as shown in Fig.14.

6. LAYOUT ANALYSIS
In complex VLSI design manual layout designing for a very
complex circuit will become very difficult. So as compared to Fig 15: layout of proposed hybrid comparator 120nm
manual layout designing an automatic layout generation
approach is preferred. In DSCH designing tool the schematic By default W=0.6μm (10 Lambda) and L=0.12μm (2 Lambda)
diagram has been firstly designed and validated at logic level. in 120nm technology
Although DSCH 3.1 have feature to analyze timing simulation
as well as power consumption at logic level but accurate layout 7. SIMULATION RESULTS
information is still missing. Verilog file is generated by the The performance of proposed one bit comparator has been
DSCH 3.1 tool which is compiled by the MICROWIND to evaluated in terms of area and power on 120nm technology.
construct the corresponding layout with exact desired design Simulation has been performed using Microwind 3.1. Results are
rules. Another way to create the design is by NMOS and PMOS measured in terms of variation in power and current with respect
devices using cell generator provided by the microwind 3.1. The to the variation in voltage.
advantage of this approach is to avoid any design rule error.
Length and width can be adjusted by the MOS generator option
on microwind tool.

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Fig 16: Power vs. Supply Voltage on BSIM-4

Simulation have been performed using the MOS Empherical

model Level-3 and BSIM Model-4 at different power Vdd.
Threshold voltage has been taken as 0.4V for both levels.
Fig 19: Current vs. Supply Voltage on LEVEL-3

Simulation results have been shown in table-2. From table it is

clear that power dissipation increases with the power supply.
Table also shows that the power and current dissipation is less at
BSIM-4 as compared to LEVEL-3 at 1.4V input supply.

Table 3. Simulation results of 1-bit Comparator Design

BSIM-4 LEVEL-3

Supply Power Current Power Current

Voltage (mW) (mA) (mW) (mA)
(V)

Fig 17: Power vs. Supply Voltage on LEVEL-3 0.6 0.042 0.463 0.025 0.206

All results have been performed using MOS Empherical model 0.8 0.099 1.119 0.095 1.010
Level-3 and BSIM Model-4 in terms of power and current on
voltage levels 0.6, 0.8, 1, 1.2 and 1.4V and operating 1.0 0.179 1.688 0.194 2.112
temperature has been taken 270C.
1.2 0.271 1.993 0.299 2.716

1.4 0.367 2.313 0.411 3.047

Layout result will change on different technology i.e. if we use

120nm or 65nm for same circuit area consumption will be
different. Finally the analog simulation has been obtained to
know the power consumption at different voltage and
temperature by using Microwind 3.1. Analog simulation is
carried out for proposed 1-bit comparator on 120nm technology.
For 120nm VDD is fixed to 1.2V and VSS to 0V. Simulation
can be done by four ways in microwind 3.1.-Voltage vs. Time,
Voltage and current vs. time, Voltage vs. Voltage and Frequency
Fig 18: Current vs. Supply Voltage on BSIM-4 vs. Time. Voltage vs. Time simulation for proposed 1- bit
comparator has been done on 120 nm.
10 different curve fitting parameters has been used in MOS
Empherical model Level-3 whereas BSIM Model-4 work with
19 different parameters Results plotted for change in power and
current have been shown in Fig.16 and 18 for BSIM-4 and in
Fig.17 and 19 for LEVEL-3 w.r.t supply voltage and results
shows non linear dependence of the power with VDD.

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 International Journal of Computer Applications (0975 – 8887)
Volume 82 – No.10, November 2013

Table 4. Comparison of Proposed 1-bit hybrid Comparator in terms of area consumption with other 1-bit
comparator designs at 120nm Technology

Parameters CMOS TG PTL GDI HYBRID

Area (μm2) 1051.7 (μm2) 716.6 (μm2) 374.0 (μm2) 350.7 (μm2) 329.3 (μm2)

NMOS 21 19 9 8 9

PMOS 21 17 9 8 8

Threshold Voltage (V) 0.4V 0.4V 0.4V 0.4V 0.4V

Operating Temperature ( 0C ) 270C 270C 270C 270C 270C

Supply Voltage (V) 1.4 (V) 1.4 (V) 1.4 (V) 1.4 (V) 1.4 (V)

Proposed 1-bit hybrid comparator has shown improvement in [4] Etienne Sicard, Sonia Delmas Bendhia, Advance of CMOS
terms of area as compared to other 1- bit comparator designs. Cell Design, TATA Mc GRAW-HILL.
Results show that area consumed by the proposed hybrid adder
is 329.3 (μm2) on 120nm technology. At 1.4V input supply [5] Anjuli, Satyajit Anand, “2-Bit Magnitude Comparator
voltage the proposed 1-bit hybrid comparator consume Design Using Different Logic Styles,” International Journal
0.411mW power at LEVEL-3 and 0.367mW power at BSIM-4 of Engineering Science Invention, Vol. 2, No. 1, pp. 13-24.
and 2.313mA current at BSIM-4 and 3.047mA current at [6] A.N. Nagamani, H V Jayashree , H R Bhagyalakshmi,
LEVEL-3 model. “Novel Low Power Comparator Design using Reversible
Logic Gates,” International Journal of Computer Science
8. CONCLUSION and Engineering,Vol.2, No. 4, pp. 566-574.
An alternative 1-bit comparator design by hybridizing PTL and [7] H V Jayashree, A.N. Nagamani, H R Bhagyalakshmi,
GDI approach has been introduced which consists only 17 “Modified TOFFOLI GATE and its Applications in
transistors. Proposed 1-bit comparator has been implemented by Designing Components of Reversible Arithmetic and Logic
using 9 NMOS and 8 PMOS transistors. Proposed 1 bit Unit,” international journal of Advance Research in
comparator has been designed using an area efficient Full adder Computer Science and Software Engineering, Vol.2, No. 7,
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Full adder module has been also compared in terms of area from
other existing Full adder modules and used full adder module [8] H G Rangaraju, Vinayak Hegde, K B Raja, “Design and
has been proven area efficient as compared to other full adder Optimization of n-bit Reversible Binary Comparator,”
designs. This area efficient module has been used as a basic International Journal of Computer Applications, Vol. 55,
module in proposed hybrid 1-bit comparator design. Area and No.18, pp. 22-30.
simulation of proposed 1-bit comparator has been shown on [9] Anjuli, Satyajit Anand, “High speed 64-Bit CMOS Binary
120nm. The simulation results have been shown on LEVEL-3 Comparator,” International Journal of Innovative Systems
and BSIM-4 models. Area of proposed design is 329.3μm2 on Design and Engineering, Vol. 4, No. 2, pp. 45-58.
120nm technology At 1.4V input supply voltage the proposed 1-
bit hybrid comparator consume 0.411mW power at LEVEL-3 [10] Geetanjali Sharma, Uma Nirmal, Yogesh Misra, “A Low
and 0.367mW power at BSIM-4 and 2.313mA current at BSIM- Power 8-bit Magnitude Comparator with Small Transistor
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[11] Anjali Sharma, Richa Singh, Rajesh Mehra, Member, IEEE,
comparator shows that the power consumption and current is
“Low Power TG Full Adder Design Using CMOS Nano
less at BSIM-4 as compared to LEVEL-3 model.
Technology,” IEEE International Conference on Parallel,
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