Pic18f67k22 PDF
Pic18f67k22 PDF
Pic18f67k22 PDF
Data Sheet
64/80-Pin, High-Performance,
1-Mbit Enhanced Flash Microcontrollers
with 12-Bit A/D and
nanoWatt XLP Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-61341-272-5
External Bus
8/16-Bit
12-Bit CCP/
Timers
CTMU
RTCC
RE3/P3C/CCP9(2)/REF0
RD6/PSP6/SCK2/SCL2
RE2/CS/P2B/CCP10(2)
RD5/PSP5/SDI2/SDA2
RD1/PSP1/T5CKI/T7G
RD0/PSP0/CTPLS
RD4/PSP4/SDO2
RE7/ECCP2/P2A
RE5/P1C/CCP7
RE4/P3B/CCP8
RE6/P1B/CCP6
RD7/PSP7/SS2
RD2/PSP2
RD3/PSP3
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1/WR/P2C 1 48 RB0/INT0/FLT0
RE0/RD/P2D 2 47 RB1/INT1
RG0/ECCP3/P3A 3 46 RB2/INT2/CTED1
RG1/TX2/CK2/AN19/C3OUT 4 45 RB3/INT3/CTED2/ECCP2(1)/PA2
RG2/RX2/DT2/AN18/C3INA 5 44 RB4/KBI0
RG3/CCP4/AN17/P3D/C3INB 6 43 RB5/KBI1/T3CKI/T1G
MCLR/RG5 7 PIC18F65K22 42 RB6/KBI2/PGC
RG4/RTCC/T7CKI(2)/T5G/CCP5/AN16/P1D/C3INC 8 41 VSS
PIC18F66K22
VSS 9 40 OSC2/CLKO/RA6
VDDCORE/VCAP
PIC18F67K22 OSC1/CLKI/RA7
10 39
RF7/AN5/SS1 11 38 VDD
RF6/AN11/C1INA 12 37 RB7/KBI3/PGD
RF5/AN10/CVREF/C1INB 13 36 RC5/SDO1
RF4/AN9/C2INA 14 35 RC4/SDI1/SDA1
RF3/AN8/C2INB/CTMUI 15 34 RC3/SCK1/SCL1
RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1/AN6/C2OUT/CTDIN
ENVREG
AVDD
RA2/AN2/VREF-
RA1/AN1
VDD
RA0/AN0/ULPWU
RA5/AN4/T1CKI/T3G/HLVDIN
RA4/T0CKI
RC1/SOSCI/ECCP2(1)/P2A
RC0/SOSCO/SCLKI
RC6/TX1/CK1
RC7/RX1/DT1
AVSS
VSS
RA3/AN3/VREF+
Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is
in Microcontroller or Extended Microcontroller mode.
2: Not available on the PIC18F65K22 and PIC18F85K22 devices.
80-Pin TQFP
RE3/P3C/CCP9(2,3)/REF0/AD11
RE2/P2B/CCP10(2)/CS/AD10
RD6/SCK2/SCL2/PSP6/AD6
RD5/SDI2/SDA2/PSP5/AD5
RD1/T5CKI/T7G/PSP1/AD1
RE5/P1C/CCP7(3)/AD13
RE4/P3B/CCP8(3)/AD12
RE6/P1B/CCP6(3)/AD14
RD0/PSP0/CTPLS/AD0
RE7/ECCP2/P2A/AD15
RD4/SDO2/PSP4/AD4
RD7/SS2/PSP7/AD7
RD2/PSP2/AD2
RD3/PSP3/AD3
RH1/AN22/A17
RH0/AN23/A16
RJ0/ALE
RJ1/OE
VDD
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/AN21/A18 1 60 RJ2/WRL
RH3/AN20/A19 2 59 RJ3/WRH
RE1/P2C/WR/AD9 3 58 RB0/INT0/FLT0
RE0/P2D/RD/AD8 4 57 RB1/INT1
RG0/ECCP3/P3A 5 56 RB2/INT2/CTED1
RG1/TX2/CK2/AN19/C3OUT 6 55 RB3/INT3/CTED2/ECCP2(1)/P2A
RG2/RX2/DT2/AN18/C3INA 7 54 RB4/KBI0
RG3/CCP4/AN17/P3D/C3INB 8 53 RB5/KBI1/T3CKI/T1G
MCLR/RG5 9 PIC18F85K22 52 RB6/KBI2/PGC
RG4/RTCC/T7CKI(2)/T5G/CCP5/AN16/P1D/C3INC 10 51 VSS
VSS
PIC18F86K22 OSC2/CLKO/RA6
11 50
VDDCORE/VCAP 12 PIC18F87K22 49 OSC1/CLKI/RA7
RF7/AN5/SS1 13 48 VDD
RF6/AN11/C1INA 14 47 RB7/KBI3/PGD
RF5/AN10/C1INB 15 46 RC5/SDO1
RF4/AN9/C2INA 16 45 RC4/SDI1/SDA1
RF3/AN8/C2INB/CTMUI 17 44 RC3/SCK1/SCL1
RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A
RH7/CCP6(3)/P1B/AN15 19 42 RJ7/UB
RH6/CCP7(3)/P1C/AN14/C1INC 20 41 RJ6/LB
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RF1/AN6/C2OUT/CTDIN
ENVREG
RA2/AN2/VREF-
RA5/AN4/T1CKI/T3G/HLVDIN
RC0/SOSCO/SCKLI
RJ4/BA0
RJ5/CE
RA3/AN3/VREF+
RC1/SOSC/ECCP2/P2A
RC6/TX1/CK1
RC7/RX1/DT1
RH5/CCP8(3)/P3B/AN13/C2IND
RH4/CCP9(2,3)/P3C/AN12/C2INC
AVDD
RA1/AN1
VDD
RA0/AN0/ULPWU
RA4/T0CKI
AVSS
VSS
Note 1: The ECCP2 pin placement depends on the CCP2MX Configuration bit setting and whether the device is
in Microcontroller or Extended Microcontroller mode.
2: Not available on the PIC18F65K22 and PIC18F85K22 devices.
3: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration
bit (CONFIG3H<1>).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Data Bus<8>
Table Pointer<21>
PORTA
Data Latch
inc/dec logic 8 8 RA0:RA7(1,2)
Data Memory
(2/4 Kbytes)
21 PCLATU PCLATH
20 Address Latch
PCU PCH PCL
Program Counter 12 PORTB
Data Address<12>
RB0:RB7(1)
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
FSR1
FSR2 12
Data Latch PORTC
inc/dec RC0:RC7(1)
8 logic
Table Latch
8
Instruction State Machine
Decode and Control Signals
Control
PRODH PRODL PORTE
RE0: RE7(1)
8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer
BITOP W
INTRC Oscillator 8 8
Oscillator 8
Start-up Timer
16 MHz PORTF
Oscillator Power-on 8 8
Reset RF1:RF7(1)
Precision ALU<8>
Band Gap Watchdog
Reference Timer
8
ENVREG BOR and
Voltage LVD
Regulator
PORTG
RG0:RG5(1)
VDDCORE/VCAP VDD, VSS MCLR
CCP ECCP
4/5/6/7/8/9(3)/10(3) 1/2/3 EUSART1 EUSART2 RTCC MSSP1/2
Table Pointer<21>
PORTA
Data Latch
inc/dec logic 8 8
RA0:RA7(1,2)
Data Memory
(2/4 Kbytes)
21 PCLATU PCLATH
20 Address Latch
PCU PCH PCL PORTB
Program Counter 12 RB0:RB7(1)
Data Address<12>
31-Level Stack
Address Latch 4 12 4
BSR Access PORTC
Program Memory STKPTR FSR0 Bank
System Bus Interface
FSR1 RC0:RC7(1)
Data Latch FSR2 12
inc/dec
8 logic PORTD
Table Latch
RD0:RD7(1)
ROM Latch
Address
Decode
Instruction Bus <16>
PORTE
IR
AD15:0, A19:16 RE0:RE7(1)
(Multiplexed with PORTD,
PORTE and PORTH) 8
Instruction State Machine
Decode and Control Signals
Control PORTF
PRODH PRODL
RF1:RF7(1)
8 x 8 Multiply
Timing 3
Power-up 8
OSC2/CLKO Generation
OSC1/CLKI Timer
BITOP W PORTG
INTRC Oscillator 8 8
Oscillator 8
Start-up Timer RG0:RG5(1)
16 MHz
Oscillator Power-on 8 8
Reset
Precision ALU<8> PORTH
Band Gap Watchdog
Reference Timer
8 RH0:RH7(1)
ENVREG BOR and
Voltage
Regulator LVD
PORTJ
CCP ECCP
4/5/6/7/8/9(3)/10(3) 1/2/3 EUSART1 EUSART2 RTCC MSSP1/2
RD6/SCK2/SCL2/PSP6/ 64
AD6
RD6 I/O ST Digital I/O.
SCK2 I/O ST Synchronous serial clock input/output for SPI mode.
SCL2 I/O I2C Synchronous serial clock input/output for I2C™ mode.
PSP6(4) I/O TTL Parallel Slave Port data.
AD6 I/O TTL External Memory Address/Data 6.
RD7/SS2/PSP7/AD7 63
RD7 I/O ST Digital I/O.
SS2 I TTL SPI slave select input.
PSP7(4) I/O TTL Parallel Slave Port data.
AD7 I/O TTL External Memory Address/Data 7.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C = I2C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
RE6/P1B/CCP6/AD14 74
RE6 I/O ST Digital I/O.
P1B O — ECCP1 PWM Output B.
CCP6(5) I/O ST Capture 6 input/Compare 6 output/PWM6 output.
AD14 I/O ST External Memory Address/Data 14.
RE7/ECCP2/P2A/AD15 73
RE7 I/O ST Digital I/O.
ECCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output.
P2A O — ECCP2 PWM Output A.
AD15 I/O ST External Memory Address/Data 15.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C = I2C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
RH7/CCP6/P1B/AN15 19
RH7 I/O ST Digital I/O.
CCP6(5) I/O ST Capture 6 input/Compare 6 output/PWM6 output.
P1B O — ECCP1 PWM Output B.
AN15 I Analog Analog Input 15.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C = I2C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
VSS
VDD
R1 (1) (1)
8-bit microcontrollers requires attention to a minimal R2
set of device pin connections before proceeding with ENVREG
MCLR
development. VCAP/VDDCORE
C1
The following pins must always be connected: C7(2)
PIC18FXXKXX
• All VDD and VSS pins
VDD
(see Section 2.2 “Power Supply Pins”) VSS
C6(2) C3(2)
• All AVDD and AVSS pins, regardless of whether or VSS
VDD
not the analog device features are used
AVDD
AVSS
VDD
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
C5(2) C4(2)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
Key (all values are recommendations):
These pins must also be connected if they are being C1 through C6: 0.1 F, 20V ceramic
used in the end application:
R1: 10 kΩ
• PGC/PGD pins used for In-Circuit Serial R2: 100Ω to 470Ω
Programming™ (ICSP™) and debugging purposes
Note 1: See Section 2.4 “Voltage Regulator Pins
(see Section 2.5 “ICSP Pins”) (ENVREG and VCAP/VDDCORE)” for
• OSCI and OSCO pins when an external oscillator explanation of ENVREG pin connections.
source is used 2: The example shown is for a PIC18F device
(see Section 2.6 “External Oscillator Pins”) with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
Additionally, the following pins may be required:
adjust the number of decoupling capacitors
• VREF+/VREF- pins are used when external voltage appropriately.
reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
0.001
0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
Note: Typical data measurement at 25°C, 0V DC bias.
.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS
Nominal
Make Part # Base Tolerance Rated Voltage Temp. Range
Capacitance
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC
Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC
Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC
Ceramic capacitors are suitable for use with the inter- -30
-40
nal voltage regulator of this microcontroller. However, -50
10V Capacitor
some care is needed in selecting the capacitor to -60
-70
6.3V Capacitor
ensure that it maintains sufficient capacitance over the -80
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
intended operating range of the application.
DC Bias Voltage (VDC)
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the
ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a
often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a
-20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt-
that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at
also vary based on additional factors, such as the 16V for the 2.5V core voltage. Suggested capacitors
applied DC bias voltage and the temperature. The total are shown in Table 2-1.
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification. 2.5 ICSP Pins
The X5R and X7R capacitors typically exhibit satisfac- The PGC and PGD pins are used for In-Circuit Serial
tory temperature stability (ex: ±15% over a wide Programming™ (ICSP™) and debugging purposes. It
temperature range, but consult the manufacturer’s data is recommended to keep the trace length between the
sheets for exact specifications). However, Y5V capaci- ICSP connector and the ICSP pins on the device as
tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to
specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom-
temperature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of
capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω.
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V Pull-up resistors, series diodes and capacitors on the
capacitors are not recommended for use with the PGC and PGD pins are not recommended as they will
internal regulator if the application must operate over a interfere with the programmer/debugger communica-
wide temperature range. tions to the device. If such discrete components are an
application requirement, they should be removed from
In addition to temperature tolerance, the effective the circuit during programming and debugging. Alter-
capacitance of large value ceramic capacitors can vary natively, refer to the AC/DC characteristics and timing
substantially, based on the amount of DC voltage requirements information in the respective device
applied to the capacitor. This effect can be very signifi- Flash programming specification for information on
cant, but is often overlooked or is not always capacitive loading limits, and pin input voltage high
documented. (VIH) and input low (VIL) requirements.
A typical DC bias voltage vs. capacitance graph for For device emulation, ensure that the “Communication
X7R type and Y5V type capacitors is shown in Channel Select” (i.e., PGCx/PGDx pins), programmed
Figure 2-4. into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
SOSCO
SOSCI
4x PLL Peripherals
Mux
MUX
OSC2
MUX
CPU
OSC1 PLLEN
FOSC<3:0> and PLLCFG
IDLEN
101
HF INTOSC 2 MHz 2 MHz
MUX
100 FOSC<3:0>
16 MHz to 1 MHz 1 MHz
011
31 kHz 500 kHz 500 kHz
010
250 kHz 250 kHz
001
31 kHz 31 kHz
000
MUX
500 kHz
Postscaler
IRCF<2:0>
MF INTOSC 250 kHz
MUX
500 kHz to
31 kHz
31 kHz
INTSRC
MFIOSEL
LF INTOSC 31 kHz
31 kHz
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
Note 1: The Reset state depends on the state of the IESO Configuration bit (CONFIG1H<7>).
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>).
4: Modifying these bits will cause an immediate clock source switch.
5: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>.
6: Lowest power option for an internal source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
OSC2 Sleep
Note 1: See Table 3-2 and Table 3-3 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
OSC2
An external clock source may also be connected to the Phase
OSC1 pin in HS mode, as shown in Figure 3-6. In this HS or EC FIN Comparator
OSC1 Mode FOUT
configuration, the divide-by-4 output on OSC2 is not
available. Current consumption in this configuration will
be somewhat higher than EC mode, as the internal Loop
oscillator’s feedback circuitry will be enabled (in EC Filter
mode, the feedback circuit is disabled).
MUX
OPERATION (HS OSC
CONFIGURATION)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For ROSEL (REVOCON<4>), the primary oscillator is available only when configured as the default via the
FOSC settings. This is regardless of whether the device is in Sleep mode.
These categories define which portions of the device 4.1.2 ENTERING POWER-MANAGED
are clocked, and sometimes, at what speed. The Run MODES
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator Switching from one power-managed mode to another
block). The Sleep mode does not use a clock source. begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
The ULPWU mode, on the RA0 pin, enables a slow fall- which Run or Idle mode is used. Changing these bits
ing voltage to generate a wake-up, even from Sleep, causes an immediate switch to the new clock source,
without excess current consumption. (See Section 4.7 assuming that it is running. The switch may also be
“Ultra Low-Power Wake-up”.) subject to clock transition delays. These considerations
The power-managed modes include several power- are discussed in Section 4.1.3 “Clock Transitions
saving features offered on previous PIC® devices. One and Status Indicators” and subsequent sections.
is the clock switching feature, offered in other PIC18 Entering the power-managed Idle or Sleep modes is
devices. This feature allows the controller to use the triggered by the execution of a SLEEP instruction. The
SOSC oscillator instead of the primary one. Another actual mode that results depends on the status of the
power-saving feature is Sleep mode, offered by all PIC IDLEN bit.
devices, where all device clocks are stopped.
Depending on the current and impending mode, a
change to a power-managed mode does not always
4.1 Selecting Power-Managed Modes
require setting all of the previously discussed bits. Many
Selecting a power-managed mode requires two transitions can be done by changing the oscillator select
decisions: bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
• Will the CPU be clocked or not
desired, it may only be necessary to perform a SLEEP
• What will be the clock source instruction to switch to the desired mode.
SOSCI 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
LF-INTOSC 1 2 3 n-1 n
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: RTCCMD can only be set to ‘1’ after an EECON2 unlock sequence. Refer to Section 18.0 “Real-Time
Clock and Calendar (RTCC)” for the unlock sequence (Example 18-1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RESET Instruction
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
PWRT
32 s PWRT 66 ms Chip_Reset
R Q
LF-INTOSC 11-Bit Ripple Counter
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
• High-Power BOR
• Medium Power BOR 5.4.1 DETECTING BOR
• Low-Power BOR The BOR bit always resets to ‘0’ on any Brown-out
• Zero-Power BOR Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
Each power Mode is selected by the BORPWR<1:0>
just by reading the state of BOR alone. A more reliable
bits setting (CONFIG2L<6:5>). For low, medium and method is to simultaneously check the state of both
high-power BOR, the module monitors the VDD depend- POR and BOR. This assumes that the POR bit is reset
ing on the BORV<1:0> setting (CONFIG1L<3:2>). A
to ‘1’ in software immediately after any Power-on Reset
BOR event re-arms the Power-on Reset. It also causes event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
a Reset, depending on which of the trip levels has been assumed that a Brown-out Reset event has occurred.
set: 1.8V, 2V, 2.7V or 3V.
LP-BOR cannot be detected with the BOR bit in the
BOR is enabled by the BOREN<1:0> bits
RCON register. LP-BOR can rearm the POR and can
(CONFIG2L<2:1>) and the SBOREN bit (RCON<6>). cause a Power-on Reset.
Typical power consumption is listed as Parameter D022A
in Section 31.0 “Electrical Characteristics”.
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD 0V 1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
007FFFh
00FFFFh
1FFFFFh
Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
00011
Top-of-Stack 001A34h 00010
000D58h 00001
00000
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
6.2.4 TWO-WORD INSTRUCTIONS used by the instruction sequence. If the first word is
skipped, for some reason, and the second word is
The standard PIC18 instruction set has four, two-word
executed by itself, a NOP is executed instead. This is
instructions: CALL, MOVFF, GOTO and LSFR. In all
necessary for cases when the two-word instruction is
cases, the second word of the instructions always has
preceded by a conditional instruction that changes the
‘1111’ as its four Most Significant bits. The other 12 bits
PC. Example 6-4 shows how this works.
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction Note: For information on two-word instructions
specifies a special form of NOP. If the instruction is in the extended instruction set, see
executed in proper sequence, immediately after the Section 6.5 “Program Memory and the
first word, the data in the second word is accessed and Extended Instruction Set”.
Note 1: Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users must
always use the complete address, or load the proper BSR value, to access these registers.
2: These addresses are unused for devices with 32 Kbytes of program memory (PIC18FX5K22). For those
devices, read these addresses at 00h.
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
6.3.2 ACCESS BANK however, the instruction is forced to use the Access
Bank address map. In that case, the current value of
While the use of the BSR, with an embedded 8-bit
the BSR is ignored entirely.
address, allows users to address the entire range of data
memory, it also means that the user must ensure that the Using this “forced” addressing allows the instruction to
correct bank is selected. If not, data may be read from, operate on a data address in a single cycle without
or written to, the wrong location. This can be disastrous updating the BSR first. For 8-bit addresses of 60h and
if a GPR is the intended target of an operation, but an above, this means that users can evaluate and operate
SFR is written to instead. Verifying and/or changing the on SFRs more efficiently. The Access RAM below 60h
BSR for each read or write to data memory can become is a good place for data values that the user might need
very inefficient. to access rapidly, such as immediate computational
results or common program variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with Access RAM also allows for faster and more code
an Access Bank, which allows users to access a efficient context saving and switching of variables.
mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different
The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST
memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail
memory (60h-FFh) in Bank 15. The lower half is known in Section 6.6.3 “Mapping the Access Bank in
as the “Access RAM” and is composed of GPRs. The Indexed Literal Offset Mode”.
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the 6.3.3 GENERAL PURPOSE
Access Bank and can be addressed in a linear fashion REGISTER FILE
by an eight-bit address (Figure 6-6).
PIC18 devices may have banked memory in the GPR
The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all
that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0
the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of
uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on
opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets.
FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ----
FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ----
FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ----
FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of ---- ----
FSR1 offset by W
FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- xxxx
FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx
FE0h BSR — — — — Bank Select Register ---- 0000
FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ----
FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ----
FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ----
FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ----
FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of ---- ----
FSR2 offset by W
FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- xxxx
FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx
FD8h STATUS — — — N OV Z DC C ---x xxxx
FD7h TMR0H Timer0 Register High Byte 0000 0000
FD6h TMR0L Timer0 Register Low Byte xxxx xxxx
FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA TOPS2 TOPS1 TOPS0 1111 1111
FD4h SPBRGH1 USART1 Baud Rate Generator High Byte 0000 0000
FD3h OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0110 q000
FD2h IPR5 TMR7GIP(3) TMR12IP(3) TMR10IP(3) TMR8IP TMR7IP(3) TMR6IP TMR5IP TMR4IP 1111 1111
FD1h WDTCON REGSLP — ULPLVL SRETEN — ULPEN ULPSINK SWDTEN 0-x0 -000
FD0h RCON IPEN SBOREN CM RI TO PD POR BOR 0111 11qq
FCFh TMR1H Timer1 Register High Byte xxxx xxxx
FCEh TMR1L Timer1 Register Low Byte xxxx xxxx
FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON 0000 0000
FCCh TMR2 Timer2 Register 0000 0000
FCBh PR2 Timer2 Period Register 1111 1111
FCAh T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
FC9h SSP1BUF MSSP Receive Buffer/Transmit Register xxxx xxxx
FC8h SSP1ADD MSSP Address Register in I2C™ Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode. 0000 0000
FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000
FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
FC4h ADRESH A/D Result Register High Byte xxxx xxxx
FC3h ADRESL A/D Result Register Low Byte xxxx xxxx
FC2h ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000
FC1h ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 0000 0000
FC0h ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000
FBFh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000
FBEh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000
FBDh CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx
FBCh CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx
FBBh CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
FBAh PIR5 TMR7GIF(3) TMR12IF(3) TMR10IF(3) TMR8IF TMR7IF(3) TMR6IF TMR5IF TMR4IF 0000 0000
FB9h PIE5 TMR7GIE(3) TMR12IE(3) TMR10IE(3) TMR8IE TMR7IE(3) TMR6IE TMR5IE TMR4IE 0000 0000
FB8h IPR4 CCP10IP(3) CCP9IP(3) CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP 1111 1111
FB7h PIR4 CCP10IF(3) CCP9IF(3) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF 0000 0000
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
FB6h PIE4 CCP10IE(3) CCP9IE(3) CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE 0000 0000
FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 0000
FB4h CMSTAT CMP3OUT CMP2OUT CMP1OUT — — — — — xxx- ----
FB3h TMR3H Timer3 Register High Byte xxxx xxxx
FB2h TMR3L Timer3 Register Low Byte xxxx xxxx
FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON 0000 0000
FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS1 T3GSS0 0000 0x00
T3DONE
FAFh SPBRG1 USART1 Baud Rate Generator 0000 0000
FAEh RCREG1 USART1 Receive Register 0000 0000
FADh TXREG1 USART1 Transmit Register xxxx xxxx
FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
FAAh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00
T1DONE
FA9h IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP ---1 -111
FA8h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000
FA7h PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ----
FA6h PIR6 — — — EEIF — CMP3IF CMP2IF CMP1IF ---0 -000
FA5h IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 1-11 1111
FA4h PIR3 TMR5GiF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 0-00 0000
FA3h PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 0-00 0000
FA2h IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP 1-11 1111
FA1h PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF 0-00 0000
FA0h PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE 0-00 0000
F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 1111 1111
F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 0000 0000
F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 0000 0000
F9Ch PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000
F9Ah TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111
F99h TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111
F98h TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111
F97h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 1111 111-
F96h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 — 1111 111-
F95h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111
F91h LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx
F90h LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx
F8Fh LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx
F8Eh LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — xxxx xxx-
F8Dh LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx
F8Ch LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx
F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx
F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx
F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx
F88h PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx
F87h PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
F86h PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 --xx xxxx
F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — xxxx xxx-
F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx
F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx
F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx
F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx
F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx
F7Fh EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000
F7Eh EECON2 EEPROM Control Register 2 (not a physical register) ---- ----
F7Dh TMR5H Timer5 Register High Byte xxxx xxxx
F7Ch TMR5L Timer5 Register Low Byte xxxx xxxx
F7Bh T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC RD16 TMR5ON 0000 0000
F7Ah T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS1 T5GSS0 0000 0x00
T5DONE
F79h CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx
F78h CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx
F77h CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000
F76h CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx
F75h CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx
F74h CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000
F73h CCPR6H Capture/Compare/PWM Register 6 High Byte xxxx xxxx
F72h CCPR6L Capture/Compare/PWM Register 6 Low Byte xxxx xxxx
F71h CCP6CON — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000
F70h CCPR7H Capture/Compare/PWM Register 7 High Byte xxxx xxxx
F6Fh CCPR7L Capture/Compare/PWM Register 7 Low Byte xxxx xxxx
F6Eh CCP7CON — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000
F6Dh TMR4 Timer4 Register xxxx xxxx
F6Ch PR4 Timer4 Period Register 1111 1111
F6Bh T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -111 1111
F6Ah SSP2BUF MSSP Receive Buffer/Transmit Register xxxx xxxx
F69h SSP2ADD MSSP Address Register in I2C™ Slave Mode. MSSP1 Baud Rate Reload Register in I2C Master Mode. 0000 0000
F68h SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000
F67h SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
F66h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0100 0000
F65h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00
F64h OSCCON2 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL -0-- 0-x0
F63h EEADRH EEPROM Address Register High Byte 0000 0000
F62h EEADR EEPROM Address Register Low Byte 0000 0000
F61h EEDATA EEPROM Data Register 0000 0000
F60h PIE6 — — — EEIE — CMP3IE CMP2IE CMP1IE ---0 -000
F5Fh RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000
F5Eh RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000
F5Dh RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> xxxx xxxx
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
F5Ch RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> 0000 0000
F5Bh ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000
F5Ah ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000
F59h ALRMVALH Alarm Value High Register Window Based on APTR<1:0> xxxx xxxx
F58h ALRMVALL Alarm Value Low Register Window Based on APTR<1:0> xxxx xxxx
F57h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000
F56h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000
F55h CTMUICONH ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000
F54h CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F53h PADCFG1 RDPU REPU RJPU(2) — — RTSECSEL1 RTSECSEL0 — 000- -00-
F52h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000
F51h ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000
F50h CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx
F4Fh CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx
F4Eh CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000
F4Dh ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000
F4Ch ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000
F4Bh CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx
F4Ah CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx
F49h CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000
F48h CCPR8H Capture/Compare/PWM Register 8 High Byte xxxx xxxx
F47h CCPR8L Capture/Compare/PWM Register 8 Low Byte xxxx xxxx
F46h CCP8CON — — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 --00 0000
F45h CCPR9H(3) Capture/Compare/PWM Register 9 High Byte xxxx xxxx
F44h CCPR9L(3) Capture/Compare/PWM Register 9 Low Byte xxxx xxxx
F43h CCP9CON(3) — — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 --00 0000
F42h CCPR10H(3) Capture/Compare/PWM Register 10 High Byte xxxx xxxx
F41h CCPR10L(3) Capture/Compare/PWM Register 10 Low Byte xxxx xxxx
F40h CCP10CON(3) — — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 --00 0000
F3Fh TMR7H(3) Timer7 Register High Byte xxxx xxxx
F3Eh TMR7L(3) Timer7 Register Low Byte 0000 0000
(3)
F3Dh T7CON TMR7CS1 TMR7CS0 T7CKPS1 T7CKPS0 SOSCEN T7SYNC RD16 TMR7ON 0000 0000
F3Ch T7GCON(3) TMR7GE T7GPOL T7GTM T7GSPM T7GGO/ T7GVAL T7GSS1 T7GSS0 0000 0x00
T7DONE
F3Bh TMR6 Timer6 Register 0000 0000
F3Ah PR6 Timer6 Period Register 1111 1111
F39h T6CON — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000
F38h TMR8 Timer8 Register 0000 0000
F37h PR8 Timer8 Period Register 1111 1111
F36h T8CON — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 -000 0000
F35h TMR10(3) TMR10 Register 0000 0000
F34h PR10(3) Timer10 Period Register 1111 1111
F33h T10CON(3) — T10OUTPS3 T10OUTPS2 T10OUTPS1 T10OUTPS0 TMR10ON T10CKPS1 T10CKPS0 -000 0000
F32h TMR12(3) TMR12 Register 0000 0000
F31h PR12(3) Timer12 Period Register 1111 1111
F30h T12CON(3) — T12OUTPS3 T12OUTPS2 T12OUTPS1 T12OUTPS0 TMR12ON T12CKPS1 T12CKPS0 -000 0000
F2Fh CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F2Eh CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F2Dh CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 0000 0000
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
F2Ch CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 00-0 -000
F2Bh CCPTMRS2 — — — C10TSEL0(3) — C9TSEL0(3) C8TSEL1 C8TSEL0 ---0 -000
F2Ah REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000
F29h ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD 000- ---0
F28h ODCON2 CCP10OD(3) CCP9OD(3) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 0000 0000
F27h ODCON3 U2OD U1OD — — — — — CTMUDS 00-- ---0
F26h MEMCON(2) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00
F25h ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 1111 1111
F24h ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 1111 1111
F23h ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 1111 1111
F22h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
F21h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
F20h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00
F1Fh SPBRGH2 USART2 Baud Rate Generator High Byte 0000 0000
F1Eh SPBRG2 USART2 Baud Rate Generator 0000 0000
F1Dh RCREG2 Receive Data FIFO 0000 0000
F1Ch TXREG2 Transmit Data FIFO xxxx xxxx
F1Bh PSTR2CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
F1Ah PSTR3CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA 00-0 0001
F19h PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD 0000 0000
F18h PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD 0000 0000
F17h PMD2 TMR10MD(3) TMR8MD TMR7MD(3) TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD 0000 0000
F16h PMD3 CCP10MD(3) CCP9MD(3) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(3) 0000 0000
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand.
000h
When a = 0 and f 60h:
The instruction executes in 060h
Direct Forced mode. ‘f’ is Bank 0
interpreted as a location in the 100h
Access RAM, between 060h 00h
and FFFh. This is the same as Bank 1 60h
locations, F60h to FFFh through
Bank 14 Valid range
(Bank 15), of data memory. for ‘f’
Locations below 060h are not FFh
F00h
available in this addressing Access RAM
Bank 15
mode.
F40h
SFRs
FFFh
Data Memory
BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
060h
Direct mode (also known as
Direct Long mode). ‘f’ is 100h
interpreted as a location in
one of the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F40h
SFRs
FFFh
Data Memory
Example Situation:
ADDWF f, d, a 000h
Not Accessible
FSR2H:FSR2L = 120h 05Fh
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
7.2 Control Registers The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, allows a write operation. On
• EECON2 register power-up, the WREN bit is clear. The WRERR bit is set
• TABLAT register in hardware when the WR bit is set and cleared when
• TBLPTR registers the internal programming timer expires and the write
operation is complete.
7.2.1 EECON1 AND EECON2 REGISTERS Note: During normal operation, the WRERR is
The EECON1 register (Register 7-1) is the control read as ‘1’. This can indicate that a write
register for memory accesses. The EECON2 register, operation was prematurely terminated by
not a physical register, is used exclusively in the a Reset or a write operation was
memory write and erase sequences. Reading attempted improperly.
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
The EEPGD control bit determines if the access is a
cannot be cleared, only set, in software. It is cleared in
program or data EEPROM memory access. When
hardware at the completion of the write operation.
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent Note: The EEIF interrupt flag bit (PIR6<4>) is
operations operate on the program memory. set when the write is complete. It must be
The CFGS control bit determines if the access is to the cleared in software.
Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations operate on Configuration
registers regardless of EEPGD (see Section 28.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
Program Memory
8 8 8 8
Program Memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TABLE 8-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Multiplexed Data and Address Only Lines
Ports Available
Data Width Address Width Address Lines (and (and Corresponding
for I/O
Corresponding Ports) Ports)
AD<11:8> PORTE<7:4>,
12-bit
(PORTE<3:0>) All of PORTH
AD<15:8>
16-bit AD<7:0> All of PORTH
8-bit (PORTE<7:0>)
(PORTD<7:0>)
A<19:16>, AD<15:8>
20-bit (PORTH<3:0>, —
PORTE<7:0>)
16-bit AD<15:0> — All of PORTH
16-bit (PORTD<7:0>, A<19:16>
20-bit PORTE<7:0>) —
(PORTH<3:0>)
D<7:0>
A<19:16>(1)
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
PIC18F87K22
AD<7:0> A<20:1> JEDEC Word
373 A<x:0>
EPROM Memory
D<15:0>
D<15:0>
CE OE WR(2)
AD<15:8>
373
ALE
A<19:16>(1)
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
PIC18F87K22
AD<7:0> A<20:1>
373 A<x:1> JEDEC Word
Flash Memory
D<15:0>
D<15:0>
AD<15:8> 138(3) CE
373 A0
ALE BYTE/WORD OE WR(1)
A<19:16>(2)
OE
WRH
WRL A<20:1>
A<x:1> JEDEC Word
BA0 SRAM Memory
I/O
D<15:0>
CE D<15:0>
LB LB
UB UB OE WR(1)
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
2: Upper order address lines are used only for 20-bit address width.
3: Demultiplexing is only required when multiple memory devices are accessed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16> 0Ch
CE
ALE
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
CE
ALE
OE
Instruction
Execution INST(PC – 2) SLEEP
D<7:0>
PIC18F87K22
AD<7:0> A<19:0>
373 A<x:1>
ALE D<15:8> A0
D<7:0>
AD<15:8>(1)
CE
(1)
A<19:16> OE WR(2)
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
2: This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16> 0Ch
AD<15:8> CFh
CE
ALE
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
BA0
CE
ALE
OE
Instruction
Execution INST(PC – 2) SLEEP
The EEADRH:EEADR register pair is used to address Note: The EEIF interrupt flag bit (PIR6<4>) is
the data EEPROM for read and write operations. set when the write is complete; it must be
EEADRH holds the two MSbs of the address; the upper cleared in software.
6 bits are ignored. The 10-bit range of the pair can Control bits, RD and WR, start read and erase/write
address a memory range of 1024 bytes (00h to 3FFh). operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 7.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
PIR1<7:0>
PIE1<7:0> TMR0IF Wake-up if in
IPR1<7:0> TMR0IE Idle or Sleep modes
TMR0IP
RBIF
PIR2<7,5:0> RBIE
PIE2<7,5:0> RBIP
IPR2<7,5:0> INT0IF
INT0IE
PIR3<7,5> INT1IF
PIE3<7,5> INT1IE Interrupt to CPU
IPR3<7,5> INT1IP Vector to Location
INT2IF
INT2IE 0008h
PIR4<7:0>
PIE4<7:0> INT2IP
IPR4<7:0> INT3IF
INT3IE
INT3IP
GIE/GIEH
PIR5<7:0>
PIE5<7:0>
IPR5<7:0> IPEN
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7, 5:0>
PIE2<7, 5:0>
IPR2<7, 5:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE IPEN
PIR3<7, 5:0> 0018h
PIE3<7, 5:0> TMR0IP
IPR3<7, 5:0>
RBIF
PIR4<7:0> RBIE
PIE4<7:0> RBIP GIE/GIEH
IPR4<7:0> PEIE/GIEL
INT1IF
INT1IE
PIR5<7:0> INT1IP
PIE5<7:0> INT2IF
IPR5<7:0> INT2IE
INT2IP
PIR6<4, 2:0> INT3IF
PIE6<4, 2:0> INT3IE
IPR6<4, 2:0> INT3IP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction
cycle, will end the mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
D Q
WR TRIS
CKx
TRIS Latch Input
Buffer
RD TRIS
Q D
ENEN
RD PORT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
12.1.4 ANALOG AND DIGITAL PORTS Setting these registers makes the corresponding pins
analog and clearing the registers makes the ports digi-
Many of the ports multiplex analog and digital function-
tal. For details on these registers, see Section 23.0
ality, providing a lot of flexibility for hardware designers.
“12-Bit Analog-to-Digital Converter (A/D) Module”.
PIC18F87K22 family devices can make any analog pin
analog or digital, depending on an application’s needs.
The ports’ analog/digital functionality is controlled by
registers: ANCON0, ANCON1 and ANCON2.
12.10 PORTJ, TRISJ and Each of the PORTJ pins has a weak internal pull-up.
LATJ Registers The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
Note: PORTJ is available only on 80-pin devices. up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PADCFG1<5>).
PORTJ is an 8-bit wide, bidirectional port. The The weak pull-up is automatically turned off when the
corresponding Data Direction and Output Latch registers port pin is configured as an output. The pull-ups are
are TRISJ and LATJ. disabled on any device Reset.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually EXAMPLE 12-9: INITIALIZING PORTJ
configurable as an input or output. CLRF PORTJ ; Initialize PORTJ by
Note: These pins are configured as digital inputs ; clearing output latches
CLRF LATJ ; Alternate method
on any device Reset.
; to clear output latches
When the external memory interface is enabled, all of MOVLW 0CFh ; Value used to
the PORTJ pins function as control outputs for the inter- ; initialize data
face. This occurs automatically when the interface is ; direction
MOVWF TRISJ ; Set RJ3:RJ0 as inputs
enabled by clearing the EBDIS control bit
; RJ5:RJ4 as output
(MEMCON<7>). The TRISJ bits are also overridden. ; RJ7:RJ6 as inputs
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FOSC/4 0
1
Sync with Set
1 Internal TMR0L TMR0IF
T0CKI Pin Programmable 0 Clocks on Overflow
Prescaler
T0SE (2 TCY Delay)
T0CS 8
3
T0PS<2:0>
8
PSA Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
1
Sync with TMR0 Set
1 Internal TMR0L High Byte TMR0IF
T0CKI Pin Programmable 0 Clocks on Overflow
Prescaler 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS<2:0>
Write TMR0L
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T1GSS<1:0>
T1G 00 T1GSPM
TMR1CS<1:0> T1SYNC
SOSCO/SCLKI OUT(4)
RC0
14.5.1 USING SOSC AS A
CLOCK SOURCE RC1
The SOSC oscillator is also available as a clock source
in power-managed modes. By setting the System
Clock Select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, RC2
the device switches to SEC_RUN mode, and both the Note: Not drawn to scale.
CPU and peripherals are clocked from the SOSC oscil-
lator. If the IDLEN bit (OSCCON<7>) is cleared and a In the Low Drive Level mode, SOSCSEL<1:0> = 01, it is
SLEEP instruction is executed, the device enters critical that RC2 I/O pin signals be kept away from the
SEC_IDLE mode. Additional details are available in oscillator circuit. Configuring RC2 as a digital output, and
Section 4.0 “Power-Managed Modes”. toggling it, can potentially disturb the oscillator circuit,
Whenever the SOSC oscillator is providing the clock even with a relatively good PCB layout. If possible, either
source, the SOSC System Clock Status flag, leave RC2 unused or use it as an input pin with a slew
SOSCRUN (OSCCON2<6>), is set. This can be used rate limited signal source. If RC2 must be used as a
to determine the controller’s current clocking mode. It digital output, it may be necessary to use the Higher
can also indicate the clock source currently being used Drive Level Oscillator mode (SOSCSEL<1:0> = 11) with
by the Fail-Safe Clock Monitor (FSCM). many PCB layouts.
If the Clock Monitor is enabled and the SOSC oscillator Even in the Higher Drive Level mode, careful layout
fails while providing the clock, polling the SOCSRUN procedures should still be followed when designing the
bit will indicate whether the clock is being provided by oscillator circuit.
the SOSC oscillator or another source. In addition to dV/dt induced noise considerations, it is
important to ensure that the circuit board is clean. Even
14.5.2 SOSC OSCILLATOR LAYOUT
a very small amount of conductive soldering flux
CONSIDERATIONS residue can cause PCB leakage currents that can
The SOSC oscillator circuit draws very little power overwhelm the oscillator circuit.
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when 14.6 Timer1 Interrupt
the oscillator is configured for extremely Low-Power The TMR1 register pair (TMR1H:TMR1L) increments
mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01. from 0000h to FFFFh and rolls over to 0000h. The
The oscillator circuit, displayed in Figure 14-2, should Timer1 interrupt, if enabled, is generated on overflow
be located as close as possible to the microcontroller. which is latched in interrupt flag bit, TMR1IF
There should be no circuits passing within the oscillator (PIR1<0>). This interrupt can be enabled or disabled
circuit boundaries other than VSS or VDD. by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
14.8 Timer1 Gate Note: The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
Timer1 can be configured to count freely or the count can
ment of a particular timer to a CCP/ECCP
be enabled and disabled using the Timer1 gate circuitry.
module is determined by the Timer to CCP
This is also referred to as Timer1 gate count enable.
enable bits in the CCPTMRSx registers.
Timer1 gate can also be driven by multiple selectable For more details, see Register 19-2,
sources. Register 19-3 and Register 20-2.
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
14.8.2 TIMER1 GATE SOURCE occurs, a low-to-high pulse will automatically be gener-
SELECTION ated and internally supplied to the Timer1 gate circuitry.
The pulse will remain high for one instruction cycle and
The Timer1 gate source can be selected from one of
will return back to a low state until the next match.
four sources. Source selection is controlled by the
T1GSSx (T1GCON<1:0>) bits (see Table 14-4). The T1GPOL bit determines when the Timer1 counter
increments based on this pulse. When T1GPOL = 1,
TABLE 14-4: TIMER1 GATE SOURCES Timer1 increments for a single instruction cycle follow-
ing a TMR2 match with PR2. When T1GPOL = 0,
T1GSS<1:0> Timer1 Gate Source Timer1 increments continuously, except for the cycle
00 Timer1 Gate Pin following the match, when the gate signal goes from
low-to-high.
01 TMR2 to Match PR2
(TMR2 increments to match PR2) 14.8.2.3 Comparator 1 Output Gate
10 Comparator 1 Output Operation
(comparator logic high output)
The output of Comparator 1 can be internally supplied
11 Comparator 2 Output to the Timer1 gate circuitry. After setting up
(comparator logic high output) Comparator 1 with the CM1CON register, Timer1 will
The polarity for each available source is also selectable, increment depending on the transitions of the
controlled by the T1GPOL bit (T1GCON<6>). CMP1OUT (CMSTAT<5>) bit.
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Cleared by
RTCCIF Cleared by Software Set by Hardware on Software
Falling Edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by Hardware on
T1GGO/ Set by Software Falling Edge of T1GVAL
T1DONE
Counting Enabled on
Rising Edge of T1G
T1G_IN
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
T2OUTPS<3:0> Set TMR2IF
Postscaler
2
T2CKPS<1:0> TMR2 Output
(to PWM or MSSPx)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare
features.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T3GSS<1:0>
T3G 00 T3GSPM
TMR3CS<1:0> T3SYNC
SOSCO/SCLKI OUT(4)
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
16.5.2.1 TxG Pin Gate Operation 16.5.3 TIMER3/5/7 GATE TOGGLE MODE
The TxG pin is one source for Timer3/5/7 gate control. It When Timer3/5/7 Gate Toggle mode is enabled, it is
can be used to supply an external source to the Timerx possible to measure the full cycle length of a Timer3/5/7
gate circuitry. gate signal, as opposed to the duration of a single level
pulse.
16.5.2.2 Timer4/6/8 Match Gate Operation
The Timerx gate source is routed through a flip-flop that
The TMR(x+1) register will increment until it matches the changes state on every incrementing edge of the
value in the PR(x+1) register. On the very next increment signal. (For timing details, see Figure 16-3.)
cycle, TMR2 will be reset to 00h. When this Reset
The TxGVAL bit will indicate when the Toggled mode is
occurs, a low-to-high pulse will automatically be gener-
active and the timer is counting.
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and Timer3/5/7 Gate Toggle mode is enabled by setting the
will return back to a low state until the next match. TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
Depending on TxGPOL, Timerx increments differently
necessary in order to control which edge is measured.
when TMR(x+1) matches PR(x+1). When
TxGPOL = 1, Timerx increments for a single instruction
TMRxGE
TxGPOL
TxGTM
TxG_IN
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGSPM
Cleared by Hardware on
TxGGO/ Set by Software Falling Edge of TxGVAL
TxDONE
Counting Enabled on
Rising Edge of TxG
TxG_IN
TxCKI
TxGVAL
Cleared by
TMRxGIF Cleared by Software Set by Hardware on Software
Falling Edge of TxGVAL
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by Hardware on
TxGGO/ Set by Software Falling Edge of TxGVAL
TxDONE
Counting Enabled on
Rising Edge of TxG
TxG_IN
TxCKI
TxGVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
4 1:1 to 1:16
TxOUTPS<3:0> Set TMRxIF
Postscaler
2
TxCKPS<1:0> TMRx Output
(to PWM)
TMRx/PRx
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMRx Comparator PRx
Prescaler
8 8
8
Internal Data Bus
ALMTHDY
Compare Registers
ALRMVALx ALWDHR
with Masks
ALMINSEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Hours
(24-hour format) Minutes Seconds
RTCCFG
Day
Second Hour:Minute Month Year
Day of Week
Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization;
clock prescaler is held in Reset when RTCEN = 0.
RTCEN bit
ALRMEN bit
RTCC Pin
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The CCP9 and CCP10 modules are not available on devices with 32 Kbytes of program memory
(PIC18FX5K22).
2: CCPxM<3:0> = 1011 will only reset the timer and not start AN A/D conversion on CCPx match.
Note 1: The CCP9 and CCP10 modules are not available on devices with 32 Kbytes of program memory
(PIC18FX5K22).
2: CCPxM<3:0> = 1011 will only reset the timer and not start AN A/D conversion on CCPx match.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is unimplemented and reads as ‘0’ on devices with 32 Kbytes of program memory
(PIC18FX5K22).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
19.1.1 CCP MODULES AND TIMER The assignment of a particular timer to a module is
RESOURCES determined by the timer to CCP enable bits in the
CCPTMRSx registers (see Register 19-2 and
The CCP modules utilize Timers, 1 through 8, which
Register 19-3). All of the modules may be active at
vary with the selected mode. Various timers are avail-
once and may share the same timer resource if they
able to the CCP modules in Capture, Compare or PWM
are configured to operate in the same mode
modes, as shown in Table 19-1.
(Capture/Compare or PWM) at the same time.
The CCPTMRS1 register selects the timers for CCP
modules, 7, 6, 5 and 4, and the CCPTMRS2 register
selects the timers for CCP modules, 10, 9 and 8. The
possible configurations are shown in Table 19-2 and
Table 19-3.
CCP8
CCP8 CCP9(1) CCP10(1)
Devices with 32 Kbytes
Capture/ Capture/ Capture/ Capture/
C8TSEL PWM C8TSEL PWM PWM PWM
Compare Compare C9TSEL0 Compare C10TSEL0 Compare
<1:0> Mode <1:0> Mode Mode Mode
Mode Mode Mode Mode
0 0 TMR1 TMR2 0 0 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2
0 1 TMR7 TMR4 0 1 TMR1 TMR4 1 TMR7 TMR4 1 TMR7 TMR2
1 0 TMR7 TMR6 1 0 TMR1 TMR6
1 1 Reserved(2) 1 1 Reserved(2)
Note 1: The module is not available for devices with 32 Kbytes of program memory (PIC18F65K22 and
PIC18F85K22).
2: Do not use the reserved setting.
TMR5H TMR5L
Set CCP5IF
C5TSEL0 TMR5
CCP5 Pin Enable
Prescaler and CCPR5H CCPR5L
1, 4, 16 Edge Detect
TMR1
C5TSEL0 Enable
4 TMR1H TMR1L
CCP5CON<3:0> Set CCP4IF
4
Q1:Q4
4
CCP4CON<3:0>
C4TSEL1 TMR3H TMR3L
C4TSEL0
TMR3
Enable
CCP4 Pin
Prescaler and CCPR4H CCPR4L
1, 4, 16 Edge Detect
TMR1
Enable
C4TSEL0
TMR1H TMR1L
C4TSEL1
Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2 and Table 19-3.
19.2.3 SOFTWARE INTERRUPT Switching from one capture prescaler to another may
generate an interrupt. Doing that will also not clear the
When the Capture mode is changed, a false capture
prescaler counter – meaning the first capture may be
interrupt may be generated. The user should keep the
from a non-zero prescaler.
CCP4IE bit (PIE4<1>) clear to avoid false interrupts
and should clear the flag bit, CCP4IF, following any Example 19-1 shows the recommended method for
such change in operating mode. switching between capture prescalers. This example
also clears the prescaler counter and will not generate
19.2.4 CCP PRESCALER the “false” interrupt.
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode EXAMPLE 19-1: CHANGING BETWEEN
selected by the mode select bits (CCP4M<3:0>). CAPTURE PRESCALERS
Whenever the CCP module is turned off, or the CCP CLRF CCP4CON ; Turn CCP module off
module is not in Capture mode, the prescaler counter MOVLW NEW_CAPT_PS ; Load WREG with the
is cleared. This means that any Reset will clear the ; new prescaler mode
prescaler counter. ; value and CCP ON
MOVWF CCP4CON ; Load CCP4CON with
; this value
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCP5CON<3:0>
TMR1H TMR1L 0
TMR5H TMR5L 1
C5TSEL0
0 TMR1H TMR1L
1 TMR5H TMR5L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
C4TSEL1
C4TSEL0
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR4H CCPR4L
CCP4CON<3:0>
Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2 and Table 19-3.
CCPR4L (Note 2)
EQUATION 19-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
19.4.3 SETUP FOR PWM OPERATION 3. Make the CCP4 pin an output by clearing the
appropriate TRIS bit.
To configure the CCP module for PWM operation,
using CCP4 as an example: 4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
1. Set the PWM period by writing to the PR2
5. Configure the CCP4 module for PWM operation.
register.
2. Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: If the ECCPx pin is configured as an out- EXAMPLE 20-1: CHANGING BETWEEN
put, a write to the port can cause a capture
CAPTURE PRESCALERS
condition.
CLRF CCP1CON ; Turn ECCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and ECCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
TMR3H TMR3L
Set CCP1IF
C1TSEL0
C1TSEL1 TMR3
ECCP1 Pin C1TSEL2 Enable
Prescaler and CCPR1H CCPR1L
1, 4, 16 Edge Detect
C1TSEL0 TMR1
C1TSEL1 Enable
C1TSEL2
4 TMR1H TMR1L
CCP1CON<3:0>
4
Q1:Q4
0 TMR1H TMR1L
1 TMR3H TMR3L
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR1H CCPR1L
CCP1CON<3:0>
FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
CCPR1H (Slave)
PxB Output Pin
Output TRIS
Comparator R Q Controller
PxC Output Pin
TMR2 (Note 1)
S TRIS
Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create
the 10-bit time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
Period
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section 20.4.6 “Programmable
Dead-Band Delay Mode”).
Pulse PR2 + 1
PxM<1:0> Signal 0
Width
Period
PxA Modulated
Delay(1) Delay(1)
10 (Half-Bridge) PxB Modulated
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCPxDEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 20.4.6 “Programmable Dead-Band
Delay Mode”).
FET
Driver +
PxA
-
Load
FET
Driver
+
PxB
-
V+
FET FET
Driver Driver
PxA
Load
FET FET
Driver Driver
PxB
FET QA QC FET
Driver Driver
PxA
Load
PxB
FET FET
Driver Driver
PxC
QB QD
V-
PxD
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: The output signal is shown as active-high.
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is:
(1/FOSC) • TMR2 Prescale Value.
PxA
PxB
PW
PxC
PxD PW
TON(2)
External Switch C
TOFF(3)
External Switch D
20.4.3 START-UP CONSIDERATIONS complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
When any PWM mode is used, the application
is indicated by the TMR2IF or TMR4IF bit of the PIR1
hardware must use the proper external pull-up and/or
or PIR5 register being set as the second PWM period
pull-down resistors on the PWM output pins.
begins.
Note: When the microcontroller is released from
Reset, all of the I/O pins are in the 20.4.4 ENHANCED PWM
high-impedance state. The external AUTO-SHUTDOWN MODE
circuits must keep the power switch The PWM mode supports an Auto-Shutdown mode that
devices in the OFF state until the micro- will disable the PWM outputs when an external
controller drives the I/O pins with the shutdown event occurs. Auto-Shutdown mode places
proper signal levels or activates the PWM the PWM output pins into a predetermined state. This
output(s). mode is used to help prevent the PWM from damaging
The CCPxM<1:0> bits of the CCPxCON register allow the application.
the user to choose whether the PWM output signals are The auto-shutdown sources are selected using the
active-high or active-low for each pair of PWM output ECCPxAS<2:0> bits (ECCPxAS<6:4>). A shutdown
pins (PxA/PxC and PxB/PxD). The PWM output event may be generated by:
polarities must be selected before the PWM pin output
• A logic ‘0’ on the pin that is assigned the FLT0
drivers are enabled. Changing the polarity configura-
input function
tion while the PWM pin output drivers are enabled is
not recommended since it may result in damage to the • C1 Comparator
application circuits. • C2 Comparator
The PxA, PxB, PxC and PxD output latches may not be • Setting the ECCPxASE bit in firmware
in the proper states when the PWM module is A shutdown condition is indicated by the ECCPxASE
initialized. Enabling the PWM pin output drivers at the (Auto-Shutdown Event Status) bit (ECCPxAS<7>). If
same time as the Enhanced PWM modes may cause the bit is a ‘0’, the PWM pins are operating normally. If
damage to the application circuit. The Enhanced PWM the bit is a ‘1’, the PWM outputs are in the shutdown
modes must be enabled in the proper Output mode and state.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is
present, the auto-shutdown will persist.
2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists.
3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or
auto-restart), the PWM signal will always restart at the beginning of the next PWM period.
Shutdown Event
ECCPxASE bit
PWM Activity
Normal PWM
ECCPxASE
Start of Shutdown Shutdown Cleared by PWM
PWM Period Event Occurs Event Clears Firmware Resumes
20.4.5 AUTO-RESTART MODE The module will wait until the next PWM period begins,
however, before re-enabling the output pin. This behav-
The Enhanced PWM can be configured to automatically
ior allows the auto-shutdown with auto-restart features
restart the PWM signal once the auto-shutdown condi-
to be used in applications based on current mode of
tion has been removed. Auto-restart is enabled by
PWM control.
setting the PxRSEN bit (ECCPxDEL<7>).
If auto-restart is enabled, the ECCPxASE bit will
remain set as long as the auto-shutdown condition is
active. When the auto-shutdown condition is removed,
the ECCPxASE bit will be cleared via hardware and
normal operation will resume.
PWM Period
Shutdown Event
ECCPxASE bit
PWM Activity
Normal PWM
FET
Driver +
PxA V
-
Load
FET
Driver
+
PxB V
-
V-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
20.4.7 PULSE STEERING MODE While the PWM Steering mode is active, the
CCPxM<1:0> bits (CCPxCON<1:0>) select the PWM
In Single Output mode, pulse steering allows any of the
output polarity for the Px<D:A> pins.
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on The PWM auto-shutdown operation also applies to the
multiple pins. PWM Steering mode, as described in Section 20.4.4
“Enhanced PWM Auto-shutdown mode”. An
Once the Single Output mode is selected
auto-shutdown event will only affect pins that have
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
PWM outputs enabled.
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits
(PSTRxCON<3:0>), as provided in Table 20-3.
Note: The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
00 = See STR<D:A>
01 = PA and PB are selected as the complementary output pair
10 = PA and PC are selected as the complementary output pair
11 = PA and PD are selected as the complementary output pair
bit 5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on the next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: Steering Enable bit D
1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to the port pin
bit 2 STRC: Steering Enable bit C
1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to the port pin
bit 1 STRB: Steering Enable bit B
1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to the port pin
bit 0 STRA: Steering Enable bit A
1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to the port pin
Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and
PxM<1:0> = 00.
PORT Data
0
TRIS
Note 1: Port outputs are configured as displayed when
the CCPxCON register bits, PxM<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
PWM
STRn
P1n = PWM
PWM
STRn
P1n = PWM
The Master Synchronous Serial Port (MSSP) module is 21.3 SPI Mode
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral The SPI mode allows 8 bits of data to be synchronously
devices may be serial EEPROMs, shift registers, transmitted and received simultaneously. All four
display drivers, A/D Converters, etc. The MSSP modes of SPI are supported. To accomplish
module can operate in one of two modes: communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 or
• Serial Peripheral Interface (SPI)
RD4/PSP4/SDO2
• Inter-Integrated Circuit™ (I2C™) • Serial Data In (SDIx) – RC4/SDI1/SDA1 or
- Full Master mode RD5/PSP5/SDI2/SDA2
- Slave mode (with general address call) • Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD6/PSP6/SCK2/SCL2
The I2C interface supports the following modes in
Additionally, a fourth pin may be used when in a Slave
hardware:
mode of operation:
• Master mode • Slave Select (SSx) – RF7/AN5/SS1 or RD7/SS2
• Multi-Master mode Figure 21-1 shows the block diagram of the MSSP
• Slave mode with 5-bit and 7-bit address masking module when operating in SPI mode.
(with address masking for both 10-bit and 7-bit
addressing) FIGURE 21-1: MSSP BLOCK DIAGRAM
(SPI MODE)
All members of the PIC18F87K22 family have two
Internal
MSSP modules, designated as MSSP1 and MSSP2. Data Bus
Each module operates independently of the other.
Read Write
Note: Throughout this section, generic refer-
ences to an MSSP module in any of its SSPxBUF reg
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O SDIx
signals use the generic designator ‘x’ to SSPxSR reg
indicate the use of a numeral to distinguish SDOx bit 0 Shift
a particular module when required. Control Clock
bit names are not individuated.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as inputs or outputs.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
SDOx SDIx
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDIx bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
SSPxSR to after Q2
SSPxBUF
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
SDIx
(SMP = 0) bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPxSR to
SSPxBUF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is ‘1’).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
REGISTER 21-7: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx
operating modes. See Section 21.4.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
DS39960D-page 300
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
terminates
transfer
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
CKP (SSPxCON<4>)
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDAx A7 A6 A5 X A3 X X ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
transfer
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
CKP (SSPxCON<4>)
Note 1: x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011
PIC18F87K22 FAMILY
DS39960D-page 301
FIGURE 21-10:
DS39960D-page 302
Receiving Address R/W = 1 Transmitting Data Transmitting Data
ACK ACK
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCLx held low P
sampled while CPU
responds to SSPxIF
BF (SSPxSTAT<0>)
Cleared in software Cleared in software
From SSPxIF ISR From SSPxIF ISR
SSPxBUF is written in software SSPxBUF is written in software
Clear by reading
CKP (SSPxCON<4>)
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
Bus master
terminates
SSPxIF (PIR1<3> or PIR3<7>) transfer
BF (SSPxSTAT<0>)
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
UA (SSPxSTAT<1>)
Note 1: x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
3: Note that the Most Significant bits of the address are not affected by the bit masking.
PIC18F87K22 FAMILY
DS39960D-page 303
FIGURE 21-12:
DS39960D-page 304
Clock is held low until Clock is held low until
update of SSPxADD has update of SSPxADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPxIF (PIR1<3> or PIR3<7>) transfer
BF (SSPxSTAT<0>)
PIC18F87K22 FAMILY
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
UA (SSPxSTAT<1>)
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPxADD has update of SSPxADD has Clock is held low until
taken place taken place CKP is set to ‘1’
R/W = 0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
BF (SSPxSTAT<0>)
DS39960D-page 305
PIC18F87K22 FAMILY
21.4.4 CLOCK STRETCHING Note: If the user polls the UA bit and clears it by
Both 7-Bit and 10-Bit Slave modes implement updating the SSPxADD register before the
automatic clock stretching during a transmit sequence. falling edge of the ninth clock occurs, and
if the user hasn’t cleared the BF bit by
The SEN bit (SSPxCON2<0>) allows clock stretching
reading the SSPxBUF register before that
to be enabled during receives. Setting SEN will cause
time, then the CKP bit will still NOT be
the SCLx pin to be held low at the end of each data
asserted low. Clock stretching, on the
receive sequence.
basis of the state of the BF bit, only occurs
21.4.4.1 Clock Stretching for 7-Bit Slave during a data sequence, not an address
sequence.
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the 21.4.4.3 Clock Stretching for 7-Bit Slave
ninth clock at the end of the ACK sequence, if the BF Transmit Mode
bit is set, the CKP bit in the SSPxCON1 register is The 7-Bit Slave Transmit mode implements clock
automatically cleared, forcing the SCLx output to be stretching by clearing the CKP bit after the falling edge
held low. The CKP bit being cleared to ‘0’ will assert of the ninth clock if the BF bit is clear. This occurs
the SCLx line low. The CKP bit must be set in the regardless of the state of the SEN bit.
user’s ISR before reception is allowed to continue. By
holding the SCLx line low, the user has time to service The user’s ISR must set the CKP bit before transmis-
the ISR and read the contents of the SSPxBUF before sion is allowed to continue. By holding the SCLx line
the master device can initiate another receive low, the user has time to service the ISR and load the
sequence. This will prevent buffer overruns from contents of the SSPxBUF before the master device
occurring (see Figure 21-15). can initiate another transmit sequence (see
Figure 21-10).
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the Note 1: If the user loads the contents of
ninth clock, thus clearing the BF bit, the SSPxBUF, setting the BF bit before the
CKP bit will not be cleared and clock falling edge of the ninth clock, the CKP bit
stretching will not occur. will not be cleared and clock stretching
will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The 2: The CKP bit can be set in software
user should be careful to clear the BF bit regardless of the state of the BF bit.
in the ISR before the next receive
sequence in order to prevent an overflow 21.4.4.4 Clock Stretching for 10-Bit Slave
condition. Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is
21.4.4.2 Clock Stretching for 10-Bit Slave
controlled during the first two address sequences by
Receive Mode (SEN = 1)
the state of the UA bit, just as it is in 10-Bit Slave
In 10-Bit Slave Receive mode, during the address Receive mode. The first two addresses are followed
sequence, clock stretching automatically takes place by a third address sequence, which contains the
but CKP is not cleared. During this time, if the UA bit is high-order bits of the 10-bit address and the R/W bit
set after the ninth clock, clock stretching is initiated. set to ‘1’. After the third address sequence is
The UA bit is set after receiving the upper byte of the performed, the UA bit is not set, the module is now
10-bit address and following the receive of the second configured in Transmit mode and clock stretching is
byte of the 10-bit address with the R/W bit cleared to controlled by the BF flag as in 7-Bit Slave Transmit
‘0’. The release of the clock line occurs upon updating mode (see Figure 21-13).
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx DX DX – 1
SCLx
Master Device
CKP Asserts Clock
Master Device
Deasserts Clock
WR
SSPxCON1
DS39960D-page 308
Clock is not held low
because buffer full bit is
clear prior to falling edge Clock is held low until Clock is not held low
of 9th clock CKP is set to ‘1’ because ACK = 1
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
terminates
transfer
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
CKP (SSPxCON<4>)
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
BF (SSPxSTAT<0>)
SSPxBUF is written with Dummy read of SSPxBUF Dummy read of SSPxBUF
contents of SSPxSR to clear BF flag to clear BF flag
SSPOV (SSPxCON1<6>)
SSPOV is set
because SSPxBUF is
still full. ACK is not sent.
UA (SSPxSTAT<1>)
DS39960D-page 309
PIC18F87K22 FAMILY
21.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is
SUPPORT transferred to the SSPxBUF, the BF flag bit is set
(eighth bit), and on the falling edge of the ninth bit (ACK
The addressing procedure for the I2C bus is such that
bit), the SSPxIF interrupt flag bit is set.
the first byte after the Start condition usually
determines which device will be the slave addressed by When the interrupt is serviced, the source for the
the master. The exception is the general call address interrupt can be checked by reading the contents of the
which can address all devices. When this address is SSPxBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device-specific or a general call address.
Acknowledge. In 10-Bit Addressing mode, the SSPxADD is required
The general call address is one of eight addresses to be updated for the second half of the address to
reserved for specific purposes by the I2C protocol. It match and the UA bit is set (SSPxSTAT<1>). If the gen-
consists of all ‘0’s with R/W = 0. eral call address is sampled when the GCEN bit is set,
while the slave is configured in 10-Bit Addressing
The general call address is recognized when the
mode, then the second half of the address is not
General Call Enable bit, GCEN, is enabled
necessary, the UA bit will not be set and the slave will
(SSPxCON2<7> set). Following a Start bit detect, eight
begin receiving data after the Acknowledge
bits are shifted into the SSPxSR and the address is
(Figure 21-17).
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared in Software
SSPxBUF is Read
SSPOV (SSPxCON1<6>) ‘0’
GCEN (SSPxCON2<7>)
‘1’
Internal SSPM<3:0>
Data Bus SSPxADD<6:0>
Read Write
SSPxBUF Baud
Rate
Generator
SDAx Shift
SDAx In
Clock Arbitrate/WCOL Detect
Clock
SSPxSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCLx
SSPM<3:0> SSPxADD<6:0>
SDAx DX DX – 1
BRG Decrements on
Q2 and Q4 Cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCLx
TBRG
S
Sr = Repeated Start
DS39960D-page 318
Write SSPxCON2<0> (SEN = 1), ACKSTAT in
Start condition begins SSPxCON2 = 1
From slave, clear ACKSTAT bit (SSPxCON2<6>)
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 ACK
of 10-bit Address
SDAx A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPxSTAT<0>)
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write to SSPxCON2<4>
to start Acknowledge sequence,
SDAx = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0> (SEN = 1),
begin Start condition ACK from master, Set ACKEN, start Acknowledge sequence,
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCLx S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknowledge
Set SSPxIF interrupt sequence
at end of receive
at end of Acknowledge
SSPxIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPxSTAT<4>)
Cleared in
SDAx = 0, SCLx = 1, software and SSPxIF
while CPU
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC18F87K22 FAMILY
DS39960D-page 319
PIC18F87K22 FAMILY
21.4.12 ACKNOWLEDGE SEQUENCE 21.4.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a
(SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to gen- the master will assert the SDAx line low. When the
erate an Acknowledge, then the ACKDT bit should be SDAx line is sampled low, the Baud Rate Generator is
cleared. If not, the user should set the ACKDT bit before reloaded and counts down to 0. When the Baud Rate
starting an Acknowledge sequence. The Baud Rate Gen- Generator times out, the SCLx pin will be brought high
erator then counts for one rollover period (TBRG) and the and one TBRG (Baud Rate Generator rollover count)
SCLx pin is deasserted (pulled high). When the SCLx pin later, the SDAx pin will be deasserted. When the SDAx
is sampled high (clock arbitration), the Baud Rate Gener- pin is sampled high while SCLx is high, the P bit
ator counts for TBRG; the SCLx pin is then pulled low. (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is
Following this, the ACKEN bit is automatically cleared, the cleared and the SSPxIF bit is set (see Figure 21-26).
Baud Rate Generator is turned off and the MSSP module
then goes into an inactive state (Figure 21-25). 21.4.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
21.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPxBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the occur).
contents of the buffer are unchanged (the write doesn’t
occur).
SCLx 8 9
SSPxIF
Cleared in
SSPxIF Set at Software
the End of Receive Cleared in
Software SSPxIF Set at the End
of Acknowledge Sequence
Note: TBRG = one Baud Rate Generator period.
TBRG
SCLx
SDAx ACK
P
TBRG TBRG TBRG
SCLx Brought High After TBRG
SDAx Asserted Low Before Rising Edge of Clock
to Set up Stop Condition
SDAx
BCLxIF
SDAx
SCLx
Set SEN, Enable Start SEN Cleared Automatically Because of Bus Collision,
Condition if SDAx = 1, SCLx = 1 MSSP module Reset into Idle State
SEN
SDAx Sampled Low Before
Start Condition, Set BCLxIF,
S bit and SSPxIF Set Because
BCLxIF SDAx = 0, SCLx = 1
SSPxIF and BCLxIF are
Cleared in Software
SSPxIF
TBRG TBRG
SDAx
FIGURE 21-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCLx S
SCLx Pulled Low After BRG
Time-out
SEN
Set SEN, Enable Start
Sequence if SDAx = 1, SCLx = 1
BCLxIF ‘0’
SSPxIF
SDAx = 0, SCLx = 1, Interrupts Cleared
Set SSPxIF in Software
SDAx
SCLx
RSEN
BCLxIF
Cleared in Software
S ‘0’
SSPxIF ‘0’
TBRG TBRG
SDAx
SCLx
S ‘0’
SSPxIF
PEN
BCLxIF
P ‘0’
SSPxIF ‘0’
SDAx
SCLx goes Low Before SDAx goes High,
Assert SDAx
Set BCLxIF
SCLx
PEN
BCLxIF
P ‘0’
SSPxIF ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16
0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
BRG Clock
RCxIF bit
(Interrupt)
Read
RCREGx
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
BRG Clock
ABDEN bit
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h
TRMT SPEN
BRG16 SPBRGHx SPBRGx
TX9
Baud Rate Generator TX9D
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREGx
Word 1 Word 2
BRG Output
(Shift Clock)
TXx (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
RX9
SPEN
8
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit Set by User Auto-Cleared
WUE bit(1)
RXx/DTx Line
RCxIF
Cleared due to User Read of RCREGx
Note 1: The EUSART remains in Idle while the WUE bit is set.
RXx/DTx Line
Note 1
RCxIF
Cleared due to User Read of RCREGx
SLEEP Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
Break
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)
RC7/RX1/DT1/
Pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/TX1/CK1/
Pin (TXCKP = 0)
RC6/TX1/CK1/
Pin (TXCKP = 1)
Write to
TxREG1 Reg
Write Word 1 Write Word 2
Tx1IF bit
(Interrupt Flag)
TRMT bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2
(RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA).
RC6/TX1/CK1 Pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
TXEN bit
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX1/CK1
Pin (TXCKP = 0)
RC6/TX1/CK1
Pin (TXCKP = 1)
Write to
bit, SREN
SREN bit
‘0’
CREN bit ‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0. This example is equally applicable to EUSART2
(RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA).
Positive Input
CHS<4:0>
CHSN<2:0> = 000 ADC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 23-5: ADRESL: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES3 ADRES2 ADRES1 ADRES0 ADSGN ADSGN ADSGN ADSGN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANSEL<15:8>: Analog Port Configuration bits (AN15 through AN8)(1)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
Note 1: AN15 through AN12 and AN23 to AN20 are implemented only on 80-pin devices. For 64-pin devices, the
corresponding ANSELx bits are still implemented for these channels, but have no effect.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANSEL<23:16>: Analog Port Configuration bits (AN23 through AN16)(1)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port
Note 1: AN15 through AN12 and AN23 through AN20 are implemented only on 80-pin devices. For 64-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.
The analog reference voltage is software-selectable to Each port pin associated with the A/D Converter can be
either the device’s positive and negative supply voltage configured as an analog input or a digital I/O. The
(AVDD and AVSS) or the voltage level on the ADRESH and ADRESL registers contain the result of
RA3/AN3/VREF+ and RA2/AN2/VREF- pins. VREF+ has the A/D conversion. When the A/D conversion is com-
two additional Internal Reference Voltage selections: plete, the result is loaded into the ADRESH:ADRESL
2.048V and 4.096V. register pair, the GO/DONE bit (ADCON0<1>) is
The A/D Converter can uniquely operate while the cleared and the A/D Interrupt Flag bit, ADIF (PIR1<6>),
device is in Sleep mode. To operate in Sleep, the A/D is set.
conversion clock must be derived from the A/D A device Reset forces all registers to their Reset state.
Converter’s internal RC oscillator. This forces the A/D module to be turned off and any
The output of the Sample-and-Hold (S/H) is the input conversion in progress is aborted. The value in the
into the converter, which generates the result via ADRESH:ADRESL register pair is not modified for a
successive approximation. Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure 23-4.
11111
1.024V Band Gap
11110
VDDCORE
11101 Reserved
Temperature Diode
11100
Reserved CTMU
11011
(Unimplemented)
11010
(Unimplemented)
11001
(Unimplemented)
11000
(Unimplemented)
10111
AN23(1)
12-Bit
A/D 10110
Converter AN22(1)
00100
AN4
00011
AN3
00010
AN2
00001
AN1
00000
AN0
111
Negative Input Voltage AN6
110
AN5
Reference
Voltage
VCFG<1:0>
AN2
VSS(2)
Note 1: Channels, AN15 through AN12, and AN20 through AN23, are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.
VSS
23.5 Selecting the A/D Conversion The A/D operation is independent of the state of the
CHS<3:0> bits and the TRISx bits.
Clock
Note 1: When reading the PORT register, all pins
The A/D conversion time per bit is defined as TAD. The configured as analog input channels will
A/D conversion requires 14 TAD per 12-bit conversion. read as cleared (a low level). Pins config-
The source of the A/D conversion clock is ured as digital inputs will convert an
software-selectable. analog input. Analog levels on a digitally
The possible options for TAD are: configured input will be accurately
• 2 TOSC converted.
• 4 TOSC 2: Analog levels on any pin defined as a
• 8 TOSC digital input may cause the digital input
buffer to consume current out of the
• 16 TOSC
device’s specification limits.
• 32 TOSC
• 64 TOSC
• Using the internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than
the minimum TAD. (For more information, see
Parameter 130 in Table 31-28.)
Table 23-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts
Time (Holding capacitor is disconnected)
CCH<1:0> CMPxOUT
(CMSTAT<7:5>)
CxINB 0
CxINC (2) 1
Interrupt
C2INB/C2IND (1,2) 2 CMPxIF
Logic
VBG 3
EVPOL<1:0>
CREF COE
VIN- CxOUT
Polarity
CxINA 0
VIN+ Cx Logic
CVREF 1
CON CPOL
Note 1: Comparators, 1 and 3, use C2INB as an input to the inverting terminal. Comparator 2 uses C2IND as an input to
the inverted terminal.
2: C1INC, C2INC and C2IND are all unavailable for 64-pin devices (PIC18F6XK22).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The CMPxIF bit is automatically set any time this mode is selected and must be cleared by the application
after the initial configuration.
2: Comparators, 1 and 3, use C2INB as an input to the inverting terminal. Comparator 2 uses C2IND.
3: C1INC, C2INC and C2IND are all unavailable for 64-pin devices (PIC18F6XK22).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VDD
VT = 0.6V RIC
RS
Comparator
<10k AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±100 nA
5 pF
VSS
Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare(2,3)
CON = 1, CREF = 0, CCH<1:0> = 00 CON = 1, CREF = 0, CCH<1:0> = 01
COE COE
VIN- CxINC VIN-
CxINB
VIN+ Cx VIN+ Cx
CxINA CxINA CxOUT
CxOUT
Pin Pin
Comparator CxIND > CxINA Compare(3) Comparator VIRV > CxINA Compare
CON = 1, CREF = 0, CCH<1:0> = 10 CON = 1, CREF = 0, CCH<1:0> = 11
COE COE
C2INB/ VIN-
C2IND VBG (1) VIN-
VIN+ Cx Cx
VIN+
CxINA CxOUT CxINA CxOUT
Pin Pin
Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare(2,3)
CON = 1, CREF = 1, CCH<1:0> = 00 CON = 1, CREF = 1, CCH<1:0> = 01
COE COE
Comparator CxIND > CVREF Compare(3) Comparator VIRV > CVREF Compare
CON = 1, CREF = 1, CCH<1:0> = 10 CON = 1, CREF = 1, CCH<1:0> = 11
COE COE
C2INB/ VIN- VIN-
C2IND VBG(1)
Cx VIN+ Cx
VIN+ CVREF
CVREF CxOUT CxOUT
Pin Pin
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
CVRSS = 1
VREF+
AVDD
CVRSS = 0
CVR<4:0>
CVREN R
32-to-1 MUX
32 Steps
CVREF
R
R
R
CVRSS = 1
VREF-
CVRSS = 0
PIC18F87K22
CVREF
R(1)
Module
+
Voltage RF5 CVREF Output
–
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
HLVDEN VDIRMAG
HLVDIN
Set
16-to-1 MUX
HLVDIF
HLVDEN
Internal Voltage
BOREN Reference
1.024V Typical
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF Cleared in Software
Internal Reference is Stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
IRVST TIRVST
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST
CTMUCON
EDGEN CTMUICON
EDGSEQEN
ITRIM<5:0> TGEN
EDG1SELx
EDG1POL IRNG<1:0> IDISSEN
EDG2SELx EDG1STAT CTTRIG
EDG2POL EDG2STAT Current Source
CTED1 Edge
CTMU
Control Control A/D Trigger
CTED2 Logic Current Logic
Control
ECCP2
Pulse CTPLS
ECCP1 Generator
A/D Converter Comparator 2
Input
Comparator 2 Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
6. Select the operating mode (Measurement or • The current source needs calibration to set it to a
Time Delay) with the TGEN bit. precise current.
• The circuit being measured needs calibration to
The default mode is Time/Capacitance
measure or nullify any capacitance other than that
Measurement.
to be measured.
7. Configure the module to automatically trigger
an A/D conversion when the second edge 27.4.1 CURRENT SOURCE CALIBRATION
event has occurred, using the CTTRIG bit The current source on board the CTMU module has a
(CTMUCONH<0>). range of ±60% nominal for each of three current
The conversion trigger is disabled by default. ranges. For precise measurements, it is possible to
8. Discharge the connected circuit by setting the measure and adjust this current source by placing a
IDISSEN bit (CTMUCONH<1>). high-precision resistor, RCAL, onto an unused analog
channel. An example circuit is shown in Figure 27-2.
9. After waiting a sufficient time for the circuit to
discharge, clear IDISSEN. To measure the current source:
10. Disable the module by clearing the CTMUEN bit 1. Initialize the A/D Converter.
(CTMUCONH<7>). 2. Initialize the CTMU.
11. Clear the Edge Status bits, EDG2STAT and 3. Enable the current source by setting EDG1STAT
EDG1STAT (CTMUCONL<1:0>). (CTMUCONL<0>).
12. Enable both edge inputs by setting the EDGEN 4. Issue the settling time delay.
bit (CTMUCONH<3>). 5. Perform the A/D conversion.
13. Enable the module by setting the CTMUEN bit. 6. Calculate the current source current using
I = V / RCAL, where RCAL is a high-precision
resistance and V is measured by performing an
A/D conversion.
CTMU
Current Source
A/D
Trigger
A/D Converter
ANx
A/D
RCAL MUX
/**************************************************************************/
//Setup AD converter;
/**************************************************************************/
// ADCON2
ADCON2bits.ADFM=1; // Resulst format 1= Right justified
ADCON2bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD
ADCON2bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32
// ADCON0
ADCON1bits.VCFG0 =0; // Vref+ = AVdd
ADCON0bits.VCFG1 =0; // Vref+ = AVdd
ADCON0bits.VCFG = 0; // Vref- = AVss
ADCON0bits.CHS=2; // Select ADC channel
int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
double VTot = 0;
float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs
Where:
• I is known from the current source measurement
step
• t is a fixed delay
• V is measured by performing an A/D conversion
int main(void)
{
int i;
int j = 0; //index for loop
unsigned int Vread = 0;
float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;
int main(void)
{
unsigned int Vread; //storage for reading
unsigned int switchState;
int i;
PIC18F87K22
CTMU
CTED1 EDG1
Current Source
CTED2 EDG2
Output Pulse
A/D Converter
ANX
CAD
RPR
PIC18F87K22
CTMU
CTED1 EDG1 CTPLS
Current Source
Comparator CTMUDS
CTMUI CTDIN
C2
CDELAY
CVREF
C1
External Reference
External Comparator
// Initialize CTMU
CTMUICON = 0x03;
CTMUCONHbits.CTMUEN = 1;
CTMUCONLbits.EDG1STAT = 1;
// Initialize ADC
ADCON0 = 0xE5; // Enable ADC and connect to Internal diode
ADCON1 = 0x00;
ADCON2 = 0xBE; // Right Justified
Note: The temperature diode is not calibrated or standardized; the user must calibrate the diode to their application.
Note 1: For the specifications, see Section 31.1 “DC Characteristics: Supply Voltage PIC18F87K22 Family
(Industrial/Extended)”.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
Note 1: For the memory size of the blocks, see Figure 28-6. The boot block size changes with BBSIZ0.
Note 1: This bit is read-only in normal Execution mode; it can be written only in Program mode.
2: For the memory size of the blocks, see Figure 28-6.
Note 1: For the memory size of the blocks, see Figure 28-6.
2: Enable the corresponding CPx bit to protect the block from external read operations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by
using the entire DEV<10:0> bit sequence.
WDT Enabled,
SWDTEN Disabled
WDT Controlled with
SWDTEN bit Setting
WDT Enabled only while
Device is Active, Disabled
WDT Disabled in Hardware,
SWDTEN Disabled
WDTPS<3:0> 4
Sleep
INTRC Source
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled.
2: This bit is available only when ENVREG = 1 and RETEN = 0.
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition(2)
CPU Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4 PC + 6
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
000000h
Code Memory
01FFFFh Device/Memory Size(2)
3FFFFFh
28.6.1 PROGRAM MEMORY to read. A table read instruction that executes from a
CODE PROTECTION location outside of that block is not allowed to read and
will result in reading ‘0’s. Figures 28-7 through 28-9
The program memory may be read to, or written from,
illustrate table write and table read protection.
any location using the table read and table write
instructions. The Device ID may be read with table Note: Code protection bits may only be written
reads. The Configuration registers may be read and to a ‘0’ from a ‘1’ state. It is not possible to
written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code
In normal Execution mode, the CPx bits have no direct protection bits are only set to ‘1’ by a full
effect. CPx bits inhibit external reads and writes. A block chip erase or block erase function. The full
of user memory may be protected from table writes if the chip erase and block erase functions can
WRTx Configuration bit is ‘0’. only be initiated via ICSP or an external
programmer. Refer to the device
The EBTRx bits control table reads. For a block of user programming specification for more
memory, with the EBTRx bit set to ‘0’, a table read information.
instruction that executes from within that block is allowed
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
00FFFFh
003FFFh
004000h
PC = 007FFEh TBLRD* WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0.
The TABLAT register returns a value of ‘0’.
00FFFFh
Results: Table reads are permitted within Blockn, even when EBTRBx = 0.
The TABLAT register returns the value of the data at the location, TBLPTR.
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1, 2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. Description: CLRWDT instruction resets the
If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post-
If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits, TO and
PD, are set.
GPR bank.
If ‘a’ is ‘0’ and the extended instruction Words: 1
set is enabled, this instruction operates Cycles: 1
in Indexed Literal Offset Addressing Q Cycle Activity:
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Decode No Process No
Literal Offset Mode” for details. operation Data operation
Words: 1
Example: CLRWDT
Cycles: 1
Before Instruction
Q Cycle Activity:
WDT Counter = ?
Q1 Q2 Q3 Q4 After Instruction
Decode Read Process Write WDT Counter = 00h
register ‘f’ Data register ‘f’ WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1 PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0 f 255 Operands: 0 f 255
a [0,1] a [0,1]
Operation: (f) –W),
Operation: (f) –W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None
Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched If the contents of ‘f’ are less than the
instruction is discarded and a NOP is contents of W, then the fetched
executed instead, making this a instruction is discarded and a NOP is
two-cycle instruction. executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank. If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See Note: 3 cycles if skip and followed
Section 29.2.3 “Byte-Oriented and by a 2-word instruction.
Bit-Oriented Instructions in Indexed
Q Cycle Activity:
Literal Offset Mode” for details.
Q1 Q2 Q3 Q4
Words: 1
Decode Read Process No
Cycles: 1(2) register ‘f’ Data operation
Note: 3 cycles if skip and followed
If skip:
by a 2-word instruction.
Q1 Q2 Q3 Q4
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4
operation operation operation operation
Decode Read Process No
register ‘f’ Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
operation operation operation operation Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER : If REG < W;
Before Instruction PC = Address (LESS)
If REG W;
PC = Address (HERE) PC = Address (NLESS)
W = ?
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
Before Instruction
W = A5h Example: DECF CNT, 1, 0
C = 0 Before Instruction
DC = 0
CNT = 01h
After Instruction Z = 0
W = 05h After Instruction
C = 1
DC = 0 CNT = 00h
Z = 1
Example 2:
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0
POP Pop Top of Return Stack PUSH Push Top of Return Stack
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 + k FSR2,
Operation: FSR(f) + k FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
TOS.
Cycles: 1
Q Cycle Activity: The instruction takes two cycles to
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to
literal ‘k’ Data FSR This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
Example: ADDFSR 2, 23h only on FSR2.
Words: 1
Before Instruction
FSR2 = 03FFh Cycles: 2
After Instruction Q Cycle Activity:
FSR2 = 0422h Q1 Q2 Q3 Q4
Decode Read Process Write to
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 zs 127 Operands: 0k 255
0 zd 127
Operation: k (FSR2),
Operation: ((FSR2) + zs) ((FSR2) + zd) FSR2 – 1 FSR2
Status Affected: None Status Affected: None
Encoding:
Encoding: 1110 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
Description The contents of the source register are memory address specified by FSR2.
FSR2 is decremented by 1 after the
moved to the destination register. The
addresses of the source and destination operation.
registers are determined by adding the This instruction allows users to push
7-bit literal offsets, ‘zs’ or ‘zd’, values onto a software stack.
respectively, to the value of FSR2. Both Words: 1
registers can be located anywhere in
the 4096-byte data memory space Cycles: 1
(000h to FFFh). Q Cycle Activity:
The MOVSS instruction cannot use the Q1 Q2 Q3 Q4
PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to
destination register. data destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the Example: PUSHL 08h
resultant destination address points to Before Instruction
an Indirect Addressing register, the FSR2H:FSR2L = 01ECh
instruction will execute as a NOP. Memory (01ECh) = 00h
Words: 2
After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Q Cycle Activity: Memory (01ECh) = 08h
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 – k FSR2,
Operation: FSRf – k FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified contents of the FSR2. A RETURN is then
by ‘f’. executed by loading the PC with the
Words: 1 TOS.
Cycles: 1 The instruction takes two cycles to
Q Cycle Activity: execute; a NOP is performed during the
second cycle.
Q1 Q2 Q3 Q4
Decode Read Process Write to This may be thought of as a special case
of the SUBFSR instruction, where f = 3
register ‘f’ Data destination
(binary ‘11’); it operates only on FSR2.
Words: 1
Example: SUBFSR 2, 23h Cycles: 2
Before Instruction Q Cycle Activity:
FSR2 = 03FFh Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
FSR2 = 03DCh register ‘f’ Data destination
No No No No
Operation Operation Operation Operation
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6V
5.5V
5V
3V
3V
1.8V
Note 1: FMAX = 25 MHz in 8-Bit External Memory mode. For VDD values, 1.8V to 3V,
FMAX = (VDD – 1.72)/0.02 MHz.
2: FMAX = 64 MHz in all other modes. For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz.
4V
3.75V
3.6V
PIC18F87K22 Family
3.25V PIC18F87K22 Family (Industrial Only)
(Extended) 3V
Voltage (VDD)
2.5V
1.8V
Note 1: When the on-chip voltage regulator is disabled, VDD must be maintained so that VDD 3.6V.
2: For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ±5.0 40 mV
D301 VICM Input Common Mode Voltage — — AVDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio 55 — — dB
D303 TRESP Response Time(1) — 150 400 ns
D304 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions
from VSS to VDD.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution — VDD/32 — LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
D312 VRUR Unit Resistor Value (R) — 2k —
D313 TSET Settling Time(1) — — 10 s
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.
Param
Sym Characteristics Min Typ Max Units Comments
No.
VRGOUT Regulator Output Voltage — 3.3 — V
CEFC External Filter Capacitor Value 4.7 10 — F Capacitor must be
low-ESR, a low series
resistance (< 5)
VDD/2
RL
CL Pin CL
Pin
VSS VSS
RL = 464
CL = 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF for OSC2/CLKO/RA6
OSC1
1 3 3 4 4
2
CLKO
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
20, 21
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
167
166
150
151 161
162
153
162A
155 154 163
BA0
170
ALE 170A
168
CE
OE
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
167
ALE 168
164
169
171
CE
171A
OE
165
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
A<19:16>
Address Address
BA0
166
153
150
156
151
ALE
171
CE
171A
154
WRH or
WRL
157 157A
UB or
LB
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O Pins
VDD BVDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable 36
VHLVD
VHLVD
HLVDIF
T0CKI
40 41
42
T1CKI
45 46
47 48
TMR0 or
TMR1
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
SCKx
(CKPx = 0)
78 79
SCKx
(CKPx = 1)
79 78
80
75, 76
81
SCKx
(CKPx = 0)
79
73
SCKx
(CKPx = 1)
80
78
75, 76
74
SSx
70
SCKx
(CKPx = 0) 83
71 72
78 79
SCKx
(CKP = 1)
79 78
80
75, 76 77
TABLE 31-19: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
Symbol Characteristic Min Max Units Conditions
No.
70 TSSL2SCH, SSx to SCKx or SCKx Input 3 TCY — ns
TSSL2SCL
70A TSSL2WB SSx to Write to SSPBUF 3 TCY — ns
71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns
72A (Slave mode) Single Byte 40 — ns (Note 1)
73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns
TSCL2DIL
75 TDOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
77 TSSH2DOZ SSx to SDOx Output High-Impedance 10 50 ns
78 TSCR SCKx Output Rise Time (Master mode) — 25 ns
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns
TSCL2DOV
83 TSCH2SSH, SSx after SCKx Edge 1.5 TCY + 40 — ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
70
SCKx 83
(CKPx = 0)
71 72
SCKx
(CKPx = 1)
80
75, 76 77
SDIx
MSb In bit 6 - - - - 1 LSb In
74
Note: Refer to Figure 31-3 for load conditions.
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
91 92
SDAx
In
110
109 109
SDAx
Out
91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock
400 kHz mode 0.6 — s pulse is generated
106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before
400 kHz mode 1.3 — s a new transmission can start
SCLx
91 93
90 92
SDAx
Start Stop
Condition Condition
SDAx
Out
TXx/CKx
Pin
121 121
RXx/DTx
Pin
120
122
Note: Refer to Figure 31-3 for load conditions.
TXx/CKx
Pin 125
RXx/DTx
Pin
126
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to
be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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