W2465

8K 8 CMOS STATIC RAM

GENERAL DESCRIPTION
The W2465 is a slow-speed, low-power CMOS static RAM organized as 8192 8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.

FEATURES
Low power consumption: All inputs and outputs directly TTL compatible
Active: 250 mW (max.) Three-state outputs
Standby: 100 W (max.)(LL-version) Battery back-up operation capability
250 W (max.)(L-version) Data retention voltage: 2V (min.)
Access time: 70/100 nS (max.) Available packages: 28-pin 600 mil DIP,
Single +5V power supply 330 mil SOP and 300 mil skinny DIP
Fully static operation

PIN CONFIGURATION BLOCK DIAGRAM

V DD

V SS

NC 1 28 VDD
A0
.
A12 2 27 WE DECODER
. CORE
A7 3 26 CS A12 ARRAY

A6 4 25 A8

A5 5 24 A9
CS2
CS1 I/O1
CONTROL .
A4 6 23 A11 OE DATA I/O .
WE I/O8
A3 7 22 OE

A2 8 21 A10

A1 9 20
PIN DESCRIPTION
CS

A0 10 19 I/O8
SYMBOL DESCRIPTION
I/O1 11 18 I/O7
A0A12 Address Inputs
I/O2 12 17 I/O6 I/O1I/O8 Data Inputs/Outputs
I/O3 13 16 I/O5 CS1, CS2 Chip Select Inputs
VSS I/O4 WE Write Enable Input
14 15

OE Output Enable Input

VDD Power Supply
VSS Ground
NC No Connection

Publication Release Date: April 1997

-1- Revision A8
 W2465

TRUTH TABLE
CS1 CS2 OE WE MODE I/O1I/O8 VDD CURRENT
H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD

DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 C
Operating Temperature 0 to +70 C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

Operating Characteristics
(VDD = 5V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.2 - VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -2 - +2 A
Output Leakage ILO VI/O = VSS to VDD -2 - +2 A
Current CS1 = VIH (min.) or CS2
= VIL (max.) or OE = VIH
(min.) or WE = VIL (max.)
Output Low Voltage VOL IOL = +4.0 mA - - 0.4 V
Output High Voltage VOH IOH = -1.0 mA 2.4 - - V
Operating Power IDD CS1 = VIL (max.), 70 - - 70 mA
Supply Current CS2 = VIH (min.)
I/O = 0 mA, 100 - - 60 mA
Cycle = min.
Duty = 100%
Standby Power Supply ISB CS1 = VIH (min.) or CS2 - - 3 mA
Current = VIL (max.), Cycle = min.
Duty = 100%
ISB1 CS1 VDD -0.2V LL - - 20 A
or CS2 0.2V L - - 50 A
Note: Typical characteristics are at VDD = 5 V, TA = 25 C.

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 W2465

CAPACITANCE
(VDD = 5V, TA = 25 C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.

AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0.6V to 2.4V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 100 pF, IOH/IOL = -1 mA/4 mA

AC Test Loads and Waveform

R1 1000 ohm
R1 1000 ohm
5V 5V

OUTPUT OUTPUT
5 pF
100 pF R2 R2
660 ohm Including
Including 660 ohm
Jig and
Jig and
Scope
Scope

(For TCLZ1,TCLZ2, TOLZ, TCHZ1,TCHZ2, TOHZ, TWHZ,TOW)

2.4V
90% 90%

0.6V 10% 10%

5 nS 5 nS

Publication Release Date: April 1997

-3- Revision A8
 W2465

AC Characteristics, continued
(VDD = 5V 10%, VSS = 0V, TA = 0 to 70 C)

Read Cycle
PARAMETER SYM. W2465-70 W2465-10 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time TRC 70 - 100 - nS
Address Access Time TAA - 70 - 100 nS
Chip Select Access Time CS1 TACS1 - 70 - 100 nS
CS2 TACS2 - 70 - 100 nS
Output Enable to Output Valid TAOE - 35 - 50 nS
Chip Selection to Output in Low Z CS1 TCLZ1* 5 - 10 - nS
CS2 TCLZ2* 5 - 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - 5 - nS
Chip Deselection to Output in High Z CS1 TCHZ1* - 30 - 35 nS
CS2 TCHZ2* - 30 - 35 nS
Output Disable to Output in High Z TOHZ* - 30 - 35 nS
Output Hold from Address Change TOH 10 - 10 - nS
* These parameters are sampled but not 100% tested.

Write Cycle
PARAMETER SYM. W2465-70 W2465-10 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time TWC 70 - 100 - nS
Chip Selection to End of Write CS1 TCW1 60 - 80 - nS
CS2 TCW2 60 - 80 - nS
Address Valid to End of Write TAW 60 - 80 - nS
Address Setup Time TAS 0 - 0 - nS
Write Pulse Width TWP 45 - 60 - nS
Write Recovery Time CS1 , WE TWR1 0 - 0 - nS
CS2 TWR2 0 - 0 - nS
Data Valid to End of Write TDW 30 - 40 - nS
Data Hold from End of Write TDH 0 - 0 - nS
Write to Output in High Z TWHZ* - 30 - 30 nS
Output Disable to Output in High Z TOHZ* - 30 - 30 nS
Output Active from End of Write TOW 0 - 0 - nS
* These parameters are sampled but not 100% tested.

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 W2465

TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)

TRC

Address

TAA TOH
TOH

D OUT

Read Cycle 2
(Chip Select Controlled)

CS1

TACS1 TCHZ1

CS2 TACS2

TCHZ2
TCLZ1
D OUT
TCLZ2

Read Cycle 3
(Output Enable Controlled)

TRC

Address

TAA

OE

TAOE TOH
TOLZ
CS1
TACS1 TCHZ1
TCLZ1

CS2 TACS2

TCLZ2 TCHZ2 TOHZ

DOUT

Publication Release Date: April 1997

-5- Revision A8
 W2465

Timing Waveforms, continued

Write Cycle 1

TWC

Address

TWR1

OE

TCW1
CS1

CS2 TCW2
TAW TWR2
WE TAS TWP

TOHZ
(1, 4)
D OUT
TDW TDH
D IN

Write Cycle 2
(OE = VIL Fixed)

TWC

Address

TCW1 TWR1

CS1

CS2 TCW2
TAW TWR2
TWP
WE TAS TOH

TWHZ(1, 4) (2) (3)

TOW
DOUT

TDW TDH
D IN

Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

-6-
 W2465

DATA RETENTION CHARACTERISTICS

(TA = 0 to 70 C)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT

VDD for Data Retention VDR CS1 VDD -0.2V, or 2.0 - - V
CS2 0.2V
Data Retention Current IDDDR CS1 VDD -0.2V, or LL - - 10 A
CS2 0.2V
VDD = 3V L - - 20 A
Chip Deselect to Data TCDR See data retention 0 - - nS
Retention Time waveforms
Operation Recovery Time TR TRC* - - nS
TRC* = Read Cycle Time

DATA RETENTION WAVEFORMS

DATA RETENTION MODE

VDD
VDR >
= 2V
4.5V 4.5V
TCDR TR

CS1
VIH CS1 >
= VDD - 0.2V VIH

CS2 VIL CS2 <

= 0.2V VIL

ORDERING INFORMATION
ACCESS TIME OPERATING STANDBY
PART NO. (nS) CURRENT CURRENT PACKAGE
MAX. (mA) MAX. (A)
W2465-70LL 70 70 20 600 mil DIP
W2465-10L 100 60 50 600 mil DIP
W2465S-70LL 70 70 20 330 mil SOP
W2465S-10L 100 60 50 330 mil SOP
W2465K-70LL 70 70 20 300 mil Skinny
W2465K-10L 100 60 50 300 mil Skinny
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

Publication Release Date: April 1997

-7- Revision A8
 W2465

BONDING PAD DIAGRAM

PAD NO. X Y

5 4 3 2 1 27S-2 27S-1 26 25 24 23 22
1 -226.95 1526.15
A4 A5 A6 A7 A12 VDD WE CS2 A8 A9 A11 2 -350.95 1526.15
VDD

6 21 3 -484.10 1526.15
A3
OE 4 -608.10 1526.15
5 -739.75 1526.15
6 -741.75 1315.10
7 -741.75 -1231.85
8 -741.75 -1456.30
Y
9 -610.60 -1456.30
10 -481.50 -1466.30
X 11 -343.80 -1466.30
12 -206.10 -1466.30
13S-1 -73.00 -1401.10
13S-2 -8.35 -1212.80
14 60.10 -1466.30
7 13S-2 20 15 193.30 -1466.30
A2 VSS
A10 16 332.40 -1466.30
13S-1
8 9 10 11 12
VSS
14 15 16 17 18 19 17 465.60 -1466.30
A1 A0 O0 O1 O2 03 O4 O5 O6 O7 CS1 18 603.30 -1466.30
19 738.15 -1456.30
20 740.15 -1221.45
21 740.15 1310.80
22 738.15 1526.15
23 606.50 1526.15
24 482.50 1526.15
25 349.35 1526.15
26 225.35 1526.15
27S-1 94.20 1526.15
27S-2 -50.40 1456.10

Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.

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 W2465

PACKAGE DIMENSIONS
28-pin P-DIP

Dimension in Inches Dimension in mm

Symbol
Min. Nom. Max. Min. Nom. Max.
0.210 5.33
A
0.010 0.25
A1
0.150 0.155 0.160 3.81 3.94 4.06
A2
0.016 0.018 0.022 0.41 0.46 0.56
B
0.058 0.060 0.064 1.47 1.52 1.63
B1
0.008 0.010 0.014 0.20 0.25 0.36
c
1.460 1.470 37.08 37.34
D D
0.590 0.600 0.610 14.99 15.24 15.49
28 15 E
0.540 0.545 0.550 13.72 13.84 13.97
E1
e1 0.090 0.100 0.110 2.29 2.54 2.79

L 0.120 0.130 0.140 3.05 3.30 3.56

E1 a 0 15 0 15

eA 0.630 0.650 0.670 16.00 16.51 17.02

0.090 2.29
S
Notes:
1 14
1. Dimension D Max. & S include mold flash or
E
tie bar burrs.
S
2. Dimension E1 does not include interlead flash.
c
3. Dimension D & E1 include mold mismatch and
A A2 A1 are determined at the mold parting line.
Base Plane
4. Dimension B1 does not include dambar
L Seating Plane protrusion/intrusion.
B
5. Controlling dimension: Inches.
e1 eA
a 6. General appearance spec. should be based on
B1
final visual inspection spec.

28-pin P-DIP Skinny

Dimension in Inches Dimension in mm

Symbol
Min. Nom. Max. Min. Nom. Max.
0.175 4.45
A
0.010 0.25
A1
0.125 0.130 0.135 3.18 3.30 3.43
A2
0.016 0.018 0.022 0.41 0.46 0.56
B
D 0.058 0.060 0.064 1.47 1.52 1.63
28 15
B1
0.008 0.010 0.014 0.20 0.25 0.36
c
1.388 1.400 35.26 35.56
D
0.300 0.310 0.320 7.62 7.87 8.13
E1 E
0.283 0.288 0.293 7.19 7.32 7.44
E1
0.090 0.100 0.110 2.29 2.54 2.79
e1
1 14
0.120 0.130 0.140 3.05 3.30 3.56
L
a 0 15 0 15

eA 0.330 0.350 0.370 8.38 8.89 9.40

0.055 1.40
S
Notes:
1. Dimension D Max. & S include mold flash or
tie bar burrs.
E
S 2. Dimension E1 does not include interlead flash.
Base Plane
c 3. Dimension D & E1 include mold mismatch and
A A2 A1 are determined at the mold parting line.
4. Dimension B1 does not include dambar
L
protrusion/intrusion.
Mounting Plane 5. Controlling dimension: Inches.
B e1 6. General appearance spec. should be based on
a eA
B1 final visual inspection spec.

Publication Release Date: April 1997

-9- Revision A8
 W2465

Package Dimensions, continued

28-pin SO Wide Body

Dimension in Inches Dimension in mm

Symbol
Min. Nom. Max. Min. Nom. Max.
0.112 2.85
A
0.004 0.10
A1
A2 0.093 0.098 0.103 2.36 2.49 2.62
28 15
0.014 0.016 0.020 0.36 0.41 0.51
e1
b
c 0.008 0.010 0.014 0.20 0.25 0.36

0.713 0.733 18.11 18.62

D
0.326 0.331 0.336 8.28 8.41 8.53
E
E HE
0.044 0.050 0.056 1.12 1.27 1.42
e
HE 0.453 0.465 0.477 11.51 11.81 12.12
0.028 0.036 0.044 0.71 0.91 1.12
L
L LE 0.059 0.067 0.075 1.50 1.70 1.91
Detail F 0.047 1.19
1 14 S
b y 0.004 0.10

0 10 0 10

Notes:
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
D e1
3. Dimension D & E include
. mold mold mismatch
c
and determined at the parting line.
A2 A
4. Controlling dimension: Inches.
5. General appearance spec should be based
S e
y A1 LE on final visual inspection spec.
See Detail F
Seating Plane

Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp.
No. 4, Creation Rd. III, Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
Science-Based Industrial Park, 123 Hoi Bun Rd., Kwun Tong, Winbond Microelectronics Corp.
Hsinchu, Taiwan Kowloon, Hong Kong
TEL: 852-27513100
Winbond Systems Lab.
TEL: 886-3-5770066
FAX: 886-3-5792647 FAX: 852-27552064 2730 Orchard Parkway, San Jose,
http://www.winbond.com.tw/ CA 95134, U.S.A.
Voice & Fax-on-demand: 886-2-7197006 TEL: 1-408-9436666
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

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