SPECIFICATION

Model: LMB161A



 LMB161A -2-

1. BASIC SPECIFICATIONS
1.1 Display Specifications
LCD Mode : STN Positive Transflective
Display Color : Dark Blue
Background Color : Yellow-Green
Driving Duty : 1/16 Duty
Viewing Direction : 6:00
Backlight : LED

1.2 Mechanical Specifications

Outline Dimension : 80.0(W) X 36.0(H) X 14.0(T) mm
Viewing Area : 64.6(W) X 16.0(H) mm
Number of Characters : 16 Characters X 1 Line
Character Size : 3.07 X 6.56 mm
Dot Size : 0.55 X 0.75 mm
Weight :

1.3 Block Diagram

VSS 16 COM
LCD LCD PANEL
VDD
VO Controller 16 Characters x 1 Line
RS LSI
R/W
E KS0066
or Eqv.
DB0 40 SEG

DB7

LEDA
LED Backlight
LEDK
 LMB161A -3-

1.4 Terminal Functions

Pin No. Symbol Level Function
1 VSS - Ground
2 VDD - Power Supply for Logic (+5V)
3 VO - Power Supply for LCD
Register Selection
4 RS H/L
H: Display Data L: Instruction Code
Read/Write Selection
5 R/W H/L
H: Read Operation L: Write Operation
Enable Signal. Read data when E is “H”, write
6 E H, H L
data at the falling edge of E.
7 DB0 H/L
In 8-bit mode, used as low order bi-directional
8 DB1 H/L
data bus.
9 DB2 H/L
In 4-bit mode, open these terminals.
10 DB3 H/L
11 DB4 H/L In 8-bit mode, used as high order bi-directional
12 DB5 H/L data bus.
13 DB6 H/L In 4-bit mode, used as both high and low order
14 DB7 H/L data bus.
15 LEDA -- LED Power Supply (+5V)
16 LEDK -- LED Power Supply (0v)

2. ABSOLUTE MAXIMUM RATINGS

Item Symbol Min. Max. Unit

Supply Voltage(Logic) VDD-VSS -0.3 7.0 V
Supply Voltage(LCD) VDD-VO -0.3 13.0 V
Input Voltage VI -0.3 VDD+0.3 V
Operating Temp. Topr -20 60
Storage Temp. Tstg -30 80
 LMB161A -4-

3. ELECTRICAL CHARACTERISTICS
3.1 DC Characteristics (VDD=5.0V,10%, Ta=25:)
Item Symbol Condition Min. Typ. Max. UNIT
Supply Voltage
VDD 4.5 5.0 5.5 V
(Logic)
Supply Voltage
VDD-VO -- 4.6 -- V
(LCD Drive)

Input High Voltage VIH 2.2 -- VDD V

Input Low Voltage VIL -0.3 -- 0.6 V

Output High Voltage VOH IOH=-0.2mA 2.4 -- VDD V

Output Low Voltage VOL IOL=1.2mA 0 -- 0.4 V

Supply Current
IDD VDD=5.0V -- 1.2 3.0 mA
(Logic)

3.2 Interface Timing Chart (VDD=5.0V,10%, Ta=25:)

Mode Characteristic Symbol Min. Typ. Max. Unit
E Cycle Time tC 500 -- --
E Rise/Fall Time tR, tF -- -- 20
E Pulse Width (High,Low) tW 230 -- --
Write Mode
R/W and RS Setup Time tSU1 40 -- --
Refer to fig.1 ns
R/W and RS Hold Time tH1 10 -- --
Data Setup Time tSU2 80 -- --
Data Hold Time tH2 10 -- --
E Cycle Time tC 500 -- --
E Rise/Fall Time tR, tF -- -- 20
E Pulse Width (High,Low) tW 230 --
Read Mode
R/W and RS Setup Time tSU 40 --
Refer to fig.2 ns
R/W and RS Hold Time tH 10 --
Data Output Delay Time tD -- -- 120
Data Hold Time tDH 5 -- --
 LMB161A -5-

V IH
RS V IL

t SU1 t H1

t H1
R/W
V IL V IL

tW tF

V IH V IH
E V IL V IL V IL

tR t SU2 t H2

V IH V IH
DB0~DB7 Valid Data
V IL V IL

tC

Fig.1 MPU Write Timing

V IH
RS V IL

t SU1 t H1

V IH V IH
R/W t H1

tW tF

V IH V IH
E V IL V IL V IL

tR
tD t DH

V OH V OH
DB0~DB7 Valid Data
V OL V OL

tC

Fig.2 MPU Read Timing

 LMB161A -6-

3.3 LED Backlight Characteristics (Ta=25 )

Item Symbol Condition Min. Typ. Max. UNIT

Forward Voltage Vf 3.9 4.1 4.3 V

Forward Current If Vf=4.1V -- 110 -- mA

Peak Wave Length p If=110mA -- 568 -- nm

Luminance Lv If=110mA -- 100 -- cd/m2

3.4 Power Supply

VDD

+5V VO
LCM

VR
10~20 k Ω
VSS
LEDA
+5V
LEDK
 LMB161A -7-

4. OPERATING PRINCIPLES & METHODES

4.1 Register
The LCD Controller has two 8-bit registers, the Instruction register (IR) and the data
register (DR).
The IR is a write only register to store instruction codes like Display Clear or Cursor Shift
as well as addresses for the Display Data RAM (DD RAM) or the Character Generator
RAM (CG RAM).
The DR is a read/write register used for temporarily storing data to be read/written to/from
the DD RAM or CG RAM. Data written into the DR is automatically written into DD RAM or
CG RAM by an internal operation of the display controller.
The DR is also used to store data when reading out data from DD RAM or CG RAM.
When address information is written into IR, data is read out from DD RAM or CG RAM to
DR by an internal operation. Data transfer is then completed by reading the DR.
After performing a read from the DR, data in the DD RAM or CG RAM at the next address
is sent to the DR for the next read cycle. The register select (RS) signal determines which
of these two registers is selected.

Table 4.1 Selection of Registers

RS R/W Function
0 Instruction Write operation (MPU writes instruction code to IR)
0
1 Read Busy flag (DB7) and Address Counter (DB0 ~ DB6)
0 Data Write operation (MPU writes data to DR)
1
1 Data Read operation (MPU reads data from DR)

4.2 Busy Flag (BF)

When the busy flag is high or “1” the module is performing an internal operation and the
next instruction will not be accepted. The busy flag outputs to DB7 when RS = 0 and a
read operation is performed. The next instruction must not be written until ensuring that
the busy flag is low or “0”.

4.3 Address Counter (AC)

The address counter (AC) assigns addresses to the DD RAM and the CG RAM.
When the address of an instruction is written into the IR, the address information is sent
from the IR to the AC. The selection of either DD RAM or CG RAM is also determined
concurrently by the same instruction. After writing into or reading from the DD RAM or CG
RAM the address counter (AC) is automatically increased by 1 or decreased by 1
(determined by the I/D bit in the “Entry Mode Set” command). AC contents are output to
DB0 ~ DB6 when RS = 0 and a read operation is performed.
 LMB161A -8-

4.4 Display Data RAM (DD RAM)

The Display Data RAM (DD RAM) stores the display data represented in 8-bit character
codes. Its capacity is 80 x 8 bits or 80 characters. The Display Data RAM that is not used
for the display can be used as a general data RAM.
The DD RAM address (ADD) is set in the Address Counter (AC) and is represented in
hexadecimal. The address counter can be written by using the “Set DD RAM Address”
instruction and can be read by using the “Read Busy Flag and Address” instruction. In
each case, data bits DB0-DB6 represent the DD RAM address. In the read operation, bit
DB7 represents the “Busy Flag”.

MSB LSB
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Relations between DD RAM addresses and positions on the liquid crystal display are
shown below.
Display
Position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DD
RAM 00H 01H 02H 03H 04H 05H 06H 07H 40H 41H 42H 43H 44H 45H 46H 47H
Addr.

When display shift operation is performed, the DD RAM address moves as follows:

For left shift:

Display
Position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DD
RAM 01H 02H 03H 04H 05H 06H 07H 08H 41H 42H 43H 44H 45H 46H 47H 48H
Addr.

For right shift:

Display
Position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DD
RAM 27H 00H 01H 02H 03H 04H 05H 06H 67H 40H 41H 42H 43H 44H 45H 46H
Addr.
 LMB161A -9-

4.5 Character Generator ROM (CG ROM)

The Character Generator ROM (CG ROM) generates 5 x 7 dot or 5 x 10 dot character
patterns from 8-bit character codes. It can generate up to 192 types of 5x7 dot character
patterns and 32 types of 5x10 dot character patterns. Table 4.3 shows the relation
between character codes and character patterns of the standard character font.

4.6 Character Generator RAM (CG RAM)

The CG RAM is a 64 x 8 bit RAM in which the user can program custom character
patterns. With 5 x 7 dots, 8 types of character patterns can be written and with 5 x 10 dots
4 types of character patterns can be written. To write previously programmed characters
from the CG RAM to the DD RAM, character codes 00H through 07H are used. (See
character font Table 4.3). Unused CG RAM locations can be used for general purpose
RAM.
The relationship between CG RAM address and data and the displayed character is
shown in Tables 4.2

To program a 5 x 7 character pattern into the CG RAM location (for example, character
code 01H), the following steps should be taken.
A. Use the “Set CG RAM address” command to position the CG RAM pointer to the 1st
row of character code 01H (CG RAM address=48H).
B. Use the “Write Data to CG or DD RAM” Command to write the top row of the custom
character (Only lower 5-bit of character pattern data is valid).
C. The CG RAM address is automatically increased if the I/D bit is set in the “Entry Mode
Set” command. When this is the case, return to step B until all rows of the character are
written.
D. After writing all 7 rows of data, use the “Set DD RAM address” command to return the
address counter to a DD RAM location.
E. To display the custom character written above, use the “Write Data to CG or DD RAM”
command with the data being 01H to display the character in the DD RAM address.
 LMB161A - 10 -

Table 4.2 Relation between CG RAM address, character codes (DD RAM) and character
patterns (5x7 dots)

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Notes:
1. Character code bits 0~2 correspond to CG RAM address bit 3~5 (3 bits: 8 types).
2. CG RAM address bits 0~2 designate the line position within a character pattern. The
8th line is the cursor position and display is determined by the logical OR of the 8th line
and the cursor. Maintain the 8th line data, corresponding to the cursor display position,
in the “0” state for cursor display. When the 8th line data is “1”, bit 1 lights up regardless
of cursor existence.
3. Character pattern row positions correspond to CG RAM data bits 0~4 as shown in the
above (bit 4 being at the left end). Since CG RAM data bits 5~7 are not used for display,
they can be used for the general data RAM as memory elements still exit.
4. As shown in Table 4.2, CG RAM character patterns are selected when character code
bits 4~7 are all “0”. However as character code bit 3 is an ineffective bit, the “A” in the
character pattern example is selected by character code “00H” or “08H”.
5. “1” for CG RAM data corresponds to selected pixels and “0” for non-selected.
 LMB161A - 11 -

Table 4.3 CGROM Character Code Table

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5. MPU INTERFACE
5.1 General
(1). The LCD controller can be operated in either 4 or 8 bits mode. Instructions/Data are
written to the display using the signal timing characteristics found in section 3.2.
When operating in 4-bit mode, data is transferred in two 4-bit operations using data bits
DB4~DB7. DB0~DB3 are not used. When using 4-bit mode, data is transferred twice
before the instruction cycle is complete. The higher order 4 bits (contents of DB4~DB7
when interface data is 8 bits long) is transferred first, then the lower order 4 bits (contents
of DB0~DB3 when interface data is 8 bits long) is transferred. Check the busy flag after
4-bit data has been transferred twice (one instruction). A 4-bit two operation will then
transfer the busy flag and address counter data.
(2). When operating in 8-bit mode, data is transferred using the full 8-bit bus DB0~DB7.

5.2 Initialization
5.2.1 Initialization by the Internal Reset Circuit
The display can be initialized using the internal reset circuit when the power is turned on.
The following instructions are executed in initialization. The busy flag (BF) is kept in busy
state until initialization ends. The busy flag will go active 10ms after Vcc rises to 4.5V.
(1). Display Clear
(2). Function set:
DL = 1 : 8 bit interface operation
N = 0 : 1 - line display
F = 0 : 5 x 7 dot character font
(3). Display ON/OFF Control:
D = 0 : Display OFF
C = 0 : Cursor OFF
B = 0 : Blink OFF
(4). Entry Mode Set
I/D = 1 : +1 (Increment Mode)
S = 0 : No Display Shift operation
If the internal power supply reset timing cannot be met (0.1ms<trcc<10ms), the internal
reset circuit will not operate normally and initialization will not be performed. In this case,
the display must be initialized by software.

5.2.2 Software Initialization

Although software initialization is not mandatory, it is recommended that this procedure
always be performed. When the internal power supply reset timing cannot be met, then
the display must be initialized using one of the following procedures.
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(1). 8-Bit Initialization:

Power on

Wait for more than 30ms

after VDD rises to 4.5V.

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 N F X X

Wait for more than 39 s

Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

Wait for more than 39 s

Display Clear

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

Wait for more than 1.53ms

Entry Mode Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 1 I/D SH

End of initialization
 LMB161A - 14 -

(2). 4-Bit Initialization:

Power on

Wait for more than 30ms

after VDD rises to 4.5V.

Function Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X
0 0 0 0 1 0 X X X X
0 0 N F X X X X X X

Wait for more than 39 s

Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 1 D C B X X X X

Wait for more than 39 s

Display Clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 0 0 1 X X X X

Wait for more than 1.53ms

Entry Mode Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 1 I/D SH X X X X

End of initialization
 LMB161A - 15 -

5.3 Connection with 8051 Family MPU

8051 KS0066
8
P0.0~P0.7 DB0~DB7
8 A0
RS
74LS373 A1
R/W

Y0
3
P2.5~P2.7 74LS138

/RD E
/WR

a. Application Circuit 1

8051 KS0066
8
P1.0~P1.7 DB0~DB7

P3.0 RS
P3.1 R/W
P3.2 E

b. Application Circuit 2
 LMB161A - 16 -

6. DISPLAY CONTROL INSTRUCTION

Table 6.1 Instructions

Instruction code Execution time
Instruction Description
(fosc=270KHz)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear Clears entire display and sets
0 0 0 0 0 0 0 0 0 1 1.53ms
Display DDRAM address to 00H.
Sets DDRAM address to 00H in
Return AC and returns shifted display to
0 0 0 0 0 0 0 0 1 - 1.53ms
Home its original position. The contents
of DDRAM remain unchanged.
Sets cursor move direction and
Entry Mode enable the shift of entire display.
0 0 0 0 0 0 0 1 I/D SH 39 s
Set These operations are performed
during data write and read.
Set ON/OFF of entire display (D),
Display ON/
0 0 0 0 0 0 1 D C B cursor ON/OFF(C), and blinking 39 s
OFF Control
of cursor position character(B).
Cursor or Moves cursor and shifts display
Display 0 0 0 0 0 1 S/C R/L - - without changing DDRAM 39 s
Shift contents.
Sets interface data length (DL:
8-bit/4-bit), numbers of display
Function Set 0 0 0 0 1 DL N F - - 39 s
line (N: 2-line/1-line), and display
font type (F: 5x11dots/5x8dots)
Set CGRAM Set CGRAM address in address
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 39 s
Address counter.
Set DDRAM Set DDRAM address in address
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 39 s
Address Counter.
Reads busy flag (BF) indicating
Read Busy
internal operation is being
Flag and 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 s
performed and reads address
Address
counter contents.
Write data
Write data into internal RAM
to CG or DD 1 0 D7 D6 D5 D4 D3 D2 D1 D0 43us
(DDRAM/CGRAM).
RAM
Read data Read data from internal RAM
from CG or 1 1 D7 D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM). 43us
DD RAM

- : don’t care

Note: 1. Make sure to check the busy flag before sending the instruction to the display. If
the busy flag is not checked, the time between first and next instruction must be
longer than the instruction execution time list in the Table 6.1.
2. After execution of CG RAM/DD RAM data write or read instruction, the RAM
address counter is increased or decreased by 1. The RAM address counter is
updated after the busy flag turns off.
 LMB161A - 17 -

6.1 Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

Clear all the display data by writing the space code “20H” to all DD RAM addresses, and
set DD RAM address to “00H” into address counter. Returns cursor to the original position,
namely, brings the cursor to the upper left end of the display. The execution of clear
display instruction sets entry mode to increment mode (I/D = 1).

6.2 Return Home

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 1 -

Sets the DD RAM address “00H” in address counter. Return display to its original position
if it was shifted. DD RAM contents do not change. The cursor or the blink moves to the
upper left end of the display. Contents of DD RAM remain unchanged.

6.3 Entry Mode Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 1 I/D SH

Sets the move direction of cursor and display.

I/D: Increases (I/D = 1) or decreases (ID = 0) the DD RAM address by 1 when a character
code is written into or read from the DD RAM.
The cursor or blink moves to the right when increased by 1 and to the left when
decreased by 1. The same applies to writing and reading the CG RAM.
S: Shifts the entire display when S = 1; shifts to the left when I/D = 1 and to the right
when I/D = 0. Thus it looks as if the cursor stands still and only the display seems to
move. The display does not shift when reading from DD RAM or writing/reading
into/from CG RAM.
When S = 0, the display does not shift.

6.4 Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 1 D C B
 LMB161A - 18 -

Controls the display ON/OFF status, Cursor ON/OFF and Cursor Blink function.
D: The entire display is ON when D = 1 and OFF when D = 0. The display data remains in
the DD RAM when display is OFF, it can be displayed immediately by setting D = 1.
C: The cursor displays when C = 1 and does not display when C = 0. The cursor is
displayed on the 8th line when 5x7 dots character font has been selected.
B: The character indicated by the cursor blinks when B = 1. The blink is displayed by
switching between all “High” data and display characters at 0.4 sec intervals.
The cursor and the blink can be set to display simultaneously.
When B = 0, the blink is off.

6.5 Cursor or Display Shift

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 S/C R/L - -

Shifts the cursor position or display to the right or left without writing or reading display
data. This function is used to correct or search for the display.
Note that the display shift is performed simultaneously in all lines.
The contents of address counter do not change when display shift is performed.

Table 6.2 Shift Patterns According to S/C and R/L Bits

S/C R/L Operation
0 0 Shifts cursor position to the left (AC is decreased by 1)
0 1 Shifts cursor position to the right (AC is increased by 1)
1 0 Shifts the entire display to the left, cursor follows the display shift.
1 1 Shifts the entire display to the right, cursor follows the display shift.

6.6 Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 DL N F - -

Sets the interface data length, the number of lines, and character font.
DL: Sets interface data length. Data is sent or received in 8-bit length (DB7 ~ DB0) when
DL = 1, and in 4-bit length (DB7 ~ DB4) when DL = 0. When the 4-bit length is
selected, data must be sent or received twice.
N: Sets the number of lines
 LMB161A - 19 -

N = 0 : 1 line display (1/8 duty)

N = 1 : 2 line display (1/16 duty)
F: Sets character font.
F = 0 : 5 x 7 dots
F = 1 : 5 x 10 dots
Note: Perform the function at the head of the program before executing all instructions
(except Busy flag/address read).

6.7 Set CG RAM Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Sets the CG RAM address to the address counter. Data is then written/read to/from the
CG RAM.

6.8 Set DD RAM Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Sets the DD RAM address to the address counter. Data is then written/read to/from the
DD RAM.
When in 1-line display mode (N = 0), DD RAM address is from “00H” to “4FH”.
When in 2-line display mode (N = 1), DD RAM address corresponding to 1st line and 3rd
line of the display is from “00H” to “27H”; the address corresponding to 2nd and 4th line of
the display is from “40H” to “67H”.

6.9 Read Busy Flag & Address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Reads the busy flag (BF) and value of the address counter (AC). BF = 1 indicates that
internal operation is in progress and the next instruction will not be accepted until BF is set
to “0”. The BF status should be checked before each write operation. At the same time the
value of the address counter is read out. The address counter is used by both CG and DD
RAM and its value is determined by the previous instruction.
 LMB161A - 20 -

6.10 Write Data to CG or DD RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

Writes binary 8-bit data to the CG or DD RAM.

The previous address set instruction (CG RAM address set or DD RAM address set)
determines whether the CG or DD RAM is to be written. After a write the address is
automatically increased or decreased by 1, according to the entry mode. The entry mode
also determines display shift.

6.11 Read Data from CG or DD RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

Reads binary 8-bit data from the CG RAM or DD RAM.

The previous address set instruction (CG RAM address set or DD RAM address set)
determines whether the CG or DD RAM is to be read. Before entering the read instruction,
you must execute either the CG RAM or DD RAM address set instruction. If you don’t, the
first read data will be invalidated. If RAM data is read several times without RAM address
instruction set before read operation, the correct RAM data can be obtained from the
second read. The “address set” instruction need not be executed just before the “read”
instruction when shifting the cursor by cursor shift instruction (when reading DD RAM).
The cursor shift instruction operation is the same as that of the DD RAM address set
instruction.
After a read the address is automatically increased or decreased by 1, according to the
entry mode; however, display shift is not executed no matter what the entry mode is.
Note: The address counter (AC) is automatically increased or decreased by 1 after a
“write” instruction to either CG RAM or DD RAM. RAM data selected by the AC
cannot then be read out even if “read” instructions are executed.
The conditions for correct data read out are: (a) Execute either the address set instruction
or cursor shift instruction (only with DD RAM) or (b) The execution of the “read data”
instruction from the second time when the read instruction is performed multiple times in
serial.
 LMB161A - 21 -

7. ELECTRO OPTICAL CHARACTERISTICS (Ta=25 )

Item Symbol Condition Min. Typ. Max. Unit Note

View Angle 2- 1 K≥2 , θ=0 -- 80 -- Deg Note1, Note2

Contrast K =0 ,θ=0 3 -- -- -- Note3

tr (rise) =0 ,θ=0 -- 250 -- ms

Response Time Note3
tf (fall) =0 ,θ=0 -- 250 -- ms

Note1: Definition of Viewing Angle ,

Z( φ =0 ) Top

φ2

Y( θ =180 , φ =-90 ) φ1

X X'
θ

Bottom

Y'( θ =0 , φ =+90 ) 

Note2: Definition of viewing Angle Range: 1, 2

2.0

φ1 φ2
Viewing Angle
 LMB161A - 22 -

Note3: Definition of Contrast

B1

Brightness

B2

Driving Voltage

Brightness of non-selected dot (B1)

Contrast=
Brightness of selected dot (B2)

Note4: Definition of Response Time

Non-selective Selective state Non-selective

state state
Brightness

90%
100%

10%

tr tf Time
 LMB161A - 23 -

8. DIMENSIONAL OUTLINE
 LMB161A - 24 -

9. PRECAUTIONS FOR USE OF LCD MODULE

9.1 Handing Precautions
1) The display panel is made of glass. Do not subject it to a mechanical shock by
Dropping it from a high place, etc.
2) If the display panel is damaged and the liquid crystal substance inside it leaks out,
Be sure not to get any in your mouth. If the substance comes into contact with your
Skin or clothes, promptly wash it off using soap and water.
3) Do not apply excessive force on the surface of display or the adjoining areas of
LCD module since this may cause the color tone to vary.
4) The polarizer covering the display surface of the LCD module is soft and easily
Scratched. Handle this polarizer carefully.
5) If the display surface of LCD module becomes contaminated, blow on the
Surface and gently wipe it with a soft dry cloth. If it is heavily contaminated, moisten
Cloth with one of the following solvents.
Isopropyl alcohol
Ethyl alcohol
Solvents other than those mentioned above may damage the polarizer.
Especially, do not use following.
Water
Ketone
Aromatic Solvents
6) When mounting the LCD module make sure that it is free of twisting, warping, and
Distortion. Distortion has great influence upon display quality. Also keep the
Stiffness enough regarding the outer case.
7) Be sure to avoid any solvent such as flux for soldering never stick to Heat-Seal.
Such solvent on Heat-Seal may cause connection problem of heat-Seal and TAB.
8) Do not forcibly pull or bend the TAB I/O terminals.
9) Do not attempt to disassemble or process the LCD module.
10) NC terminal should be open. Do not connect anything.
11) If the logic circuit power is off, do not apply the input signals.
12) To prevent destruction of the elements by static electricity, be careful to maintain
an optimum work environment.
Be sure to ground the body when handling the LCD module.
Tools required for assembly, such as soldering irons, must be properly
grounded.
To reduce the amount of static electricity generated, do not conduct assembly
and other work under dry conditions.
The LCD module is coated with a film to protect the display surface. Exercise
care when peeling off this protective film since static electricity may be
generated.
9.2 Storage Precautions
1) When storing the LCD module, avoid exposure to direct sunlight or to the light of
Fluorescent lamps and high temperature/high humidity. Whenever possible, the
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LCD module should be stored in the same conditions in which they were shipped
from Our company.
2) Exercise care to minimize corrosion of the electrode. Corrosion of the electrodes is
accelerated by water droplets or a current flow in a high humidity environment.
9.3 Design Precautions
1) The absolute maximum ratings represents the rated value beyond which LCD
module can not exceed. When the LCD modules are used in excess of this rated
value, their operating characteristics may be adversely affected.
2) To prevent the occurrence of erroneous operation caused by noise, attention must
be paid to satisfy VIL, VIH specification values, including taking the precaution of
using signal cables that are short.
3) The liquid crystal display exhibits temperature dependency characteristics. Since
recognition of the display becomes difficult when the LCD is used outside its
designated operating temperature range, be sure to use the LCD within this range.
Also, keep in mind that the LCD driving voltage levels necessary for clear displays
will vary according to temperature.
4) Sufficiently notice the mutual noise interference occurred by peripheral devices.
5) To cope with EMI, take measures basically on outputting side.
6) If DC is impressed on the liquid crystal display panel, display definition is rapidly
deteriorated by the electrochemical reaction that occurs inside the liquid crystal
display panel. To eliminate the opportunity of DC impressing, be sure to maintain
the AC characteristics of the input signals sent to the LCD Module.
9.4 Others
1) Liquid crystals solidify under low temperatures (below the storage temperature
range) leading to defective orientation or the generation of air bubbles (black or
white).
Air bubbles may also be generated if the LCD module is subjected to a strong
shock at a low temperature.
2) If the LCD modules have been operating for a long time showing the same display
patterns, the display patterns may remain on the screen as ghost images and a
slight contrast irregularity may also appear. A normal operating status can be
regained by suspending use for some time. It should be noted that this
phenomenon does not adversely affect performance reliability.
3) To minimize the performance degradation of the LCD modules resulting from
destruction caused by static electricity, etc., exercise care to avoid touching the
following sections when handling the module:
Terminal electrode sections.
Part of pattern wiring on TAB, etc.