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SATISH KASHYAP - A First Course On VLSI Design and CAD Video Lectures by IIT Professors

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The document discusses video lectures from IIT professors on VLSI design and CAD tools. It covers various topics related to VLSI design and uses tools like Verilog for logic synthesis.

Topics covered include MOSFET fundamentals, digital CAD, amplifiers, op amps, low power design, verification, and physical design automation among others.

Tools mentioned that are used for VLSI design and CAD include Verilog for logic synthesis and behavioral modeling, and analog behavioral modeling with Verilog-A.

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A First Course on VLSI Design and CAD video lectures by


IIT Professors
Video Lecture Series from IIT Professors :

A First Course on VLSI Design and CAD Tools


by Lecturers & Professors (IIT KGP)

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These Videos are taught by Many Professors and Lecturers from IIT
Kharagpur.....
Essential for every VLSI and Embedded Systems P.G. student.

Nov18
Johannesburg

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Lecture - 1- introduction
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Lecture - 2 introduction - overview


Lecture - 3 MOSFET fundamentals and device modeling
Lecture - 4 active device modeling - HFET
Lecture - 5 introduction to digital cad
Lecture - 6 single stage amplifier
Lecture - 7 current mirror
Lecture - 8 communication circuits
Lecture - 10-current and voltage reference

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Lecture - 11-ADIC
Lecture - 12 digital vlsi design using verilog

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Lecture - 13 digital vlsi design using verilog


Lecture - 14 logic synthesis using verilog

1,892,10

Lecture - 15 logic synthesis - tools perspective


Lecture - 17 op amp
Lecture - 18 op amp

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Lecture - 19 low power vlsi design


Lecture - 20 simulation based verification
Lecture - 21 assertions as applied to design verification
Lecture - 22 switch capacitor amplifier
Lecture - 24 high level synthesis
Lecture - 26 bipolar design in vlsi

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Lecture - 27 input output buffer latchup, electro static discharge


Lecture - 28 physical design automation
Lecture - 29 physical design automation
Lecture - 30 introduction to analog cad
Lecture - 31 introduction to analog behavioral modeling and verilog-A
Lecture - 32 introduction to op amp macro modeling
Lecture - 33 static timing analysis
Lecture - 34 static timing analysis
Lecture - 35a. RF and microwave passives
Lecture - 35b RF and microwave passives
Lecture - 36 signal integrity
Lecture - 37 algorithms for timing analysis
Lecture - 38 introduction to formal verification

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Lecture - 39 introduction to FPGA


Lecture - 41 low drop out voltage regulators
Lecture - 42 testing and DFT
Lecture - 45 design of buck converter
Lecture - 46 basic rf integrated circuit building blocks

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Labels: iit videos

2 comments:
umar July 11, 2012 at 2:44 AM
For lecture 29, there is no audio. So can you please put an audio and again upload it.
Reply

Skype August 8, 2012 at 6:32 AM


For lecture 29, there is no audio. So can you please put an audio and again upload it.
Reply

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