MBIST Basics
MBIST Basics
MBIST Basics
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EE141 VLSI Test Principles and Architectures
Memory BIST
BRAINS: BIST generator
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EE141 VLSI Test Principles and Architectures
Marking
Post-BI Test
Burn-In (BI)
Pre-BI Test
Final Test
Visual Inspection
QA Sample Test
Shipping
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EE141 VLSI Test Principles and Architectures
Functional Test
Device characterization
Failure analysis
Fault modeling
Simple but effective (accurate & realistic?)
Address latch
Column decoder
Refresh logic
Row decoder
Write driver
Sense amplifiers
Data register
Data out
Data in
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EE141 VLSI Test Principles and Architectures
New fault models are being proposed to cover new defects and failures in modern memories:
New process technologies New devices
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SRAM
Leakage Fault
Static Data Losses---defective pull-up
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EE141 VLSI Test Principles and Architectures
{c ( w 0 ); c ( r 0 ); c ( w1); c ( r1)}
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EE141 VLSI Test Principles and Architectures
1 0 1 0 1 0 1 0 1
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BC
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BC
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EE141 VLSI Test Principles and Architectures
Detects all faults as GALPAT, except for some CFs Complexity is 4N**1.5.
1 1 1 1
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{ (w0); (r0, w1, r1); (r1, w0, r0); (r0, w1, r1); (r1, w0, r0)}
Parametric (12NlogN): for Read access time
2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit Repeat T2~T5 for each address bit GALPAT---all 2-address sequences
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EE141 VLSI Test Principles and Architectures
1 0 0 1 0
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{ ( w0); ( r 0, w1, r1); ( r1, w0, r 0); ( w1); ( r1, w0, r 0); ( r 0, w1, r1)}
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EE141 VLSI Test Principles and Architectures
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EE141 VLSI Test Principles and Architectures
{c ( w0); (r0, w1); (r1, w0); c (r0); (r0, w1); (r1, w0);c (r0)}
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EE141 VLSI Test Principles and Architectures
March Tests: March CMarch CRemove the redundancy in March C Also for AF, SAF, TF, & all CFs Optimal (irredundant)
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EE141 VLSI Test Principles and Architectures
Word-Oriented Memory
A word-oriented memory has Read/Write operations that access the memory cell array by a word instead of a bit. Word-oriented memories can be tested by applying a bit-oriented test algorithm repeatedly with a set of different data backgrounds:
The repeating procedure multiplies the testing time
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EE141 VLSI Test Principles and Architectures
Cocktail-March Algorithms
Motivation:
Repeating the same algorithm for all logm+1 backgrounds is redundant so far as intra-word coupling faults are concerned Different algorithms target different faults.
Approaches:
1. Use multiple backgrounds in a single algorithm run 2. Merge and forge different algorithms and backgrounds into a single algorithm
March-CW
Algorithm:
March C- for solid background (0000) Then a 5N March for each of other standard backgrounds (0101, 0011):
Results:
Complexity is (10+5logm)N, where m is word length and N is word count Test time is reduced by 39% if m=4, as compared with extended March CImprovement increases as m increases
Ref: Wu et al., IEEE TCAD, 04/02
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EE141 VLSI Test Principles and Architectures
Port Faults:
Stuck-open fault (SOF) Address decoder fault (AF) Multi-port fault (MPF)
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EE141 VLSI Test Principles and Architectures
BLA 3 1 2
BLA
WLA WLA
WLB WLB
BLB
EE141 VLSI Test Principles and Architectures
BLB
BLB
BLB
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Port A
Address 1
Cell 1
Address 1
Cell 1
Cell 2 Cell 3
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EE141 VLSI Test Principles and Architectures
Faulty
Cell
Cell Cell
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EE141 VLSI Test Principles and Architectures
/* Single-cell fault */
# CFst <0;s/1> AGR := v0 SPT := * /* All other cells are suspects */ VTM := r0 RCV := w1
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EE141 VLSI Test Principles and Architectures
RAMSES
Complexity is N**2
For each test operation { If op is AGR then mark victim cells; If op is RCV then release victim cells; If op is VTM then report error; }
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EE141 VLSI Test Principles and Architectures
RAMSES Algorithm
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EE141 VLSI Test Principles and Architectures
Template Set
Exhaustive generation: complexity is very high, e.g., 6.7 million templates when N = 9 Heuristics should be developed to select useful templates
T(1N) (w)
T(2N) T(3N)
(w)(w)
(wr)
(w)(r)
(ww)(w) (wrw)
TAGS Procedure
1. 2. 3. 4. 5. 6. 7.
Initialize test length as 1N, T(1N) = {(w)}; Increase test length by 1N: apply generation options; Apply filter options; Assign address orders and data backgrounds; Fault simulation using RAMSES; Drop ineffective tests; Repeat 2-6 using the new template set until constraints met;
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EE141 VLSI Test Principles and Architectures
Template Generation/Filtering
Generation heuristics:
(r) insertion (r), (r) expansion (w) insertion (w), (w) expansion
Filtering heuristics:
Consecutive read: (rr) Repeated read: (r)(r) Tailing single write: (w)
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Word-Oriented TAGS
1. 2. 3. 4.
Construct bit-oriented test algorithms Generate initial Cocktail-March: Assign each data background to the test in Step 1a cascade of multiple March algorithms Optimize the Cocktail-March (!P1) /* non-solid backgrounds */ Optimize the Cocktail-March (P1) /* solid background */
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EE141 VLSI Test Principles and Architectures
b) c)
Generate a new CocktailMarch test by replacing the March algorithm having P1 as its background with a shorter one from the test set generated in Step 1. Repeat with every test candidate for other backgrounds. Run RAMSES for the new CocktailMarch. Repeat 4(a) and 4(b) for all candidate test algorithms from 3(d) until the FC drops and cannot be recovered by any other test algorithm of the same length or by selecting other candidates.
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Can it support fault location and redundancy repair? Can it support BI? Can it support on-chip redundancy analysis and repair? Does it allow characterization test as well as mass production test? Can it really replace ATE (and laser repair machine)?
Programmability, speed, timing accuracy, threshold range, parallelism, etc.
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EE141 VLSI Test Principles and Architectures
Hardwired BIST
Fast Compact
Hybrid
Interface
Serial (scan, 1149.1) Parallel (embedded controller; hierarchical)
Pattern Generator
RAM
Go/No-Go
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BIST Architecture
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Controller
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Sequencer
D Q
Combination Logic #0 Combination Logic #1 Row Address Counter Column Address Counter Control Counter
D Q
D Q
D Q
BIST Controller
D Q
D Q
eDRAM
D Q
D Q
MCK
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EE141 VLSI Test Principles and Architectures
Sequencer States
Disable BIST_EN=low SEQ_EN=low All outputs and flags are high-z Idle& Wait BIST_EN=high SEQ_EN=low All outputs and flags are in precharged state
Reset/Initiate BIST_EN=high SEQ_EN=high All outputs and flags seted to known state
CBR Refresh
NON_EDO A WD
NON_EDO B RDWD'
EDO_ROW
EDO_ROW
EDO_ROW
Self Refresh
EDO_COL 0 WD
EDO_COL 1 RDWD'
EDO_COL 2 RDWD'RD'
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EE141 VLSI Test Principles and Architectures
3. 4.
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EE141 VLSI Test Principles and Architectures
RAM BIST compiler is the trend BRAINS (BIST for RAM in Seconds)
Proposed BIST Architecture Memory Modeling Command Sequence Generation Configuration of the Proposed BIST
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Controller
Sequencer
TPG
Controls
Test Collar
Comparator
Address D Q
Memory
Normal Access
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EE141 VLSI Test Principles and Architectures
address
TPG
RAM
The test pattern generator (TPG) translates high-level memory commands to memory input signals. Four parameters to model a memorys I/Os:
Type: input, output, and in/out Width Latency: number of clock cycles the TPG generates the physical signal after it receives a command from the sequencer Packet_length: number of different signal values packed within a single clock cycle
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sequencer
Ram Core C
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MBS
MSI
MBO
MRD
MSO
MBC MBR
MCK
Controller
TPG
TPG
TPG
TPG
TPG
TPG
RAM
RAM
RAM
RAM
RAM
RAM
Source: ATS01
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EE141 VLSI Test Principles and Architectures
BRAINS GUI
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EE141 VLSI Test Principles and Architectures
Supported Memories
The Built-In Memory List
DRAM
EDO DRAM SDRAM DDR SDRAM
SRAM
Single-Port Synchronous SRAM Single-Port Asynchronous SRAM Two-Port Synchronous Register File Dual-Port Synchronous SRAM Micron ZBT SRAM
Examples
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EE141 VLSI Test Principles and Architectures
Area Overhead
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Concluding Remarks
BIST is considered the best solution for testing embedded memories:
Low cost Effective and efficient