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    ATPG Tool Flow

    Uploaded by

    Adhi Suruli
    This document outlines the typical ATPG (Automatic Test Pattern Generation) flow using the Tessent ATPG tool. It describes the key inputs needed, including the design netlist, ATPG library, and setup file. It then details the steps to invoke Tessent, specify clock signals, EDT (Enhanced Design for Testability) options, and add constraints. The flow also covers switching to analysis mode, creating test patterns, reporting statistics, and writing out the generated patterns, faults, and flat simulation model files.

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    ATPG Tool Flow

    Uploaded by

    Adhi Suruli
    562 views12 pages
    This document outlines the typical ATPG (Automatic Test Pattern Generation) flow using the Tessent ATPG tool. It describes the key inputs needed, including the design netlist, ATPG library, and setup file. It then details the steps to invoke Tessent, specify clock signals, EDT (Enhanced Design for Testability) options, and add constraints. The flow also covers switching to analysis mode, creating test patterns, reporting statistics, and writing out the generated patterns, faults, and flat simulation model files.

    Original Description:

    Tool flow

    Original Title

    ATPG Tool Flow (2)

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    This document outlines the typical ATPG (Automatic Test Pattern Generation) flow using the Tessent ATPG tool. It describes the key inputs needed, including the design netlist, ATPG library, and setup file. It then details the steps to invoke Tessent, specify clock signals, EDT (Enhanced Design for Testability) options, and add constraints. The flow also covers switching to analysis mode, creating test patterns, reporting statistics, and writing out the generated patterns, faults, and flat simulation model files.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    562 views12 pages

    ATPG Tool Flow

    Uploaded by

    Adhi Suruli
    This document outlines the typical ATPG (Automatic Test Pattern Generation) flow using the Tessent ATPG tool. It describes the key inputs needed, including the design netlist, ATPG library, and setup file. It then details the steps to invoke Tessent, specify clock signals, EDT (Enhanced Design for Testability) options, and add constraints. The flow also covers switching to analysis mode, creating test patterns, reporting statistics, and writing out the generated patterns, faults, and flat simulation model files.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 12

    .

    ATPG Flow
    May 2017

    -Chaitanya Varma
    ATPG flow-Tessent
    Inputs
    1. Design Scan inserted netlist
    2. ATPG Library Descriptions of all the cells
    the
    design uses.
    3. Setup File Dofile and Test proc file (Set of
    commands
    given to the
    ATPG Tool on how to
    generate
    .

    .
    Invoking Tessent
    tessent -shell
    SETUP> set_context patterns -scan
    Specifying Clock signals
    SETUP> add_clocks 0 clk1 clk2...
    SETUP> add_clocks 1 rst_1...
    Where 0 is the off-state for "clk1" and "clk2" and
    1 is the off-state for rst_1
    SETUP> add_scan_group grp1
    <testproc_gen_by_scan>
    Specifying EDT options
    set_edt_finder on/off
    If on, TestKompress automatically adds proper
    constraints to input channels if pipelines are
    detected and their clocks are not constrained off
    during capture, also it will automatically find
    EDT logic and get updated scan pin information
    for test pattern generation
    set_edt_mapping on
    EDT mapping enables the tool to obtain EDT
    pin information from the block-level dofiles.
    ...Cont
    add_edt_block <edt_block>
    add_pin_constraints <cg_test_en> 0/1
    0 for s@ ,1 for TR
    add_pin_constraints <scan_enable> C0
    add_no_faults <occ>,<memories> ...
    set_split_capture_cycle on
    Set sentization checking on
    Set clockpo patterns off
    ...Cont
    set_xclock_handling X
    report_drc_rules -verbose
    Set internal fault off
    Set contention check on -atpg
    set_tied_signals z
    Switching to analysis mode
    Run DRC before switching to analysis mode to
    identify any setup issues are present.
    report_drc_rules
    set_system_mode analysis
    Note: Tool does not enter into analysis mode if
    there are any DRC present.
    ...Cont
    create patterns -auto
    report_statistics -detail
    Report patterns
    write_patterns <$design_stuck.pat.gz> -replace
    Set pattern_count <number>
    Save patterns <(chain,serial,parallel).v.gz> -
    procfile -<(chain/scan)_test -pad0 -
    serial/parallel -verilog -replace -mode_external
    ...Cont
    write_faults <$design_stuck.faults.gz> -replace
    write_flat_model
    <$design_stuck.flat_model.gz> -replace
    .

    Thank You

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