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EEE241-DLD Course Outline

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D E P A RT M E N T OF E l e c t r i c a l En g i n e e r i n g

COMSATS Institute of Information Technology


Lahore Campus, Defence Road, Off Raiwind Road, Lahore

COURSE OUTLINE
Course: Instructor: Digital Logic Design Ahmed Saeed Room: N-9 (New Faculty Block-EE) Email: ahmadsaeed@ciitlahore.edu.pk

Credit Hours:04 (3,1) Course Code: EEE241 Course Objective: The main goals of the course are to teach students the fundamental concepts in classical manual digital design and to illustrate clearly the way in which digital circuits are designed today. Ensure students to be familiar with modern hierarchy of digital hardware design and edify them the state-of-the-art computer hardware design methodologies. Finally provide them basic idea how to design and simulate logic circuits Schedule: Lectures: Two Lectures per week. Laboratory Work: Three hours of Lab work per week Lab: VLSI/MPI Lab, Recommended Books: Text Book(s): Digital Design, 3/E by M. Morris Mano Digital Fundamentals, Thomas Floyd Reference Book(s): Digital Systems by Principles and Applications,8th Edition by Tocci & Widmer Digital Design by Frank Vahid Lecture Breakdown:
Lecture No. Topics

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Introduction & Overview to Digital Logic. Number Systems. Number conversion, Signed Binary Numbers 1s & 2s complement. Data representation and Codes. Binary Logic, Integrated Circuits Introduction of Boolean Algebra. Basic Definitions and theorems. Properties of Boolean Algebra Canonical and Standard Forms. Implementation of SOP & POS. Standard form of SOP & POS. Minterms & Maxterms Logic Gates, universal Gates DC Supply Voltage. Logic Levels and Noise Margin. Propagation Delay Fan-out and loading Simplification of Boolean Expressions .The Map Method: Two and three variable Maps.Four Variable Maps. Dont care States. Product of Sums Simplification Nand and Nor Implementations. Other Two-Level Implementations Combinational Logic: Introduction: SOP & POS Combinational Circuits. Active low/high input/output. Functional Table and Implementation.

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Combinational Function Devices: XOR-XNOR Gate Implementation Half-Adder: Functional Table, Boolean Expressions and Implementation Full-Adder: Functional Table, Boolean Expressions and Implementation. Subtractions and Code Conversion Circuits designing Analysis Procedures. Multilevel NAND circuits Multilevel NOR circuits, Exclusive-or and Equivalence Functions Combinational Logic with MSI and LSI: Parallel Binary Adder, Carry Propagation Delay Look-Ahead Carry Generator,MSI Adders BCD Adders: Invalid BCD number detector, 2-digit BCD Adder. Arithmetic & Logic Unit Magnitude Comparators and Decoders: Applications of Decoders, Binary 2-to-4 Decoder, MSI 2-to-4 Decoder Multiplexers and Boolean Function Implementation Read only Memory (ROM): Designing and Combination logic Implemenation.Programmable Logic array (PLA) Sequential Logic :Introduction. Latches & Flip-flops: NAND S-R Latch, NOR S-R Latch and S-R Timing Diagrams J-K Flip-flop and its applications. Triggering of flip flops: Master Slave flip-flop, Edge-triggered S-R flip-flop Edge-triggered D flip-flop. Analysis of Clocked sequential circuits: State Table, State Diagram and State Equations Flip Flop input Functions. Sate Reduction Techniques and Assignments. Excitation Tables of flip-flops. Design Procedure: Design of Counters with examples. Design with state Equations Arithmetic Circuits and Sequential Logic Devices: Registers with Parallel Load and serial load, Sequential Logic implementation. Shift Registers with serial transfer: Serial Addition. Counters: Asynchronous Counters: Binary and BCD Ripple counters Counters: Synchronous Counters: Binary up-down counter. 4-bit Up/Down Counter The memory unit and its operation Design of simple computer Digital Integrated Circuits

Shaded area represents tentative quiz schedule Grading Policy: i) Quizzes & Assignments: ii) Sessional Tests: iii) Final Exams: Marks (25) (10 + 15) (50) Percentage 25% 25% 50%

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