Faculty of Information and Communication Technology (FICT) 8088 vs 8086

MAXIMUM MINIMUM
MAXIMUM MINIMUM
MODE /MX=gnd MODE MX=+5V
MODE /MX=gnd MODE MX=+5V
GND 1 40 Vcc
GND 1 40 Vcc
AD14 AD15 A14 A15

AD13 A16,S3 A13 A16,S3

UCCE2043 Basic Microprocessor A12 A17,S4
AD12 A17,S4
AD11 A18,S5 A11 A18,S5

8088/86 Microprocessor and AD10

AD9
A19,S6
/BHE,S7
A10
A9
A19,S6
high /SS0

Memory Interfacing (I) AD8

AD7
MN,/MX
/RD
A8
AD7
MN,/MX
/RD
AD6 /RQ,/GT0 HOLD AD6 /RQ,/GT0 HOLD
8086 AD5
8088 /RQ,/GT1 HLDA
AD5 /RQ,/GT1 HLDA
AD4 /LOCK /WR AD4 /LOCK /WR
AD3 /S2 /IO,M AD3 /S2 IO,/M
H Y Lee AD2 /S1 DT,/R AD2 /S1 DT,/R
AD1 /S0 /DEN AD1 /S0 /DEN
leehy@utar.edu.my AD0 QS0 ALE AD0 QS0 ALE
NMI QS1 /INTA NMI QS1 /INTA
INTR /TEST INTR /TEST
CLK READY CLK READY
GND 20 21 RESET GND 20 21 RESET

IO/M Address lines Data lines/Address lines RD and WR

1 (For AD ALE=0) 2
(For AD ALE=1)

Maximum and minimum modes

Summary 8088/86 pins
Minimum mode-

MN/MX' pin ->+5V. Used in small systems
Only one CPU.

Least expensive because all the control signals for the

3 major differences between 8088/86 pins memory and IO are generated by the microprocessor.

8088 generates all control signals by itself

Some control signal must be generated using logic gate.
8086 8088

88/86 in min mode provides 3 signals

Using RD, WR, AND IO / M’ (or M / IO’ ) to generate 4 signals
BHE’/S7 pin SS0 pin

Maximum mode-

MN/MX' pin -> ground. Used in large systems and systems
M/IO’ IO/M’
with more than one processors.

8088 does not generate control signals itself.
AD8-15 pins A8-15 pins
control signals must be externally generated. Requires
additional circuitry. E.g. need a chip - the 8288/89 bus
controller.

* Homework…find out more about 8288/8289 from internet!!

3 4
 Minimum Mode Bus Design
Minimum Mode
(8088)
RD’ WR’ IO/M’ (8088) Signal WR’
M/IO’ (8086)
IOW’
0 1 0 MEMR (8088)
IOR (8086)
MEMW (8088) MEMW’
1 0 0 IO/M’
IOW (8086) MEMR’
0 1 1 IOR (8088)
MEMR (8086) IOR’

1 0 1 IOW (8088)
RD’
MEMW (8086)
0 0 X NO USE
5 6

Minimum mode (1) Minimum mode (2)

MAXIMUM
MODE
MINIMUM
MODE
DEN Data Enable (active low)(26) MAXIMUM
MODE
MINIMUM
MODE
GND 1 40 Vcc
• output signal GND 1 40 Vcc
AD14 AD15 • enable 74LS245, which allows AD14 AD15 IO / M’ (8088) or IO’ / M (8086) (28)
AD13 A16,S3 isolation of the CPU from system bus AD13 A16,S3
• Memory or Input/output
AD12 A17,S4 AD12 A17,S4
AD11 A18,S5 AD11 A18,S5
• Indicate whether address bus is accessing
ALE address latch enable (active high)(25) memory or input / output device
AD10 A19,S6 AD10 A19,S6
AD9 /BHE,S7
• output signal AD9 /BHE,S7
AD8 MN,/MX • Indicate that a valid address is available AD8 MN,/MX
AD7 /RD on the external address bus AD7 /RD
AD6 /RQ,/GT0 HOLD AD6 /RQ,/GT0 HOLD
AD5
8086
/RQ,/GT1 HLDA
• Multiplexes the Address and Data signals AD5
8086
/RQ,/GT1 HLDA
AD4 /LOCK /WR onto the same set of pins AD4 /LOCK /WR
AD3 /S2 /IO,M AD3 /S2 /IO,M
AD2 /S1 DT/R INTA interrupt acknowledge (active low)(24) AD2 /S1 DT,/R
AD1 /S0 /DEN
• output signal AD1 /S0 /DEN DT / R’ Data Transmit Receive (active low) (27)
AD0 QS0 ALE AD0 QS0 ALE
• Inform interrupt controller that an • output signal
NMI QS1 /INTA NMI QS1 /INTA
INTR /TEST interrupt has occurred INTR /TEST
• used to control the Data Direction of data flow
CLK READY • And the vector number is available on the CLK READY through 74LS245 buffer
GND 20 21 RESET GND 20 21 RESET
lower 8 lines of the data bus.
7 8
 DEN’ vs DT/R’ Minimum mode (3)
MAXIMUM MINIMUM
MODE MODE
GND 1 40 Vcc
HOLD (active high) (31) )
AD14 AD15
DEN’ DT/R’ Action AD13 A16,S3
• input from DMA controller
AD12 A17,S4 • Indicates that external devices requesting
0 0 data travels into AD11 A18,S5 to control the local buses
AD10 A19,S6
processor AD9 /BHE,S7
AD8 MN,/MX HLDA hold acknowledge (active high) (30)
0 1 data travels away AD7 /RD • output signal used after HOLD.
from processor AD6
8086
/RQ,/GT0 HOLD
• Indicates that CPU is in HOLD state and
AD5 /RQ,/GT1 HLDA
AD4 /LOCK /WR
allows external devices to use buses.
1 0 data bus AD3 /S2 /IO,M
disconnected . AD2 /S1 DT/R WR write (active low) (29)
AD1 /S0 /DEN
• output signal
AD0 QS0 ALE
1 1 data bus NMI QS1 /INTA
• Indicating that Data on the bus is being
disconnected . INTR /TEST written to memory or I/O device
CLK READY
GND 20 21 RESET

9 10

Minimum mode (4)

MAXIMUM MINIMUM
MODE MODE SSO status line (8088 only) (34)
GND Vcc
1 40
• output signal that can be used along
A14 A15
A13 A16,S3
with the IO/M’ and DT/R’ to decode the
A12 A17,S4 status of the current bus cycle.
A11 A18,S5
A10 A19,S6
A9 high /SS0
A8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8088 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO,/M Minimum Mode 8088
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

11 12
 Maximum Mode
MAXIMUM MINIMUM
MODE MODE
GND 1 40 Vcc
AD14 AD15
S2’,S1’,S0’ (26-28)– identifies
AD13 A16,S3 the status of current bus cycle.
AD12 A17,S4
AD11 A18,S5
(Decoded by 8288 – the Bus Controller).
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
QS0, QS1 (24-25)–instruction queue code
AD7 /RD
AD6 /RQ,/GT0 HOLD

Tells the external circuit what type
8086
AD5 /RQ,/GT1 HLDA of info was removed from the queue
AD4 /LOCK /WR
AD3 /S2 IO/M
during the previous clock cycle.
AD2 /S1 DT/R
In IBM PC, these pins are connected to
AD1 /S0 /DEN
AD0 QS0 ALE 8087 to synchronize with 8088.
Minimum Mode 8086 NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

13 14

Maximum Mode Maximum Mode

QS1(pin 24) QS0(pin 25) QUEUE STATUS
Status Inputs (pin 26-pin 28) 8288
CPU Cycle 0 0 No operation. During the
Commands
S2’ S1’ S0’ last clock cycle, nothing
was taken from the
0 0 0 Interrupt ack. INTA’ queue

0 0 1 Read I/O port IORC’ 0 1 First byte. The byte

taken from the queue
0 1 0 Write I/O port IOWC’,AIOWC’ was the first byte of the
instruction
0 1 1 Halt NONE
1 0 Queue Empty. The
1 0 0 Inst. fetch MRDC’ queue has been
reinitialized as a result
1 0 1 Read memory MRDC’ of the execution of a
transfer instruction.
1 1 0 Write memory MWTC’,AMWC’
1 1 Subsequent Byte. The
1 1 1 Passive NONE byte taken from the
queue was a subsequent
byte of the instruction.
Memory bus cycle status codes produced in maximum mode
15 16
 Maximum Mode
MAXIMUM MINIMUM
MODE MODE LOCK’ (active low) (29)
GND 1 40 Vcc • output signal
AD14 AD15
• Used to prevent other processors or
AD13 A16,S3
AD12 A17,S4
devices from gaining control on the
AD11 A18,S5 buses.
AD10 A19,S6 • Activated by LOCK prefix in the instruction
AD9 /BHE,S7
of the assembly program
AD8 MN,/MX
AD7 /RD
AD6
8086
/RQ,/GT0 HOLD RQ’/GT0’ and RQ’/GT1’ request Grant(30,31)
AD5 /RQ,/GT1 HLDA
• Bidirectional Lines
AD4 /LOCK /WR
AD3 /S2 IO/M
• Allow other processors to gain control
AD2 /S1 DT/R on the bus
AD1 /S0 /DEN • In IBM PC, RQ / GT0 is connected to
AD0 QS0 ALE Maximum Mode 8088
NMI QS1 /INTA
high making it disabled and RQ /GT1 is
INTR /TEST connected to 8087
CLK READY
GND 20 21 RESET Same functions as
those pins on the 8088
17 minimum mode 18

8088/86 pins

Vcc CLK MRDC# INTR Interrupt Request (18)

MWTC# MAXIMUM MINIMUM
AMWC# MODE MODE • Active high level-triggered input
S0#
S1#
8288 GND 1 40 Vcc • Monitored by µp at the last clock cycle
8284A CLK IORC#
S2# Bus
Clock READY
Controller
IOWC# AD14 AD15 after each instruction.
Generator RESET AIOWC# AD13 A16,S3
DEN
RDY DT/R# INTA# AD12 A17,S4
8086 ALE AD11 A18,S5
NMI Non-maskable interrupt (17)
CPU AD10 A19,S6
MN/MX# AD9 /BHE,S7
• Edge triggered input signal from low to high
LE AD8 MN,/MX • Input to µp.
OE# AD7 /RD • Cause µp to jump into interrupt vector after
BHE# 74LS373 AD6 /RQ,/GT0 HOLD
AD15:AD0 x3
A19:A0,
AD5
8086
/RQ,/GT1 HLDA
finishing current instruction
ADDR/DATA BHE#
A19:A16 AD4 /LOCK /WR • Can not be masked by software
INTR AD3 /S2 IO’/M
AD2 /S1 DT/R
AD1 /S0 /DEN
Maximum Mode 8086 DIR AD0 QS0 ALE
EN# BHE’ Bus High Enable (34)
NMI QS1 /INTA
74LS245
74LS245 D15:D0 INTR /TEST • Used with 8086 to distinguish between
x2
ADDR/Data x2 CLK READY high and low byte in memory
GND 20 21 RESET

19 20
8088/86 Hardware Organization of the Memory Space Memory Bank Selection in 8086
Byte-Wide addressing
ODD Addresses (8086) EVEN Addresses (8086)
(8088)
BHE’ A0/BLE Selection
FFFFF FFFFF FFFFE
FFFFE ONE ADDRESS FFFFD FFFFC
FFFFD FFFFB FFFFA
FFFFC FFFF9 FFFF8
0 0 Whole word (16-bits)

A19..A1 A19..A1
0 1 High byte to/from odd
address
00002 00005 00004
00001 00003 00002 1 0 Low byte to/from even
00000 00001 00000 address

1 1 None

D15:D8 D7:D0

BHE BLE(A0)
21 22

8088/86 pins 8088/86 pins

CLK (19)
MAXIMUM MINIMUM • µp require a very accurate clock for MAXIMUM MINIMUM RESET (21)
MODE MODE MODE MODE
synchronizing. • Input to µp to provide a hardware reset
GND 1 40 Vcc GND 1 40 Vcc
AD14 AD15
• Intel designed 8284 clock generator to AD14 AD15
• Switching RESET to logic 0 initializes the
AD13 A16,S3 work with 8088/86. AD13 A16,S3 internal registers of the µp and initiates
AD12 A17,S4 • CLK is an input and connected to 8284 AD12 A17,S4 a reset service routine.
AD11 A18,S5 AD11 A18,S5
clock generator. • After reset, µp will contains the following
AD10 A19,S6 AD10 A19,S6
AD9 /BHE,S7
• Any irregularity will cause the CPU to AD9 /BHE,S7 data:
AD8 MN,/MX malfunction AD8 MN,/MX
AD7 /RD AD7 /RD CPU CONTENTS
AD6 /RQ,/GT0 HOLD AD6 /RQ,/GT0 HOLD CS FFFFH
8086 8086
AD5 /RQ,/GT1 HLDA Vcc AD5 /RQ,/GT1 HLDA
DS 0000H
AD4 /LOCK /WR AD4 /LOCK /WR
AD3 /S2 IO/M AD3 /S2 IO/M SS 0000H
8284A CLK
AD2 /S1 DT/R Clock READY AD2 /S1 DT/R
ES 0000H
AD1 /S0 /DEN Generator RESET AD1 /S0 /DEN
AD0 QS0 ALE RDY AD0 QS0 ALE IP 0000H
NMI QS1 /INTA 8086 NMI QS1 /INTA FLAG CLEAR
INTR /TEST
CPU INTR /TEST
MN/MX# QUEUE EMPTY
CLK READY CLK READY
GND 20 21 RESET GND 20 21 RESET

23 24
 8088/86 pins 8088/86 pins
MAXIMUM MINIMUM MAXIMUM MINIMUM
MODE MODE MODE MODE
GND 1 40 Vcc READY (22) GND 1 40 Vcc
AD14 AD15 • Input signal AD14 AD15
AD13 A16,S3
• Used to insert a wait state for slower AD13 A16,S3 S3,S4,S5,S6,S7 (35-38) – STATUS
AD12 A17,S4 AD12 A17,S4
memories and IO. • Output signal
AD11 A18,S5 AD11 A18,S5
AD10 A19,S6 • As long as READY is held at ‘0’, wait AD10 A19,S6
• S7: Logic 1, S6: Logic 0.
AD9 /BHE,S7 states are inserted. AD9 /BHE,S7 S5: Indicates condition of IF flag bit.
AD8 MN,/MX AD8 MN,/MX S4-S3: Indicate which segment is
AD7 /RD AD7 /RD
accessed during current bus cycle:
AD6 /RQ,/GT0 HOLD AD6 /RQ,/GT0 HOLD
8086 8086
AD5 /RQ,/GT1 HLDA AD5 /RQ,/GT1 HLDA
TEST’ (23)
AD4 /LOCK /WR AD4 /LOCK /WR
AD3 /S2 IO/M • Input to µp AD3 /S2 IO/M
AD2 /S1 DT/R • Related to external interrupt interface AD2 /S1 DT/R
AD1 /S0 /DEN • Used to synchronize the operation of the AD1 /S0 /DEN
AD0 QS0 ALE AD0 QS0 ALE
NMI QS1 /INTA
µp to an event in external hardware. NMI QS1 /INTA
INTR /TEST Ex: Serve as input signal from 8087 INTR /TEST
CLK READY Coprocessor CLK READY
GND 20 21 RESET GND 20 21 RESET

25 26

Memory Concepts Memory organization

The total number of bits that a memory

Hold program code, data that processed chip can store is equal to the number of
by CPU locations times the number of data bits per

Performance - amount and type of system location.
memory. =2X * y
x is the number of address pins on the IC.

Software Support: Newer programs
y is the number of data pins on the IC.
require more memory than old ones.
E.g. 8K*8

Reliability and Stability: Bad memory
cause “hang”. Choose correct RAM

27 28
 Example 1 Example 2
A given memory chip has 12 address pins and
A 512K capacity memory chip has 8 pins for
4 data pins. Find data. Find:
(a) the organization (a) the organization
(b) the capacity (b) the number of address pins for this
memory chip
Solution:
(a) This memory chip has 4096 locations (2^12 = 4096), Solution:
each location can hold 4 bits of data. (a) A memory chip with 8 data pins means that each location within
This gives an organization of 4096 x 4, often represented as 4Kx4. the chip can hold 8 bits of data.
(b) 4Kx4=16K To find the number of locations within this memory chip, divide the
capacity by the number of data pins. 512K/8 = 64K; therefore,
the organization for this memory chip is 64Kx8;
(b) The chip has 16 address pins 64K=65536 = 2^16

From the book The 80x86 IBM PC by Muhammad Ali From the book The 80x86 IBM PC by Muhammad Ali
29 30
Mazidi and Janice Gilispie pg. 267 Mazidi and Janice Gilispie pg. 267

Memory Types EPROM & Eraser & Programmer

ROM – non volatile, secure
 ROM- perform functions that cannot be
changed.
 PROM- one-time programmable
For every bit of the PROM, there exists a
fuse. PROM is programmed by blowing the
fuses.
 EPROM- uv light is used to erase the
information. ~ 20 min to erase
 EEPROM- erase thru software, flash BIOS.
One can select which byte to be
erased
 ROM is slower than RAM, shadowing is
used

RAM – volatile
 Faster than ROM
 RAM is often used to shadow the BIOS
ROM
 RAM

Static & Dynamic

Volatile & Non-volatile RAM
31 32
 EPROM -2764
Access Time

amount of time that it takes for the memory to
produce the data required, from the start of
the access until when the valid data is
available for use
SIZE?

Ranging 2ns to 70ns - depending on the IC
technology used in the design and
fabrication.

33 34

EEPROM
EEPROM X2816C

EEPROM allows its contents to be programmed
and erased while it is still in the system board.
It does not require physical removal of the
memory chip from its socket.

To utilize EEPROM fully, the designer must SIZE?

incorporate into the system board the circuitry
to program the EEPROM, using 12.5 V for VPP.
EEPROM with VPP of 5 - 7 V is available, but it
is more expensive.

35 36
 Flash memory EPROM
Static RAM(1)

The process of erasure of the entire
contents takes less than a second.
Used as Cache memory, LI & L2.

Storage cells in static RAM memory are made

The erasure method is electrical.
of flip-flops and therefore do not require

Difference between EEPROM and flash refreshing in order to keep their data. This is in
memory is the fact that when flash contrast to DRAM
memory's contents are erased, the
SRAM bit consist 4 to 6 transistor, DRAM just 1
entire device is erased, in contrast to + a capacitor.
EEPROM, where one can erase a
SRAM chips consists thousands, millions of
desired section or byte. identical cells.
 Incomparison, CPU occupies a large area of die
with non-repetitive structure.
37 38

Static RAM(2) SRAM-6264

Simplicity : don't require external refresh circuitry

Speed : faster than DRAM.

Cost: several times more expensive than DRAM.

SIZE?

Size: take up much more space than DRAMs (which is part
of the reasons why the cost is higher).

39 40
 DRAM (1) DRAM (2)

High density (capacity),

Holds its data if it is continuously accessed by special
Cheaper cost per bit,
logic called a refresh circuit.

Lower power consumption per bit.

Keep on refresh whether it been used by CPU or not.

Must be refreshed periodically, due to the fact that the

The use of capacitors as storage cells in DRAM results capacitor cell loses its charge;
in much smaller net memory cell size.

While it is being refreshed, the data cannot be

Cheaper and take up much less space, typically 1/4 (or accessed. This is in contrast to SRAM's flip-flops,
less) the silicon area of SRAMs. which retain data as long as the power is on, which do

The transistor is used to read the contents of the not need to be refreshed, and whose contents can be
capacitor but keep on refresh. accessed at any time.

Refreshing action=dynamic and expressed in
DRAM requires more supporting circuitry.
nanosecond (ns)
41 42

Packaging issue in DRAM (1)

Problem of packing a large number of cells into a single Packaging issue in DRAM (2)
chip with the normal number of pins assigned to
addresses.
To access a bit of data from DRAM, both row and column

E.g. a 64K-bit chip (64Kx1) must have 16 address lines addresses must be provided. For this concept to work, there must
be a 2 by 1 multiplexer outside the DRAM circuitry and a
and 1 data line, requiring demultiplexer inside every DRAM chip.

16 pins to send in the address if the conventional method is used +
Vcc power, ground, + read/write control pins.

Due to the complexities associated with DRAM interfacing (RAS,

Solution: Signals lines, RAS( Row Address Select) & CAS, the need for multiplexer and refreshing circuitry),
CAS(Column Address Select) introduced.  DRAM controllers are designed to make DRAM interfacing much easier.
 The first half of the address is sent in through the 8 pins A0 - A7.
By activating RAS (row address strobe), the internal latches
Many small microprocessor-based projects that do not require
much RAM (usually less than 64K bytes) use SRAM instead of
inside DRAM grab the first half of the address. DRAM.
 The second half of the address is sent in through the same pins.
By activating CAS (column address strobe), the internal latches
E.g. 16Mbit = 4Mx4 = 4,194,304 = 22bits = 22 address line, 11
inside DRAM again latch this second half of the address. address lines if divide into row and column address

This results in using 8 pins for addresses plus RAS and ∴reduce numbers of pins, slow down addressing process, fewer
CAS =10 pins input, less power, smaller chips
From the book The 80x86 IBM PC by Muhammad Ali
From the book The 80x86 IBM PC by Muhammad Ali 43 44
Mazidi and Janice Gilispie pg. 274
Mazidi and Janice Gilispie pg. 273
 DRAM (4)
DRAM(3)

SIZE?

Typical memory IC
45 46

Example 1
DRAM (5)
Show possible organizations and number
of address pins for 256K DRAM chip

DRAM is usually places on Solution:
For 256K chips, possible organizations are 256Kx1 or 64Kx4.
small circuit boards called In the case of 256Kx1, there are 256K locations and
SIMMs (Single In-line each location inside DRAM provides 1 bit.
The 256K. locations are accessed through the 18-bit address
Memory Modules). A0–A17 since 2^18 = 256K.
The chip has only A0-A8 physical pins plus RAS and CAS and
one pin for data in addition to Vcc, ground,
and the R/W pin that every DRAM chip must have.
For 64Kx4 organization,
4Mx9 it requires 16 address bits to access each location (2^16 = 64K),
and each location inside the DRAM has 4 cells.
SIZE? That means that it must have 4 data pins, D0-D3, 8 address pins,
A0-A7, plus RAS and CAS.

From the book The 80x86 IBM PC by Muhammad Ali

47 48
Mazidi and Janice Gilispie pg. 275
 Example 2 NV-RAM (nonvolatile RAM)

Show possible organizations and number of
While both DRAM and SRAM are volatile, there is a new type of
RAM called NV-RAM, nonvolatile RAM.
address pins for 1M DRAM chip
Like other RAMs, it allows the CPU to read and write to it, but when the
power is turned off, the contents are not lost, just like ROM.

NV-RAM combines the best of RAM and ROM: the read and write ability
of RAM, plus the non-volatility of ROM.

To retain its contents, every NV-RAM chip internally is made of the
Solution: following components:
In the case of a 1M chip, there can be either 1Mx1 or 256Kx4 organizations.
It uses extremely power efficient (very, very low power consumption) SRAM cells
built out of CMOS.
For 1Mx1, there are A0 - A9, 10 pins,

It uses an internal lithium battery as a backup energy source.
to access 1M locations with the help of RAS and CAS and one pin for data.

It uses an intelligent control circuitry.
The 256Kx4 has 9 (A0 - A8) and 4 (D0 - D3) pins,
respectively, for address and data plus RAS and CAS pins.
The main job of this control circuitry is to monitor the Vcc pin
constantly to detect loss of the external power supply. If the power to
the Vcc pin falls below out-of-tolerance conditions, the control circuitry
switches automatically to its internal power source, the lithium battery.
In this way, the internal lithium power source is used to retain the NV-
RAM contents only when the external power source is off.
From the book The 80x86 IBM PC by Muhammad Ali
Mazidi and Janice Gilispie pg. 276
From the book The 80x86 IBM PC by Muhammad Ali
49 50
Mazidi and Janice Gilispie pg. 276

Complete 8086/8 8284 clock generator (1)

In Maximum Mode the 8086/8 needs at
least the following: 8284A Clock Generator,
Designed to be used with
8088/86 microprocessors,
8288 Bus Controller, 74HC373s and

Provides the clock and
74HC245s synchronization for the

With the aid of these devices the 8086 microprocessor,

Provides the READY signal
begins to look like the ideal microprocessor for the insertion of wait
we looked at earlier (Slide 18 &19) states into the CPU bus
cycle.

51 52
 8284 clock generator (2)
8284 clock generator (3)

/8088
•Correct reset timing requires that the RESET input to
the microprocessor becomes a logic 1 NO LATER than
4 clocks after power up and stay high for at least 50us.

53 54

Important pins in 8284(1) Important pins in 8284 (2)

RES’ (reset in) (11) X1 and X2 (crystal in) (16,17) F/C’ Frequency Clock select (13)(i/p)
RESET (10) (output)
XI and X2 are the pins to which a
option for the way the clock is

Input active-low signal to
crystal is attached. generated.
generate RESET.
This is an active-
The crystal frequency must be 3
If low, the clock is generated by

In the IBM PC, it is connected to times the desired frequency for the 8284 with the crystal oscillator.
the power-good signal from the
high signal that the microprocessor.
If it is connected to high, it
power supply. provides a RESET
The maximum crystal for the
8284A is 24 MHz and 30 MHz for
expects to receive clocks at the
EFI pin.

When the power switch in the
IBM PC is turned on, assuming
signal to the 8088/86. the 8284A-1.
IBM PC uses a crystal, this pin is

The IBM PC is connected to a connected to low.
that the power supply is good, a
It is activated by the crystal of 14.31818 MHz. For
low signal is provided to this pin some turbo compatibles, it is 24
and the 8284 in turn will activate RES’ input signal. MHz.
the RESET pin, forcing the
8088/86 to reset EFI (external frequency in) (14)(input)
; then the microprocessor takes • External frequency is connected to this pin if F/C’ has been connected to
over. high.

This is called a cold boot. • In IBM PC, this is not connected since a crystal is used instead of an
external frequency generator.

55 56
 Important pins in 8284 (3) Important pins in 8284 (4)
RDY1 and AEN1 (3,4) (input) OSC (oscillator) (12) (output) CLK (clock) (8) (output) PCLK (peripheral clock)(2)(output)

Output clock frequency equal to
This frequency is one-half of CLK

RDY1 is active high and AEN1

Provides a clock one-third of the crystal oscillator, (or one-sixth of the crystal) with a
(address enable) is active low. or EFI input frequency, with a duty cycle of 50% and is TTL
frequency equal to the duty cycle of 33%. compatible.

They are used together to
provide a ready signal to the crystal oscillator and it is
This is connected to the clock
In the IBM PC this 2.386383 MHz is
microprocessor, which will TTL compatible. input of the 8088/86 and all other provided to the 8253 timer to be
devices that must be used to generate speaker tones,
insert a WAIT state to the CPU
The IBM crystal oscillator synchronized with the CPU. and other functions
read/write cycle. is 14.31818 MHz, OSC will
In IBM PC it is connected to pin

In the IBM PC, RDY1 is 19 of the 8088 microprocessor
provide this frequency to and other circuitry under the
connected to DMAWAIT and CLK88 label. READY (5) (output)
AEN1 is connected to the expansion slot of the


This frequency, 4.772776 MHz Connected to READY of the CPU.
RDY/WAIT. IBM PC. (14.31818 divided by 3), is the

processor frequency on which all
In the IBM PC it is used to signal

They allow the wait state to be
of the timing calculations of the the 8088 to indicate if the CPU
inserted either by the CPU or memory and I/O cycle are based needs to insert a wait state due to
by DMA. on. the slowness of the devices that
the CPU is trying to contact.

57 58

Clock cycles

All µp actions are synchronized by a continuous train of Why Clock Cycle Calculations?
regularly time pulses known as clock.

These clock pulse obtained from an oscillator circuit .

Each clock period is generally called a T-state or time state
Delays

If the clock frequency is 5 MHz then each T-state lasts
Analog to digital sampling
200ns. Each basic operation is called a machine cycle.

The number of T-states in a machine cycle depends on the

Sound
instruction----take at least 3 or 4 T-states.
Real-Time Applications
Example of clock cycle
Anti-lock breaking system
T-state
Industrial vision inspection of
items on a conveyor belt

Playback of stored video clips

One machine cycle

M1 fetch M2 Read M3 Write

Instruction cycle 59 60
 Clock Cycle Calculation (1) Clock Cycle Calculation (2)

Speed between the two processors can be
differentiated by calculating the number of
If we design a delay loop, how many clock
clock cycles each requires for a series of cycles are used in the loop? and how much
operations. time a single clock cycle lasts?

E.g. In 80286 the LOOP instruction takes 8
We can adjust the number of iterations of the
clocks instead of 17 clocks in 8086/88.
delay loop so that the time consumed t, is

The Intel datasheet lists the number of clocks equal to the desired value.
each instruction needs to execute.

t=total of clocks used * duration of one clock

For each instruction the clock cycle might be
fixed or variable, depend on cycle *number of iteration

Operand type, operand size, instruction outcome, and
addressing mode.
61 62

Answer
Clock Cycle Calculation (3)
mov cx,N ;
mov al,01 ;

Assume the Pentium µp( clock frequency = 50MHz) has the out 23,al
following information
Instruction Number of clocks
ag: loop ag ; 6*(N-1) + 5 clocks
Mov reg,immed 1
mov al,00h ; 1 clock
loop 6/5 (6 if branch, 5 if not)
out 23,al ; 12 clocks
Out al,immed 12

How many iteration will be needed to achieve the 1 ms delay for
Total no. of clocks = 6*(N-1)+5+1 +12
the following code?

mov cx,N ; N unknown- number of iteration
Total time = 6*(N-1)+5+1 +12*1/(50MHz)
mov al,01
out 23,al
To achieve 1ms delay:
ag: loop ag ; cx=cx-1 with each loop; loop til cx=0
mov al,00h ; 1 clock (6N+12)/50 = 1ms
out 23,al ; 12 clocks
N = 8331 iterations
63 64
 Example

Write a program to generate a delay of 100ms using 8086 system that
runs on 10MHz frequency.
Instruction Execution Time
Mov cx, count ;4

Assume that the instructions have already
again: Dec
nop
cx ;2
;3
been fetched by the BIU and stored in the
jnz again ;16
Number of clock cycles for execution of the loop > instruction queue.
Time required for execution of the loop * 1/10 MHz =2.1 µs
Count=100ms/2.1 µs = 47619 = BA03H NOTE:
Complete codes

8086 has a 6-byte queue
delay proc far
8088 has a 4-byte queue
mov cx, BA03H ;4
again: Dec cx ;2
nop ;3
The wider data bus for 8086 means I.Q.
jnz
ret
again ;16 if branch, 4 if not
;8 filled up faster.
Exact time= 0.1*4 + (2+3)*47619*0.1 + 16*47618*0.1 + 4*0.1 + 8*0.1= 99.9999ms

* Impossible to generate 100% accurate time delay… to be more accurate use

programmable timer chip 8253 or 8254
65 66

Inserting Wait States (1) Example

To access an external device such as memory or I/O, the
Calculate the memory cycle time of a 20-MHz 80386
CPU provides a fixed amount of time called bus cycle time. system with:

The bus cycle time used for accessing memory is called
0 WS
memory cycle (MC).
1 WS

The time the CPU provides the addresses at its address pins
2 WS
to the time the data is expected at its data pins is called * Assuming that the bus speed is the same as the processor speed.
memory read cycle time.

8088 memory cycle time = 4 clocks, 80286 Solution:
clocks. 1/20MHz = 50ns is the processor clock period. Since the 386 bus

If memory is slow and its access time do not match cycle time of zero wait states is 2 clocks, we have
the MC time of the CPU, extra time called wait states
from the CPU is inserted to extend the read cycle time. Memory cycle time with 0WS = 2x50=100 ns

To reduce wait states, cache memory(L1 & L2) and Memory cycle time with 1WS = 100 + 50 =150ns
Memory cycle time with 2WS = 100 + 50 + 50 = 200ns
high speed DRAM is invented.

From the book The 80x86 IBM PC by Muhammad Ali From the book The 80x86 IBM PC by Muhammad Ali
Mazidi and Janice Gilispie pg. 291 Mazidi and Janice Gilispie pg. 291
67 68
 Inserting Wait States (2) Notes on Clock Cycles Calculations

Memory access time is not the only factor slowing down
the CPU although it is the largest. • 8088 needs 4 extra clock cycles for each 16-bit

Path Delay: memory access.
Time taken for address signals to go from CPU pins to memory
pins going through decoders and buffers. This include the time it • 8086 needs 4 extra clock cycles for each 16-bit
takes for the data to travel from memory to CPU. memory access only if address is odd.

E.g – A 20MHz 80386 based system is using ROM of • Transfer of control instructions require more time if
speed 150ns. Calculate the number of wait states they jump (to flush queue and fetch new machine
needed if the path delay is 25ns. instructions).

Answer: • JNZ ; 16 clocks cycles if jump else 4
 Total time to get data into CPU= 150+25=175ns
 Memory cycle time of 20MHz 80386 with 0 WS • Segment overrides add 2 clock cycles.
= 1/20MHz * 2 = 100ns.
 2 WS is needed to make the memory cycle time > 175ns.
=> 100+50+50=200ns

69 70

Clock cycles for Effective Address Example (refer to instruction set)

Addressing Mode Operand CLK
Direct Label 6
Register indirect [BX] 5
[SI] 5 8086 8088

DS=2500H BX=3000H
mov [BL],12H ; total clocks=10+5=15
[DI] 5
=> PA= 28000H (even)
mov [BX],1234H; total clocks =
[BP] 5
mov [BX],1234H; total clocks = 10 + 10+4+5=19
Based relative [BX]+DISP 9 5 =15

34<-28000H and 12<-28001 fetched
[BP]+DISP 9
into the CPU in 1 memory cycle.
Indexed relative [DI]+DISP 9
If BX=3005H, => PA=28005H
[SI]+DISP 9 - extra 4 clock penalty for non
aligned data
Use EVEN directive
Based relative [BX][SI] 7  Org 0020H

mov [BX],1234H; total clocks =
[BX][DI] 7 10+4+ 5 =19 DATA1 db 34H
EVEN
[BP][SI] 8
34<-28005H and 12<-28006 fetched. DATA2 dw 7F5BH
[BP][DI] 8
** D0-D7 (in even address)
D8-D15 (in odd address) DS:0020=34
Based indexed relative [BX][SI] 11

if mov [BL],12H with BX=3005H DS:0021=?
[BX][DI] 11 DS=2500H – only 1 memory cycle DS:0022=5B
with just the contents of DS:0023=7F
[BP][SI] 12
28005H->12H
[BP][DI] 12
UPDATE 2009 71 72
 8086 Memory Interfacing Circuits (1) 8086 Memory Interfacing Circuits (2)

Address / Data Bus Multiplexing

 8086/8 Multiplexes the Address and Data
signals onto the same set of pins (Refer to
Slide 2)
 Need external IC to separate the signals

Address Bus Latches & Buffers

 74373, an octal latch device can be used to
implement the address latch section of the
8086 memory interface circuit.
* Read Triebel & Singh, page 364-366 for detail descriptions 73 74

74HC373 Octal Transparent Latch Use of ALE (Address Latch Enable)

Address/
Data Bus

ALE (from 8086/88) is used with an external

latch (74373) to de-multiplex the address
and data lines
ALE

74373 is transparent when its LE input
(connected to ALE) is high

When ALE goes low, the 74373 holds the
System Address Bus last data until ALE goes high again
OE’= TriState Control signal,
OE’, shown connected to
GND for simplicity * Read Triebel & Singh, page 366-367 for detail descriptions
75 76
 Fan-out
74HC373 Timing diagram
Fan-out is the maximum number of (input)
devices that can be powered by a single
Clock (output) device

For example, a single NOT gate driving several
other NOT gates.
Address/
Address Data Time
Data
Time
Bus

ALE
Fan out = Max supply/unit load

Calculate for both high
and low logic levels
Output of
Use the lower fan-out value
Microcomputer Address Bus
74HC373 as the overall fan-out for the device

77 78

Example

Find how many unit loads can be driven by the 74HCT244/245 Buffers/drivers
output of the LS logic family with the following
information:
When the receiver current requirements exceed
the driver capability, bus buffering is use to
IIL = 1.6 mA IOL = 8 mA IIH = 40 uA IOH = 400 uA boost the signals traveling on the buses.

For unidirectional bus
Fan-out (low) = IOL = 8mA = 5  74XX244s are used
IIL 1.6mA
For bidirectional bus
I 400uA  74XX245s are used
Fan-out (high) = OH = = 10
Can sink and source a much larger current than
IIH 40uA other gates…fan out is high compare to others.
This mean that the fan out is 5. in other words the LS output must not connected  IOH=3mA

74244 and 74245 IOL=12mA
to more than 5 inputs with unit load characteristics

79 80
74HC244 and 74HC245

Enable DIR Operation

G’
74HC244 Octal buffer L L B to A bus
74HC245 Bidirectional
buffer L H A to B bus

H X 81
Isolation