Ad0 Ad7 A8 A15 A16/s3 A19/s6 Ad0 Ad7 A16/s3 A19/s6
Ad0 Ad7 A8 A15 A16/s3 A19/s6 Ad0 Ad7 A16/s3 A19/s6
Ad0 Ad7 A8 A15 A16/s3 A19/s6 Ad0 Ad7 A16/s3 A19/s6
essor
8088 pin
onguration
The 8088 ma
hine
y
le
onsists of four
lo
k
y
les. The four
lo
k pulses within the ma
hine
y
le are normally
alled T1, T2, T3 and T4. During T1 the 20 pins AD0 − AD7, A8 − A15 and
A16/S3 − A19/S6 a
t as the address bus. after that, AD0 − AD7, a
t as the 8-bit data bus and
A16/S3 − A19/S6 a
t as four status pins.
Fun
tionalities of some of the other pins:
• RD - memory read (if S2 is 1) or I/O read (if S2 is 0).
• READY - the pin through whi
h the addressed memory or I/O devi
e a
knowledges that it is
able to
omplete the data transfer.
• IN T R - interrupt request
• CLK -
lo
k input whi
h provides the basi
timing for the pro
essor. This should be an asym-
metri
signal with 33
• M N/M X - indi
ates what mode the pro
essor is to operate in ( minimum mode or maximum
mode).
• S0, S1 and S2 - status pins. A
tive only during T1, T2 and T4. Otherwise stay in 1 state.
8088 registers
Memory segmentation
The 8088 mi
ropro
essor has a 20 bit address bus. Therefore one
an
onne
t a maximum of 1
Megabytes of memory. However, the internal registers are all 16-bit. In parti
ular, the instru
tion
pointer IP is a 16-bit register. Therefore IP alone
annot a
ess more than 64 kilobytes of memory.
This problem has been solved by the use of segment registers. Whenever the 8088 needs to fet
h
an address from the memory, it
onstru
ts a 20-bit address by
ombining IP with the
ode segment
register CS. As shown below, this
ombining is done by shifting the
ontents of the segment register
by 4 bits to the left and adding it to IP.
1
Following are the general rules for using segment
registers:
• IP is always added to CS
• SP is always added to SS
• BP is normally added to SS
IRQ0
IRQ1 interrupt
IRQ2 requests
8259
interrupt IRQ7
controller
The 8284A
lo
k generator produ
es the
lo
k signal for the pro
essor. The
lo
k signal is a square
wave whi
h is high during one third of the
y
le and low during two thirds of the
y
le. An 8088
ma
hine
y
le
onsists of four
lo
k
y
les.
The 8288 bus
ontroller generates following
ontrol signals using the information from S0 - S2 lines.
IOR (I/O read): When this line is low, the pro
essor is reading the
ontents of the I/O port
address spe
ied by the address bus.
IOW (I/O write): When this line is low, the pro
essor is writing the
ontents of the data bus to
the I/O port address spe
ied by the address bus.
M EM R (memory read): When this line is low, the pro
essor is reading from memory address
spe
ied by the address bus.
M EM W (memory write): When this line is low, the pro
essor is writing to the memory address
spe
ied by the address bus.
IN T A (interrupt a
knowledgment): This line is used by the pro
essor to a
knowledge an interrupt.
2
Memory mapped and isolated I/O
Read/Write y les
Interrupt handling
When an external devi
e needs to
ommuni
ate with the pro
essor, it sends a signal through one of
the 8 interrupt inputs of the 8259. (Ideally, only one devi
e should be atta
hed to ea
h of the 8 inputs
labeled IRQ0, IRQ1 . . . . Otherwise an interrupt
oni
t
an o
ur.)
Seeing the interrupt request from the external devi
e, the 8259 sets the INTR line of the 8088
high. At the same time it pla
es a number on the data bus identifying the input line through whi
h
it re
eived the request.
If the data byte put on the data bus by the interrupt
ontroller is n, the pro
essor assumes that
memory lo
ations 0:n×4 and 0:n×4 +1
ontain the IP. The lo
ations 0:n×4+2 and 0:n×4+3 are
assumed to
ontain CS. This
ombination of IP:CS determines the interrupt ve
tor.
Assignment of hardware interrupts to various devi
es
an be viewed in PCs running Windows XP
by sele
ting
ontrol panel, system, devi
e manager, properties and interrupt request as shown below.
3
For example, if IRQ5 line is a
tivated by an external devi
e, the 8559 sets the INTR high and
puts the number 0Dh (or 13 in de
imal) on the data bus. Then the pro
essor fet
hes two bytes from
addresses 0:34 and 0:35 and loads them in IP. Two bytes from 0:36 and 0:37 are loaded in CS.
Interrupt Type Name Comments
0 divide by 0
1 single step
2 NMI
3 breakpoint
4 overow
5 print s
reen
6 unused Software interrupts
7 unused Software interrupts are very similar to
8 IRQ0 - time of day hardware interrupts. One important dif-
9 IRQ1 - key board feren
e is that they are generated by a
A IRQ2 software instru
tion of the form INT n
B IRQ3 - COM2 8259A instead of a hardware signal. The num-
C IRQ4 - COM1 interrupt ber n whi
h follows INT is used to deter-
D IRQ5 - unused lines mine the lo
ation of the ve
tor, exa
tly
E IRQ6 - diskette the way it is done in hardware interrupts.
F IRQ7 - LPT1 The interupt assignment s
heme in the
10 video I/O original IBM PC is shown in the table.
11 equipment Modern PCs have more hardware IRQ
12 memory lines and therefore this table is dierent
13 disk I/O for them.
14 serial I/O
15
assette BIOS
16 keyboard I/O entry
17 printer points
18 resident BASIC
19 bootstrap
1A time of day