8087
8087
8087
Control Unit
Execution Unit
Vcc
CLK 79 0 TAG TAG
0 register
BHE/S7 TAG 7
Bus
tracking Floating point arithmetic module
AD15 - AD0 control
logic, Status Register 16 bit
A19/S6 __ A16/S3 instruction
queue Control Register
QS1-QS0
____ ____ 16 LBS of instruction address
RQ/GT
____ ____0 4MSB inst address 0 11 LSB of op code
RQ/GT1 16 LSB of operand address
Busy
Ready 4 MSB of operand address 0
Reset vss
M. Krishna Kumar MM/M4/LU10/V1/2004 5
Block Diagram of 8087
Control Unit Numeric execution unit
B C3 ST C2 C1 C0 ES PE UE OE ZE DE IE
IC RC PC PM UM OM ZM DM IM
• IC Infinity control
• RC Rounding control
• PC Precision control
• PM Precision control
• UM Underflow mask
• OM Overflow mask
• ZM Division by zero mask
• DM Denormalized operand mask
• IM Invalid operand mask
INT INTR
8259A
8086 CPU
PIC Multi
CLK
____ ____ 8086
RQ/GT1 master
Multi
BUS System
_______
IRn
QS0 QS1 TEST master INTER- bus
FACING
local
COMPO-
8284A bus
QS1 BUSY NENTS
QS0
CLICK ____ _____
RQ/GT0
GENERATOR
CLK CLK 8087
____ _____
INT RQ/GT1
¾ When the 8087 is using the buses for its data transfer, it
____ ___
sends another low-going pulse out on its RQ/ GT0 pin to
8086 to know it can have the buses back again.
The next type of the synchronization between the host
processor and the coprocessor is that required to make sure the
8086 hast does not attempt to execute the next instruction before
the 8087 has completed an instruction.
(a)
(b)