Chip Design Lecture4

Chip Design
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2018 Synopsys, Inc. All rights reserved.
Chip Design
Lecture - 4
1 Developed By: Vazgen Melikyan
Course Overview
 Introduction to Chip Design  Physical Data Preparation

 1 lecture  3 lectures
 IC Manufacturing Process  Liberty Format
 Phases of IC Design  Liberty NCX Introduction
 1 lecture  1 lecture
 Cell-Level Digital Design Flow  Transistor level description
 2 lectures  1 lecture
 Digital Design Flow  Physical Design Formats
 2 lectures  2 lectures
 Library/IP design  Functional Description
Chip Design
Lecture - 4
Developed By: Vazgen Melikyan
2
Cell-Level Digital Design Flow

Chip Design
Lecture - 4
3 Developed By: Vazgen Melikyan
Design Flow Concept
Specification Data from the
previous level
Level 1
Operation
Level 2 needed
no Meets
the
spec?
Level n
yes
Next level
Completed
Design
Chip Design
Lecture - 4
4
IC Design Types
 Digital Standard Cells

 Basic cells performing simplest functions (e.g. AND, OR, etc.) or more
complex functions (Multiplexers, Latches, Flip-Flops, etc.) used as
building blocks for large digital circuits
 Intellectual Property (IP) Blocks
 Large blocks performing completed functions (DAC, ADC, PLL, etc),
used in large designs
 Input/Output (I/O) Cells
 Implements the connection between IC inner circuitry and external
environment (PCB)
 Digital ICs
 Large ICs (e.g. processor, GPU, etc.), distributed to end-users
Chip Design
Lecture - 4
5
Custom Design Flow
Layout design
DRC Checking
Specification
DRC
Schematic design
LVS Checking
Simulation
LVS
no Parasitic Extraction
Meets the
spec? Simulation
yes no
Meets the
spec?
Completed design

Chip Design
Lecture - 4
6
Specification Example
N0 Parameter description Min Typ Max Units
1. Process 3.3V IO devices in TSMC 0.11
2. Resolution 9 10 Bits
3. Conversion Rate 200 400 MHz
4. Input Clock Frequency 200 400 MHz
5. Integral Nonlinearity 1 LSB
6. Differential Nonlinearity 0.5 LSB
7. Gain Error 5 %FSR
8. Offset error 5 %FSR
9. Signal to Noise Ratio 56 62 DBc
10. Harmonic Distortion -60 DBc
11. Temperature Drift 12 ppm/C
12. Reference Voltage 1.25 V
13. Analog Input Voltage 1.6 V
14. Power Supply Voltage1 0.8 1.1 1.22 V
15. Power Supply Voltage2 3 3.3 3.6 V
16. Power Dissipation 125 180 mW
17. Operating Temperature 0 125 °C
18. Spurious Free Dynamic Range -10 dB
19. Effective Resolution Band Width 6 MHz
20. Clock jitter 28 Ps

Chip Design
Lecture - 4
7
Circuit Selection
 Usually a known circuit structure is selected

 Design can find a convenient structure which is known to be good
for the problem being solved
VDD
M2
A A
Input Output
M1

Chip Design
Lecture - 4
8
Schematic Design
Specification
Operating Schematic design

conditions
Simulator Simulation task
Parameter values Waveforms

Delay=1.2n
Power=2.3p
Parameter
specification Check if the
results meet
the spec
yes
Layout Design

Chip Design
Lecture - 4
9
Parametric Optimization
 Each device has configurable parameters

 Schematic designer changes these parameters
to get a circuit which meets the spec
L
W
L
R=
L HW
H
n+ n+
p-Si W
W - gate width, L - gate length W - resistor width, L - resistor length
Transistor gate width and length, or resistor dimensions can be changed to change
their electrical characteristics.

Chip Design
Lecture - 4
10
Example of Circuit

Chip Design
Lecture - 4
11
Layout Design
 Place devices present in schematic and

connect to each other according to schematic
 Do necessary actions to ensure that Layout
will not affect circuit operation
 Ensure that Layout does not violate
fabrication rules.
The aim of Layout design is to lay out a physical view of the schematic, which will
operate the same way.

Chip Design
Lecture - 4
12
Layout Design (2)
supply
supply
output
input output
input
ground
ground
N+ Active N_Well Polysilicon
P+ Active Diffuse Metal1

Chip Design
Lecture - 4
13
Transistor Layout
NFET Polysilicon n+ diffusion

Chip Design
Lecture - 4
14
Example of Layout

Chip Design
Lecture - 4
15
Layout Design Rules
Layout is constrained by the design rules given

by fabrication process
Alignment
min. poly overlap of diffusion

exact contact size
min. contact overlap
min. gate to contact spacing

Chip Design
Lecture - 4
16
Design Rule Check (DRC)
To ensure that Layout does not violate design

rules there is a program that can check this
Contact not
Layout
covered by
metal
Design rules
DRC Checker
from fabrication
Error? Yes
Minimum
No spacing
Next step violation

Chip Design
Lecture - 4
17
Layout Versus Schematic (LVS)
Layout design
LVS
Schematic
and layout
No represent
same circuit?
Yes
Next step

Chip Design
Lecture - 4
18
Layout Parasitic Extraction (LPE)
There is a parasitic extractor tool which calculates parasitic
devices present in layout adds them back to circuit
Extracted
Netlist
Parasitic
Extraction tool

Chip Design
Lecture - 4
19
Simulation of Extracted Netlist
Extracted Layout design

Netlist
LPE
Simulation
Simulation task
Results
Do
parameters
No meet the
spec?
Yes
Next step

Chip Design
Lecture - 4
20
Deliverables
 Completed design is a set of files which

represent different design views:
 SPICE netlist format is used to deliver schematic view
 GDSII binary format is used to deliver layout of the circuit
Schematic View Layout
SPICE Description GDSII

Chip Design
Lecture - 4
21
SPICE Description Example
 SPICE is a hardware description language (HDL) which

enables to describe circuit at device level
 It has text-based format so is readable and can be easily
modified
vdd
T2 Inverter.sp
NFIN=4
L=0.014μm
.subckt inverter
out Xmt1 out in vdd n08 l = 0.014u nfin = 4
in
Xmt2 out in vdd p08 l = 0.014u nfin = 4
T2 .ends
NFIN=4
L=0.014μm
vss

Chip Design
Lecture - 4
22
An Example of GDSII file
GDSII is binary format, therefore it is not

readable
Inverter.gds
02000200 60000201 1C000300 02000600 ...........`.... 000000
01000E00 02000200 60002500 01000E00 .....%.`........ 000010
42494C45 4C504D41 58450602 12002500 .%....EXAMPLELIB 000020
413E0503 14000300 02220600 59524152 RARY..".......>A 000030
1C00545A 9BA02FB8 4439EFA7 C64B3789 .7K...9D./..ZT.. 00004
60000000 01000E00 02000200 60000205 ...`...........` 000050
58450606 0C001100 01000E00 02000200 ..............EX 000060
0100020D 06000008 04000045 4C504D41 AMPLE........... 000070
0000F0D8 FFFF0310 2C000000 020E0600 .......,........ 000080
FFFF204E 00001027 0000204E 00001027 '...N ..'...N .. 000090
0000F0D8 FFFFF0D8 FFFFF0D8 FFFFF0D8 ................ 0000A0
00000004 04000007 04000011 04001027 '............... 0000B0
00000000 00000000 00000000 00000000 ................ 0000C0

Chip Design
Lecture - 4
23
Cell Based Automated Design
Process
process begin
wait until not
RTL / Logic
CLOCK'stable
Design and CLOCK=1;
if(ENABLE='1') then
TOGGLE<= not
Rules TOGGLE;
end if;
end process;
Cell Library
EDA Tools
Design

Chip Design
Lecture - 4
24
Standard Cell Example: Inverter
in out

Chip Design
Lecture - 4
25
Standard Cell Physical Structure
 Cells are placed in rows, next to each other

 One cells structure continue previous one
 Cells on neighbor rows are flipped so that they can share same
supply
VDD VDD VDD VDD VDD
SAED14_MUX2_2
SAED14_AOI211
SAED14_FDPQB
SAED14_AN2_2
SAED14_INV_1
Placement Rows
_V2_8
_0.5
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS
SAED14_MUX2_2
SAED14_BUF_10
SAED14_NR2B_0.5
SAED14_ND2_12
SAED14_INV_1
SAED14_INV_1
SAED14_EO3_4
VDD VDD VDD VDD VDD VDD VDD

Chip Design
Lecture - 4
26
DSCL Content Selection
a a
 In libraries it is necessary to have b b
various cells and various variants
of a cell for optimization. c c
d d
 Cells are selected with different Area = 4
Area = 6
functions to achieve small number of
cells in design with optimal number of
cells in DSCL
a&b&c
a Area = 8
 Cells performing same function should a
b b
be present with multiple inputs c
 In order for cells to be able to drive large
number of other cells connected to Area = 6
output cells with different fan-out are
added
a a
b 1X b
4X

Chip Design
Lecture - 4
27
Basic Steps of Synthesis
Circuit description y=(a+b)&(c d)&e
Logic Synthesis
a
b y
Logic Circuit c
d
e
Physical Synthesis
Layout of finished design

Chip Design
Lecture - 4
28
Logic Synthesis
Logic synthesis is the process which produces logic circuit

from circuit description
Circuit description Standard cells
y : output; AND
a,b,c : input;
y= (a+b)*c; OR
Logic synthesis
a
b
c
Chip Design
Lecture - 4
29
Physical Synthesis
Physical synthesis is the process that produces

layout of logic circuit.
Standard cell
Circuit
layouts
a AND
b
c OR
Physical synthesis

Chip Design
Lecture - 4
30
Physical Synthesis Steps
 Floorplanning
 Placement
 Routing

Chip Design
Lecture - 4
31
Floorplanning
During the floorplanning step the overall cell is

defined, including: cell size, supply network,
etc.
Floorplan

Chip Design
Lecture - 4
32
Placement
 Placement – exact placement of modules (modules can

be standard cells, IPs).
 The goal is to minimize the total area and interconnect
length
Cells from a circuit Floorplan Placed design

Chip Design
Lecture - 4
33
Unit tile
 Placement uses grid in

which cells are placed unit tile
(site)
 Floorplaning uses ‘unit BUF FF
tile’ cell to build this grid

NOR
 Unit tile is defined by a library
developer INV
 All the cells in the library are

designed to be multiple to unit
tile
Chip Design
Lecture - 4
34
Routing
 Routing connects placed cells according to schematic

 The goal is minimal impact of interconnects on circuit
operation
Placed design Routed design

Chip Design
Lecture - 4
35
Digital IC Design Flow
Cell description coding
Specification Synopsys Tools
(RTL)
Description simulation Simulation tool

VCS
Logic Synthesis Synthesis tool
Design Compiler
Formal Verification Formal verification tool
(RTL Vs Gate level circuit)
Formality
Pre-layout STA STA tool
PrimeTime
Timing
no OK?
yes
Floorplanning, Physical synthesis tool
Placement & Routing
IC Compiler
Post-layout STA STA tool
no Timing PrimeTime
OK?
yes
Finished design

Chip Design
Lecture - 4
36
Design Environment of Logic
Synthesis input A, B, C;
output X; (Verilog / VHDL)
Physical Design
if (A) X = B | C;
(Physical synthesis tool)
Design RTL else X = B & C;
description
Specification Gate-level
Logic Synthesis
Netlist
Design
Constraints (Verilog / VHDL)
input A, B, C;
output reg X;
…..
• clock period Digital Standard
IP cell library and2 U1 (.I0(B), .I1(C), .Z(T1);
• input delay
Cell Library
or2 U2 (.I0(B), .I1(C), .Z(T2);
• output delay
Logic Models
• load 0.25
•……….

Chip Design
Lecture - 4
37
Design Environment of Physical
Synthesis
Technological Data
Logic Synthesis
(Synthesis tool) Design Rules
Parasitics Models
Gate-level Netlist
(Verilog / VHDL)
Physical Design Layout

(Physical design tool)
Design Constraints
Digital Standard
IP cell library
Cell Library
Physical Descriptions

Chip Design
Lecture - 4
38
Necessary Data For Digital Design
Flow Cell description coding Specification
Cell logic models, containing cell Description simulation

functionality, pins, area, timing,
power
Used for circuit constructions, Logic Synthesis
timing, power and area optimizations
Formal Verification
(RTL Vs Gates)
Pre-layout STA
Cell physical model (Abstract
Cell Library view): cell size, pin locations, pin no Timing
OK?
directions
Used by physical synthesis
yes
Cell physical view: Original cell Floorplanning,
layout Placement & Routing
Used to build layout of finished
design Post-layout Simulation
Cell descriptions: Behavioral no Timing yes Finished

(Verilog) and transistor OK? design
level(SPICE)
Used to simulate completed design
at the required level

Chip Design
Lecture - 4
39
Cell Logic Model
 Cell logic model is generated by characterization

process
 Cell model contains
 Cell name, pins, pin directions A Z
 Functionality Functionality
 Timing parameters B Parameters
 Power parameters
 Other parameters if needed by EDA tool
 Pin capacitances
 etc.

Chip Design
Lecture - 4
40
Characterization Goal
 Characterization computes cell parameter (e.g. delay, output current)

depending on input variables: output load, input slew, etc.
 Characterization is preformed for various combinations of operating
conditions: process, voltage, temperature (also called PVT corners).
slew
Input Slew slew
0.7
0.7 0.5 Process: Fast
slew Temp: 125o
0.7 0.5 Voltage: 1.32v
0.2
Iout
0.5 0.2 Process: Slow
0.1
Temp: -40o
0.2 0.1 .023 .047 .065 .078 .091 Voltage: 1.08v
Cchar output cap
0.1 .023 .047 .065 .078 .091 Process: Typical
output cap
Temp: 25o
.023 .047 .065 .078 .091 Voltage: 1.2v
output cap

Chip Design
Lecture - 4
41
Characterization Flow
Extracted netlists Characterization task Cell functionality data
Characterization tool
Timing Characterization
(transition, delay, setup, hold, recovery,
removal times)
Power Characterization
(dynamic power, leakage)
Other Parameter Characterization

(variability, etc.)
Characterized library
(*.LIB, *.DB,)
Chip Design
Lecture - 4
42
Characterization Corners
Process Temperature (0C)
Corner Name/
# (NFET proc. – Power Supply (V)
Library Name Suffix
PFET proc.)
Typical Characterization Corners
1 tt0p8v25c Typical - Typical 0.8 25
3 tt0p8vm40c Typical - Typical 0.8 -40
4 ss0p72v25c Slow - Slow 0.72 25
5 ss0p72v125c Slow - Slow 0.72 125
6 ss0p72vm40c Slow - Slow 0.72 -40
7 ff0p88v25c Fast - Fast 0.88 25
8 ff0p88v125c Fast - Fast 0.88 125
9 ff0p88vm40c Fast - Fast 0.88 -40
Low Voltage Operating Conditions
12 tt0p6vm40c Typical - Typical 0.65 -40
13 ss0p6v25c Slow - Slow 0.6 25
14 ss0p6v125c Slow - Slow 0.6 125
15 ss0p6vm40c Slow - Slow 0.6 -40
16 ff0p7v25c Fast - Fast 0.7 25
17 ff0p7v125c Fast - Fast 0.7 125
18 ff0p7vm40c Fast - Fast 0.7 -40
Chip Design
Lecture - 4
43
Cell Library Logic Model File
 Synopsys Liberty Format (.lib) library (saed14rvt_tt0p8v125c){

delay_model : table_lookup;
 Library (.lib) is a text file cell(SAEDRVT14_AN2_0P5) {
area : 0.3552;
pin(A1) {
 Content: direction : input;
}
 Cell Function pin(A2) {
direction : input;
 Delays }
pin(X) {
 Rise/Fall Times direction : output;
function : "A&B";
timing() {
 Cell Area related_pin : “A1" ;
timing_type : "combinational" ;
 Pin Directions cell_rise(…) { values(“0.00869, 0.01280"}
rise_transition(…) { values("0.02069, 0.03315"}
 Pin Capacitances cell_fall(…) { values("0.0720, 0.2060"); }
fall_transition(...) { values("0.02187, 0.03333"); }
 etc. }
}
} /* end of cell */
} /* end of library*/

Chip Design
Lecture - 4
44
FRAM (Abstract) View of Cell
Abstract views contain only minimal data needed for

placement and routing.
VDD VDD
A B A B Metal
Pins
Y Y
NAND_1
GND GND
Layout View Abstract View
Chip Design
Lecture - 4
45
Library Exchange Format (LEF)
 LEF file is the text-based MACRO single_port_bbb

CLASS BLOCK ;
format containing cell FOREIGN single_port_bbb ;
ORIGIN 0 0 ;
physical abstract
SIZE 774 BY 547 ;
SYMMETRY X Y R90 ;
PIN OUT
model contents DIRECTION INPUT ;
USE SIGNAL ;
PORT
 Cell geometries LAYER M3 ;
RECT 420.180 625.650 420.960 625.810 ;
 Pin geometries END
END OUT
OBS
 Blockages LAYER M1 ;
RECT 0.000 0.000 774.000 547.000 ;
 Pin antenna information END
END single_port_bbb
 …
Chip Design
Lecture - 4
46
Library Data (Library Deliverables)
 Two types of deliverables

 Data: views, files
 Needed by the design flow or process in which cells are to be
used
 Documentation, reports, etc.
 Needed by library users to be introduced to library

Chip Design
Lecture - 4
47
Digital Standard Cell Library
Deliverables
 Logic libraries: Timing, Power
 Footprint (LEF/FRAM) Physical Libraries
 Library GDSII Layouts
 SPICE netlists
 Verilog/VHDL simulation models
 Databook in PDF format
 Datasheets containing timing tables (HTML)
 Layouts’ Design Rule Check (DRC) Reports
 Layout versus Schematics (LVS) Check reports
 Simulation results

Chip Design
Lecture - 4
48

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Chip Design

Professor: Sci.D., Professor

Synopsys University Courseware

 Introduction to Chip Design  Physical Data Preparation

Synopsys University Courseware

 Digital Standard Cells

Synopsys University Courseware

16. Power Dissipation 125 180 mW

17. Operating Temperature 0 125 °C

18. Spurious Free Dynamic Range -10 dB

19. Effective Resolution Band Width 6 MHz

20. Clock jitter 28 Ps

Synopsys University Courseware

 Usually a known circuit structure is selected

Synopsys University Courseware

Operating Schematic design

Simulator Simulation task

Parameter values Waveforms

Synopsys University Courseware

 Each device has configurable parameters

W - gate width, L - gate length W - resistor width, L - resistor length

Synopsys University Courseware

Synopsys University Courseware

 Place devices present in schematic and

Synopsys University Courseware

N+ Active N_Well Polysilicon

P+ Active Diffuse Metal1

Synopsys University Courseware

NFET Polysilicon n+ diffusion

Synopsys University Courseware

Synopsys University Courseware

Layout is constrained by the design rules given

min. poly overlap of diffusion

min. contact overlap

min. gate to contact spacing

To ensure that Layout does not violate design

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Extracted Layout design

Synopsys University Courseware

 Completed design is a set of files which

Schematic View Layout

SPICE Description GDSII

Synopsys University Courseware

 SPICE is a hardware description language (HDL) which

Synopsys University Courseware

GDSII is binary format, therefore it is not

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Cells are placed in rows, next to each other

Synopsys University Courseware

Synopsys University Courseware

Circuit description y=(a+b)&(c d)&e

Layout of finished design

Synopsys University Courseware

Logic synthesis is the process which produces logic circuit

Physical synthesis is the process that produces