Wichip Hut Chip Design
Wichip Hut Chip Design
Wichip Hut Chip Design
1
Design flow
2
Engineering
ideas
Historical Technology
WICHIP 3
Engineering
ideas
SRAM
uP Core
Flash
SRAM
uP Core
ROM SRAM FIFO
MPEG
Logic ROM Serial
Design Methodology
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Engineering
ideas
Virtual Component
Reuse
Socketized Functions for
Core Reuse Plug & Play Integration
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Engineering
ideas
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Engineering
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Engineering
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Specification Problem
Spec. Documentation
Less cost when early phase of design
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Engineering
ideas
Purpose of Specification
Specification for Integration
Functional/Physical/ Design requirements
The Block diagram
Interfaces to external system
Manufacturing test methodology
Software model
Software requirements
Specification for Block Design
Algorithm Spec
Interface Spec
Authoring Guide
Test Spec Lint & Coverage
Synthesis Constraints
Verification Environment, Tools Used
WICHIP 9
Engineering
ideas
Types of Specifications
Formal Specification
Desired characteristic (functionality, timing, power, area,), independent
to implementation
Not widely used, important research topic
Executable Specification
Description of Functional behavior
Parallel with RTL Model in the TestBench
Fast Feed-Back
Higher Level : C/C++(SpecC, SystemC), SDL, etc.,
Lower Level : VerilogHDL, VHDL,
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Engineering
ideas
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Engineering
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Engineering
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From FPGA to ASIC:
Design Flow
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Engineering
ideas
Front-End Procedure
Overall procedure
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Engineering
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Back-End Procedure
Overall procedure
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Engineering
ideas
Back-End Procedure
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Design Example 1
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Engineering
ideas
plcp_tx_data
pulse_shape_re
plcp_data_vld
conv pilot guardtime data pulse
scrambler interleaver mapper ifft pulse_shape_im
encoder insertion insertion selection shaping
plcp sig_vld
pulse_shape_vld
plcp_tail_vld
clk
preamble
rst_n tx_control
generator
BLOCK 1 BLOCK 2
WICHIP 19
Engineering
ideas
plcp_tx
conv_enco der
243 clo ck
interleaver
51 clock / 99 c lo c k / 195 c loc k 241 c loc k
mapp er
51 c lock
p ilot_insertion
c loc k
142 c loc k
ifft
49 c lo ck
guardtime_insertion
3 c lo c k
data_selection
p reamble_start
S x x7 x4 1
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Engineering
ideas
clk
rst_n
sig_in_vld
data_in_vld
tail_vld
in_data
out_sig_vld
out_data_vld
out_data
out_vld
0 0 0 0 0 0
out_data
sc rambled
sc rambled data tail bits(all z eros) data
WICHIP 22
Engineering
ideas
802.11a Receiver
g uardtime
sync fft pilot_extract rx_buffer equalizer demapper deinterleaver viterbi descrambler
remove
plcp_rx
rx_c ontrol
BLOCK 1 BLOCK 2
WICHIP 23
Engineering
ideas
sync
65 clock
pilot_extract
2 clock
rx_buffer
51 clock
demapper
1 clock
deinterleaver
110 clock
viterbi
1 clock
descram
48 clock
plcp_rx
662 clock
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Verification
27
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Output
data
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Engineering
ideas
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Engineering
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Engineering
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Engineering
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Engineering
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WICHIP 40
Emulation
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Engineering
ideas
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Engineering
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Engineering
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Engineering
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Engineering
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Area Report
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Thanks and Cheers
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