IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.

3, MARCH 1997 357

The Modeling, Characterization, and Design

of Monolithic Inductors for Silicon RF IC’s
John R. Long, Member, IEEE, and Miles A. Copeland, Fellow, IEEE

Abstract—The results of a comprehensive investigation into the tion. The accuracy of the lumped element model is evaluated
characteristics and optimization of inductors fabricated with the for variations in metallization thickness, layout geometry, and
top-level metal of a submicron silicon VLSI process are presented. substrate parameters, using a combination of three-dimensional
A computer program which extracts a physics-based model of
microstrip components that is suitable for circuit (SPICE) sim- (3-D) numerical simulations and experimental measurements.
ulation has been used to evaluate the effect of variations in The results of this investigation highlight areas where process
metallization, layout geometry, and substrate parameters upon improvements and parameter optimization can be applied to
monolithic inductor performance. Three-dimensional (3-D) nu- maximize the performance of RF circuits using silicon-based
merical simulations and experimental measurements of inductors inductor designs. Some design guidelines for maximizing the
were also used to benchmark the model accuracy. It is shown in
Q
this work that low inductor is primarily due to the restrictions inductor performance in similar technologies will also be
imposed by the thin interconnect metallization available in most described.
very large scale integration (VLSI) technologies, and that com-
puter optimization of the inductor layout can be used to achieve
Q
a 50% improvement in component -factor over unoptimized
II. THE MONOLITHIC INDUCTOR
designs. Resonant-tuned (LC) circuits offer numerous benefits to the
Index Terms— Computer-aided design, HF analog integrated designer of high-frequency circuits. Operation at a low supply
circuits, MMIC’s, modeling, monolithic inductors, RFIC’s, silicon voltage, simplified impedance matching between stages, and
integrated circuit technology. low dissipation for reduced circuit noise are just a few of the
properties of LC circuits that can be exploited to achieve a
higher level of performance from a given fabrication tech-
I. INTRODUCTION
nology. However, an on-chip inductance is required for the

R ADIO frequency (RF) circuits fabricated in monolithic

microwave integrated circuit technologies (such as GaAs
MMIC) make extensive use of on-chip transmission lines to
realization of LC networks for these purposes. At radio and
microwave frequencies, a purely passive inductor is often
preferable to synthesis of an inductive reactance with an active
realize an inductance, the inductor being a key component in circuit. Passive components introduce less noise, consume less
many high-performance narrowband circuit designs. Silicon power, and have a wider bandwidth and linear operating range
IC technologies have rarely been used for analog applications than their electronic equivalents, such as the gyrator.
in the radio and microwave range of frequencies, primarily Passive inductors can be implemented on-chip using trans-
because transmission line structures perform poorly on the mission lines. The input impedance ( ) of a short section of
semiconducting substrates used to manufacture silicon IC’s transmission line which is terminated in a short circuit can be
[1]. In order to exploit the capabilities offered by a monolithic written as follows:
inductance, the limitations imposed by silicon technology upon
the component performance must be accurately modeled and (1)
characterized. The ability to optimize and refine silicon circuit
where is the characteristic impedance and is the propa-
designs incorporating on-chip inductors has been identified by
gation constant for a transmission line of length, . Here it is
others [2] as lacking in the present state of the design art.
assumed that the physical length of the line is shorter than one-
A computationally efficient, scalable, lumped-element
tenth of a wavelength at the desired frequency of operation,
model which can be applied to an arbitrary configuration
that is, the line appears to be “electrically short.” From (1), the
of microstrip transmission lines, such as the monolithic spiral
input impedance will be either resistive or inductive, depend-
inductor [3]–[5], will be described in this paper. An efficient
ing upon the value of the resistance/unit length, , compared
and scalable inductor model can be used to rapidly optimize
to the inductance/unit length, , of the transmission line. For
the electrical performance of an inductor for an RF IC applica-
low resistivity metals such as the interconnect metallization
Manuscript received August 15, 1996; revised October 28, 1996. This work used on an integrated circuit chip, the input impedance can
was supported by Micronet, the Natural Sciences and Engineering Research be made to appear predominantly inductive. The ratio of the
Council of Canada (NSERC), and the Telecommunications Research Institute
of Ontario (TRIO). series inductance to shunt capacitance per unit length defines
J. R. Long is with the Department of Electrical and Computer Engineering, the characteristic impedance ( ) of the transmission line.
University of Toronto, Toronto, ON, M5S 3G4 Canada. Maximizing the characteristic impedance (e.g., using a narrow
M. A. Copeland is with the Department of Electronics, Carleton University,
Ottawa, ON, Canada. metal line) will reduce the length of line that is required to
Publisher Item Identifier S 0018-9200(97)01294-8. realize a given inductance.
0018–9200/97$10.00  1997 IEEE

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358 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

The microstrip transmission line structure on a silicon IC using a microstrip transmission line wound as a square spiral,
consists of a metal strip above a conducting (or ground) and their electrical behavior was modeled adequately by
plane, with the substrate and intermetal oxide layers sand- a lumped inductance with a few additional parasitic (RC)
wiched between the two conductors. For dimensions typically components. Some simple LC filtering and signal processing
encountered in a commercial IC fabrication process (metal circuits using these inductors were also demonstrated [11],
linewidths between 5–50 m on a 350- m thick substrate), [12], although the performance of the circuits was limited by
the characteristic impedance of a microstrip line ranges from the low of the inductors, which was less than five. Silicon
approximately 100–200 . The substrate behavior depends RF integrated circuits incorporating monolithic inductors for
upon both the resistivity and the frequency of the propa- product applications have subsequently been developed and
gating wave. However, the substrate tends to behave as a demonstrated by a number of manufacturers [13]–[15].
lossy dielectric in modern silicon very large scale integration The characteristics of inductors fabricated in various silicon
(VLSI) processes [6], where resistivities are typically in the technologies have been studied and reported in the literature.
1–100 -cm range and operation is in the GHz range of The main motivation behind these studies has been improve-
frequencies. ment in the inductor quality through a modification of the
The largest inductive reactance that can be realized on-chip metallization scheme and/or the properties of the underlying
is determined from the following equation: substrate. The methods which have been employed to date
have included: thicker metallization [16], stacking of metal
Inductive reactance (2) layers in a multilevel metal process [17], thicker intermetal
oxide [18], fabrication using high-resistivity silicon substrates
where is the transmission line length and is the guided [16], and the selective removal of silicon from beneath the
wavelength. A short transmission line (i.e., less than one- inductor structure by chemical etching [19]. Justification for
tenth of a wavelength long) is assumed here, with a maximum these experimental investigations has come from a heuristic
characteristic impedance of 200 . The inductive reactance assessment of the parameters limiting inductor performance
from (2) corresponds to an inductance of 20 nH at a frequency or from numerical simulations of the inductor’s electrical
of 1 GHz. This is close to the upper limit that can be realized characteristics using commercially available electromagnetic
monolithically in a standard silicon process. The smallest field solvers.
inductance value for most practical circuit applications in the
1–3 GHz range of frequencies is on the order of 1 nH. The
losses introduced by the semiconducting substrate in a silicon IV. SILICON MONOLITHIC INDUCTOR MODEL
IC technology restrict the -factor to less than ten for most
A circuit model which describes the electrical behavior of
commercial IC processes.
the monolithic inductor at RF and microwave frequencies
In addition to the rectangular geometry used here, circular
is required for the computer simulation and optimization of
and octagonal geometries are also widely used to implement
tuned circuits fabricated in silicon IC technologies. Modeling
microstrip spiral inductors. Although an improvement in -
of spiral inductors on silicon has been limited to reports of
factor of up to 10% is possible using a circular rather than
numerical simulation results [20] and/or parameter fitting of
square design, the circular spiral consumes greater chip area,
lumped-element equivalent circuits to measured data [16],
and introduces difficulties in the efficient generation of pho-
[17]. Electrical circuit models for an inductor that are derived
tomasks [7], [8]. In addition, the interaction between the
in this way cannot be scaled to reflect changes in the layout
magnetic field components on adjacent sides of a nonrectan-
or fabrication technology.
gular spiral inductor adds extra complexity to the development
Numerical simulators are now commercially available [21]
of a circuit model. Thus, only the rectangular spiral inductor
which compute the electromagnetic field distribution of planar-
will be considered in the following discussion.
type conductor configurations in three dimensions. These
The spiral inductor structure, while compact and more
simulators can extract the circuit parameters (i.e., RLCG
space efficient than an equivalent straight wire inductor, is
parameters) of the spiral inductor from the field solutions
more difficult to analyze. The accurate characterization of this
for use in a circuit simulator such as SPICE. However,
structure at microwave frequencies requires an analysis of
a disadvantage of 3-D numerical simulation is that some
the fringing fields, parasitics, ground plane effects, and most
sophistication on behalf of the user is required in order to get
importantly for silicon IC design, an analysis of the effect
meaningful results. Another drawback is the limitation that
of the conductive substrate on the component performance.
processing speed and memory size place upon the structures
These effects cannot be fully analyzed to yield closed-form
which can be analyzed within a reasonable amount of time.
expressions which adequately predict the inductor behavior,
Optimization of the -factor in a planar structure requires
and hence, numerical analysis is required in order to determine
closely spaced microstrip lines for tight coupling of the
the parameters of the inductor’s electrical model.
magnetic field and wide microstrip lines in order to reduce
the Ohmic losses in the microstrip. Hence, a large ratio of
III. THE MONOLITHIC INDUCTOR IN SILICON TECHNOLOGY linewidth to line spacing is necessary, and this requires a
The performance of rectangular spiral microstrip inductors substantial amount of computer memory and computation
in a 0.8- m silicon BiCMOS technology was reported by time in order to determine the circuit model parameters if a
Nguyen and Meyer in 1990 [10]. The inductors were fabricated commercially available field solver package is employed.

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 359

TABLE I
MICROSTRIP LINE PARAMETERS [24]

Fig. 1. Simplified microstrip spiral inductor layout (three turns).

model from the inductor’s specifications. The parameters of the

A. Scalable Inductor Model lumped-element model for each microstrip line are computed
A scalable inductor circuit model allows the circuit designer from the layout geometry, using the substrate and metallization
the flexibility to tailor the inductor design for a given RF appli- properties. Table I lists the technological parameters for the
cation. Scalability implies that the electrical circuit parameters BiCMOS process [24] used to fabricate the inductors described
of the inductor model can be extracted from geometric and in this paper. The self and mutual inductances for all parallel
technological parameter specifications. A fully scalable model line segments are calculated from closed-form expressions,
will allow any inductance value to be designed for use in an RF where the nonzero metallization thickness is incorporated in
circuit. It also simplifies integration of the model into a typical the self and mutual inductance calculations using the geometric
CAD framework. The ability to generate inductor parameters mean distance of the conductor cross section [25].
on-demand eliminates the need to develop an inductor design The self-inductance, (in nH), of a straight conductor with
library, which can be costly to generate and maintain. a rectangular cross section can be calculated from Grover’s
Ohmic losses in the conductive substrate must be accounted formulation for the mutual inductance between two current
for in the scalable model. These losses can be related to carrying filaments [26]. The self and mutual capacitances are
the three possible modes for the propagation of signals on computed using a two-dimensional (2-D) numerical technique
transmission lines fabricated in the SiO /Si system: the skin- developed for coupled microstrip lines [27]. The shunt re-
effect, slow-wave, and quasi-TEM modes. Lumped-element sistance of the semiconducting layer can then be estimated
equivalent circuits for each propagating mode were proposed directly from the quasistatic capacitance, [6]. Dissipation
by Hasegawa [6], where the shunt parasitic components of of the mutual capacitances is neglected because the microstrip
the microstrip line can be represented (in general) by a lines are closely spaced. The frequency dependent resistance,
combination of two capacitors and a resistor. This simplifying , is approximated from closed form expressions [28] to
approximation can be applied to the spiral inductor as shown form a complete lumped-element equivalent circuit represen-
in Fig. 1, where the inductor is shown as a collection of short tation.
microstrip transmission line sections. Each transmission line As an example of the GEMCAP2 analysis technique, a
section is physically short in length, and is therefore adequately circuit model can be derived for the spiral inductor illustrated
described by a lumped-element model that includes series in Fig. 1. The physical layout of the microstrip spiral is first
elements to model the inductance and resistance per unit length partitioned into groups of multiple coupled lines for analysis;
and shunt elements to model the substrate parasitics and losses. one group per side of the rectangular layout as shown in
These lumped element models are then joined serially to model the figure. The parameters of a lumped-element -equivalent
the entire spiral structure. The electric and magnetic coupling circuit are then extracted for the individual microstrip lines in
between parallel conducting strips must be accounted for in each group. Four such -equivalents are required for a single
the model; however, the weak coupling between orthogonal turn of the spiral, as illustrated in Fig. 2, as well as lumped
strips is neglected in order to reduce the model complexity. capacitors to model mutual capacitive coupling between the
This segmented approach to microstrip inductor modeling lines (represented by capacitors in Fig. 2). Dependent
was originated by Greenhouse [22], refined by others [23], current sources account for the mutual magnetic coupling
and then extended to an arbitrary configuration of orthogonal between parallel strips in a group of coupled lines.
microstrip lines by Rabjohn [3]. The flexibility and computa- As the number of turns of the spiral increases, more lumped
tional efficiency afforded by this approach have been adopted element sections are added to account for the additional
for the scalable inductor model developed in this work. The coupled lines within each group. For an eight-turn spiral
model capabilities have been extended to include the Ohmic inductor with microstrip lines per side, for example,
losses in the conductive substrate. there would be 4 or 32 lumped-element sections in total,
A computer program, GEMCAP2 [3], [4], was used to along with the additional interconnecting elements to model
extract the electrical parameters for a lumped-element circuit the mutual capacitance between strips as in Fig. 2.

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360 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

Fig. 2. Lumped-element circuit model for one turn of a spiral inductor.

Fig. 3. Compact lumped-element circuit model for a spiral inductor ( Nt = 4:5, W = 10 m, S = 5 m).

There are a number of other parasitics and higher-order and passive RF circuit elements. The complete model would
effects which should be taken into consideration. Interwinding normally be reduced to a compact model or -parameter
capacitance to the conductor used to contact the center of the representation for faster optimization of a complex RF cir-
spiral (usually an “underpass” in a multilevel metal process) cuit.
can be modeled using lumped capacitors between the external
terminal and the appropriate lumped-element sections. These B. Compact Inductor Model
capacitors are not shown in Fig. 2. Current crowding at the
A simplified or compact version of the fully scalable induc-
corners of the rectangular spiral adds parasitic inductance and
tor model (i.e., a model with the minimum possible number
capacitance which is accounted for by a connection of lumped of circuit elements) is required for hand calculations and to
elements and at each corner node (note that only facilitate optimization of more complex RF circuit structures.
is shown in Fig. 2). For frequencies in the low GHz For efficient optimization, the compact model should be easily
range, this effect is quite small and is often neglected [29]. derived from the complex scalable model structure.
Coefficients are also added to the dissipative components of A single -type lumped-element section (as shown in Fig. 3)
the model to account for the dependence of the inductor losses has been used by others as a compact model to fit experimental
upon operating temperature. measurements of silicon monolithic inductors [10], [16], [17].
The scalable circuit model can be used directly in a time The , and parameters of the compact model can be
domain (e.g., SPICE transient analysis) or frequency domain established through a combination of parameter identification
(e.g., Touchstone) circuit simulation along with other active and fitting with the aid of a computer-driven optimizer.

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 361

Frlan [30] has shown that the compact model can be the parasitic capacitances have little effect), and then fitting the
estimated directly from the parameters of the scalable model. remaining parameters of the model using a computer-driven
Using this technique, the series resistance and inductance optimizer. Once the compact model parameters have been
of the single -model ( and in Fig. 3) are obtained determined, the inductive reactance, the total dissipation, and
by simply summing the inductance and resistance of each the -factor are easily computed. For example, the -factor of
individual microstrip section connected in series. The para- an inductor connected as a one-port (i.e., with Port 2 in Fig. 3
sitic capacitances of the individual sections can be similarly grounded) can be estimated from the following equation:
summed into a single lumped capacitance for the compact
model, with one shunt arm of the -model representing -factor (3)
the outer windings and the other arm modeling the inner
winding parasitics. Resistances in the compact model
are computed from the shunt capacitance, , making the
complete parameter set consistent. From this initial estimate,
where is the oxide resonant frequency defined by induc-
it is possible to closely match to the electrical characteristics
tance and capacitance . Here the parasitic capacitances
of the scalable model by refinement of the parameters using
and of the compact model have been assumed neg-
a computer optimizer. This approach is simple to implement
ligible in order to simplify the resulting expression. The two
with most commercial simulators that have the capability to
terms in the denominator represent the sources of dissipation in
optimize circuit parameters (e.g., HSPICE or Touchstone), and
the monolithic inductor, which consist of the resistance of the
it requires little additional computation time to refine the small
metal lines ( ) and the dissipation added by the conductive
number of parameters in a single lumped-element section. The
substrate.
component values for the compact model shown in Fig. 3 were
Some insight into the relationships between circuit parame-
derived by estimation and fitting the scalable (GEMCAP2)
ters and the -factor can be gained through examination of (3).
model of a 4.5-turn spiral inductor. The shunt parasitics are
It can be seen that decreasing through the use of a thicker
not symmetric (i.e., is not equal to ), which is a
oxide layer will increase both the oxide resonant frequency
consequence of the asymmetry inherent in the spiral inductor
and the substrate corner frequency, ,
layout. This model is simple enough to be useful for hand
resulting in an improvement in the inductor -factor. Equation
calculations in a circuit and it fits the GEMCAP2 model up to
(3) also predicts that an increase in the substrate resistivity will
the first self-resonant frequency of the inductor. However, the
cause a drop in the factor for frequencies much less than
parameters of the compact model cannot be easily adjusted
and an improvement in -factor for frequencies much
for slight changes in the inductor design because of the
greater than . However, it should be realized that the
nonphysical nature of this simple model.
lumped equivalent model for the inductor shown in Fig. 3 is
invalid when highly conductive substrates are used (less than
C. -Factor Extraction and Computation approximately 1 -cm), and hence (3) can only be used to
from a Compact Model approximate the inductor over a limited range of substrate
resistivities.
The inductor -factor is used as a figure of merit to
compare the performance of the spiral inductors studied in
this work. The factor is defined by the ratio of the inductive V. MODEL VALIDATION
reactance to the total dissipation, , for an equivalent In order to verify the accuracy of the scalable model,
circuit consisting of inductance in series with a resistor the behavior of a spiral inductor predicted by the lumped-
(representing the total dissipation), [31]. A measurement element model (GEMCAP2 simulator) was compared with
or simulation of the impedance parameters for a monolithic a 3-D electromagnetic field simulation. The 3-D numerical
inductor will normally include the effect of capacitive par- simulations were performed using a full-wave simulator for
asitics, and therefore the inductive reactance and the total planar structures [21]. A 4.5-turn square spiral 5 nH inductor
dissipation must be properly identified in order to determine with a 10- m wide line and a 5- m line spacing was selected
the component . For a one-port, the -factor is often esti- for this comparison. The ratio of line width to line spacing
mated by taking the ratio of the imaginary and real components was kept small to ensure that the memory requirements and
of the one-port impedance. While this approximation is valid simulation time for the 3-D numerical computations were not
at low frequencies (less than 500 MHz), a significant error is excessive. It would be possible to optimize the inductor design
caused by the parasitic capacitances of a spiral inductor as the for the best possible circuit performance, such as optimization
frequency increases. This error is avoided by computing the of the inductor -factor, but this is not necessary for model
-factor directly from the parameters of the compact model. validation.
The procedure for compact model extraction from the fully The substrate and metallization parameters from the BiC-
scalable inductor model was outlined in the previous section MOS process from Table I were used to obtain the simulation
of this paper. For experimental data, the compact model results shown in Fig. 4. The inner terminal of the spiral was
parameters (see Fig. 3) are determined by first estimating the connected to ground and the impedance of the resulting one-
inductance, , and series resistance, , from the impedance port network as a function of frequency was computed in
measured between Ports 1 and 2 at low frequency (i.e., where both cases. Excellent agreement is seen between the real

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362 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

Fig. 4. Simulated one-port impedances for a 5 nH inductor ( Nt = 4:5, W = 10 m, S = 5 m).

and imaginary parts of the one-port impedance simulated

using numerical simulation (3-D EM) and the lumped-element
model (GEMCAP2) almost up to the self-resonant frequency
(i.e., where the imaginary part of the impedance is zero).
Both simulations predict a low-frequency inductance (which
is given by the reactive portion of the impedance divided
by the radian frequency) close to 5 nH with a self-resonant
frequency of approximately 10 GHz. The consistent difference
in the reactive component of the impedance is due in part
to the fact that the finite thickness of the conducting strip is
not accounted for in the numerical simulations. An increase
in the conductor thickness causes the inductance, and hence
the inductive reactance, to decrease. At low frequencies, (a) (b)
the resistive component of the impedance is close to the Fig. 5. Inductor layouts used for characterization experiments.
dc resistance of the inductor, which is about 8.5 . As
the frequency increases, the resistive component of the loss to line spacing, while computation time for the lumped-
increases greatly due to losses in the substrate and skin effect element model is unaffected by the choice of line width or
in the metal conductors. line spacing. This fact, combined with the large advantage
Design of an inductor to fit a particular application would in computational efficiency for even simple structures, lends
require extensive simulation work in order to determine the a considerable advantage in both speed and flexibility to the
number of turns, line width, and line spacing necessary to lumped-element modeling approach when compared to 3-D
achieve the best performance within a given technology. numerical simulation.
Extraction of a lumped element component model is faster than
other simulation methods, making this type of optimization VI. EXPERIMENTAL MEASUREMENT
more practical. In this particular example, the computation of The effect of layout geometry, metallization thickness, and
the lumped-element model parameters was performed in less substrate parameters upon the inductor performance has been
than 2 min on a SUN SPARC-2 work station. By compari- investigated experimentally. The number of turns of the rect-
son, 3-D EM simulation of the one-port impedance required angular spiral, the metal line width, and the metal spacing were
approximately 5 min per frequency point on the same work each varied independently in order to determine the effect of
station (equipped with 64 MBytes of RAM), or 50 min for the physical layout upon the inductor performance. In addition,
11 data points between 0.5–10 GHz. It should be noted that the effect of changes in the oxide thickness and the silicon
a large ratio of line width to line spacing is desirable in substrate resistivity were also explored experimentally. A 3.5-
order to maximize the coupling between adjacent microstrip turn spiral inductor with a nominal inductance of 1800 pH
lines in the spiral inductor. The time required for a 3-D (as shown in part (a) of Fig. 5) was used for the metal
numerical simulation increases with the ratio of line width and oxide thickness experiments, while the 4.5-turn 5 nH

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 363

Fig. 6. Q-factor as a function of metal width (L = 5 nH).

inductor (shown in part (b) of the same figure) was used to ues to rise, the dissipation of energy in the semiconducting
characterize the effect of layout and substrate variations upon substrate and the ac resistance of the metallization begin to
the inductor performance. It should be noted that both of these increase faster than the inductive reactance. Thus, the -
designs exploit the large line width to line spacing ratio that factor peaks, and then decreases. The larger surface area
is possible in modern silicon VLSI technologies and would of the inductor with wide conductor metallization results in
require excessively long simulation times if 3-D numerical higher parasitic capacitances, which lowers the inductor self-
simulation were used to predict the inductor behavior. The resonant frequency and increases the substrate dissipation.
results of the experimental measurements are useful as a This confirms the behavior predicted by (3). In addition,
benchmark to confirm the predictions of the lumped-element the distribution of current across the conducting strip is
(i.e., GEMCAP2) computer model and also to provide insight nonuniform as a result of the skin effect, causing the ac
into the possible optimization of different aspects of the resistance of the metallization to increase at higher frequencies.
inductor performance, such as the -factor. As the strip widens, the penalty in ac resistance due to the
The experimental data was collected from on-wafer mea- skin effect will increase at a given frequency [28]. Thus, the
surements of the two-port -parameters for each inductor peak of the inductor -factor shifts to a lower frequency as
test structure using coaxial RF probes. The measured data in the conductor width increases. However, this can be used
each case was fitted to a compact model for the inductor, to advantage in the optimization of a given inductor for the
as described in Section IV-C, and the one-port impedance
maximum within a desired range of frequencies.
parameters (or the -factor) computed from the resulting
The effect of the spacing between conductor lines on
parameter set by grounding Port 2 of the inductor compact
inductor -factor has also been investigated. Narrow line
model (refer to Fig. 3).
spacings were found to increase the magnetic coupling be-
tween windings, which causes an increase in the inductance
A. Inductor Layout (Metal Width, Spacing, and the -factor for a given layout area as shown in Fig. 7.
and Number of Turns) For the thin metallization used to fabricate on-chip inductors,
The measured -factor of a rectangular spiral inductor and interwinding capacitance was found to have a negligible effect
the performance predicted by the lumped-element computer upon the performance as shown in the figure. However, there is
model for conductor widths of 5 and 15 m are shown in a significant improvement in the -factor when the minimum
Fig. 6. A layer of top-level aluminum 1 m thick was used to spacing is used.
fabricate a 4.5-turn spiral with an inductance of 5 nH in each The relationship between the number of turns of the spiral
case. The outside dimensions of the inductor ( in Fig. 1) and the peak -factor for a given inductance was also investi-
were increased in order to maintain a constant inductance gated experimentally, and the results are listed in Table II. The
value in both cases. outer dimensions of the spiral were varied in order to realize
At frequencies well below the peak in the inductor , the an inductance of 5 nH for each design. The line width and line
shunt parasitics of the spiral inductor have little effect and spacing were kept constant at 10 and 1.5 m, respectively. The
consequently the inductive reactance and inductor increase drop in inductor as the number of turns increases is related
with frequency. However, as the operating frequency contin- to the distance (or gap) between opposite sides at the center

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364 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

Fig. 7. Q-factor as a function of metal spacing (L = 5 nH).

TABLE II
NUMBER OF TURNS VERSUS THE PEAK INDUCTOR Q-FACTOR FOR A CONSTANT INDUCTANCE OF 5 nH (W = 10 m, S = 1:5 m)

of the spiral. As the number of turns increases, the spacing fabricated with thicker metal shows close agreement with the
between opposite sides of the spiral shrinks, causing a drop in predictions of the lumped-element circuit model. The -factor
inductance because of negative mutual coupling. Thus, more initially rises with frequency as the reactive component of
metal is required to maintain a constant inductance value of the impedance increases, peaks, and then decreases due to
5 nH, and the total length of the spiral begins to increase as the increasing dissipation of energy at higher frequencies.
seen from the data listed in the table. Increasing the number The inductor -factor at 3 GHz improves from five to ten
of turns reduces the outer dimension of the spiral ( ) and when the thickness of the aluminum metal layer is increased
conserves chip area; however, some space is required at the from 1 to 3 m. The improvement in inductor is less
center of the spiral in order to realize the highest -factor. than a factor of three (as would be expected from resistance
considerations) because the inductance is inversely propor-
tional to the thickness of the conductor. Hence, the inductance
B. Metallization Thickness decreases with increasing metal thickness, lowering the .
Thin metallization in most VLSI processes limits the quality The frequency dependence of the conductor resistance, or
factor of microstrip inductors, because energy is dissipated the skin effect, is more pronounced as the thickness of the
by the finite resistivity of the metallization as well as in metallization is increased, which also contributes to higher
the conductive substrate. The quality of the spiral inductor, dissipation and a lower -factor at RF. The measured behavior
or -factor, could therefore be improved by increasing the of the inductor fabricated with thicker metal also showed close
conductor thickness. The measured quality factor for a 1.8-nH agreement with the predictions of the lumped-element circuit
spiral inductor fabricated with 1–3 m thick metal layers is model. These results indicate that inductors suitable for many
plotted in Fig. 8. This inductor consists of 3.5 turns of 15- m RF IC applications could be fabricated in production silicon
wide top-level metal in the BiCMOS process with a line technologies, if a low resistivity metal of adequate thickness
spacing of 1.5 m. The measured behavior of the inductor were available.

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 365

Fig. 8. Q -factor for different metal thickness (L = 1:8 nH).

The -factor predicted by GEMCAP2 for the same planar The measured behavior of the 5 nH spiral inductor of Fig. 6
spiral on a lossless substrate (Ideal sub.) is also plotted in the is shown in Fig. 10 for two different substrate conductivities
Fig. 8 for comparison. The slight downward curvature is the (10 and 0.01 -cm). A layer of aluminum 1 m thick and
result of capacitive parasitics which cause self-resonance. In 10 m wide was used to fabricate the 4.5-turn spiral in both
addition to ac losses in the metallization, the data shows that cases. At low frequencies, the real or resistive component
the substrate conductivity also introduces a significant degra- of the impedance (Re ) is close to the dc resistance
dation in the component . This demonstrates that the effect of of the inductor, which is about 8.5 . As the frequency
the substrate conduction on the inductor -factor is significant increases, the resistive component increases, primarily due to
at higher frequencies, but also that operation close to the ideal dissipation in the conductive substrate. As seen in the figure,
curve is obtained for frequencies below approximately 1.5 the dissipation of the inductor fabricated on a low resistivity
GHz. These results also indicate that inductors with a -factor substrate (0.01 -cm) is substantially greater than for the
of ten, which is suitable for many RF IC applications, could be substrate resistivity normally used in the BiCMOS process
fabricated in silicon production technologies if a low resistivity (10 -cm). As a result, the peak -factor is reduced by a factor
metal of adequate thickness were available. of two because of the increased dissipation, which makes the
inductor unsuitable for most RF circuit applications.
In Fig. 10, the inductance, which is given by the reactive
C. Substrate Effects portion of the measured impedance (Im ) divided by the
The ability to predict the substrate effects on the inductor frequency, is 5 nH at low frequencies in each case. The effect
performance is key to the design and realization of inductors of parasitic capacitance between the metal and substrate is
with acceptable performance in silicon technology. When larger when a highly doped substrate is used to fabricate the
substrate effects are properly accounted for in a circuit simu- inductor, which leads to a lower self-resonant frequency. The
lation, the inductor design can be optimized to minimize these reactance of the inductor fabricated on the 0.01 -cm substrate
losses and improve circuit performance. In production silicon rises to a peak at 4 GHz and then falls rapidly as the inductor
technologies, an insulating oxide layer separates the top level approaches self-resonance. However, the low frequency in-
metal and the semiconducting silicon wafer. The thickness of ductance is unaffected. Current flow in the substrate beneath
the oxide layer is an important parameter which influences the the spiral would cause negative mutual coupling and thus a
inductor performance. The measured effect of changes in the reduction in the low frequency inductance of the spiral. These
oxide thickness upon the component factor is illustrated in results indicate that the substrate current that is induced by
Fig. 9, for the 1.8 nH inductor discussed previously (refer to the magnetic field is small.
Fig. 8, metal thickness of 3 m). A thicker oxide layer reduces
the parasitic capacitance of the structure, which improves the
inductor self-resonant frequency. This is seen in Fig. 9 as a VII. COMPONENT TOLERANCES
broadening of the inductor -factor with frequency as the It is important to characterize the effects of processing and
oxide thickness increases. Performance closer to that predicted temperature variations upon the parameters of a monolithic
for an ideal (i.e., nonconductive) substrate can be achieved component in order to estimate the yield of working circuits
when the oxide thickness is maximized. that meet the design specifications. Parameter variations due

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366 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

Fig. 9. Q -factor as a function of oxide thickness (L = 1:8 nH).

Fig. 10. Measured one-port impedance versus substrate resistivity (L = 5 nH).

to fluctuations in the ambient temperature should also be small lithographic variations in modern silicon IC processes.
characterized and modeled so that circuit operation over a wide Simulations predict that the tolerance on the self and mutual
temperature range can be ensured during the design phase. inductances of the inductors described in this study will be
Thus, the processing and temperature induced tolerances in less than 3% for a 0.2 m change in the line width and line
the behavior of the monolithic inductor and transformer are of spacing. A larger and more subtle tolerance is introduced by
interest to the RF circuit designer. variations in the intermetal oxide thickness and changes in sub-
The metal lines used in the inductor or transformer layout strate resistivity, both of which affect the parasitic capacitances
have dimensions on the order of microns, however, these of the inductor structure. However, simulations also predict
dimensions are defined photolithographically to within one- that the variation in self-resonant frequency will be less than
tenth of a micron in a submicron IC process. The inductive 5% for a 1 m change in oxide thickness and a 50% change
reactance of a monolithic inductor is set by metal line width in substrate resistivity from the nominal BiCMOS process
and line spacing, and thus the inductance is insensitive to the parameters listed in Table I. These tolerances are far less

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 367

than those typically encountered for other passive monolithic 4) Magnetic flux must be allowed to pass through the
components, such as resistors and capacitors. center of the spiral. This ensures that negative mutual
Other sources of variation are the metallization and silicon coupling between opposite sides of the inductor does
substrate resistivities, both of which depend upon temperature. not significantly affect the inductance and the -factor.
The aluminum–copper alloy typically used in silicon VLSI Thus, the four groups of coupled lines which form the
technologies (98% aluminum) has a temperature coefficient sides of the inductor must be spaced sufficiently apart.
of 0.44%/ C [32], which can cause a large increase in the Following the previous guideline, a space of greater than
metal losses with increasing temperature. Other interconnect five line widths (i.e., 5 ) is recommended.
metals, such as gold, also exhibit a strong positive temperature 5) The oxide layer which isolates the metal conductors
coefficient (0.4%/ C). The shift in metal resistance with tem- from the silicon substrate should be kept as thick as
perature directly affects the component quality factor [as seen possible in order to minimize shunt parasitics and dis-
from (3)], and it must be carefully considered in the design sipation.
and optimization of an RF circuit. 6) The inductor is most sensitive to the thickness and re-
The substrate resistivity also has a positive temperature sistivity of the metal layer used in fabrication. Although
coefficient, which is approximately 0.7%/ C [33]. As seen the metal thickness is fixed in production technolo-
from (3), an increase in substrate resistivity with temperature gies, metal layers in a multilevel metal process can
can cause a degradation in the -factor at frequencies much be connected in parallel (metal stacking) to reduce
less than the substrate corner frequency ( ), Ohmic losses. This technique has demonstrated a 20%
and an improvement in -factor for frequencies higher than improvement in -factor when compared to inductors
. Choosing to operate in a frequency band close to the fabricated using only top metal [17] in some tech-
peak reduces the effect (over temperature) of the substrate nologies. However, there is a tradeoff between the
resistivity upon the inductor performance. improvement in metal thickness and the reduction in
oxide thickness as a result of metal stacking.
The results of this study have shown that a silicon tech-
VIII. INDUCTOR DESIGN AND OPTIMIZATION
nology with a substrate resistivity in the 10 -cm range and
The design of a spiral inductor in silicon VLSI technologies a 5- m thick oxide between metal and substrate can be used
involves a complex tradeoff between the various layout and to fabricate inductors with acceptable -factors in the 1–3
technological parameters, as demonstrated by the experimental GHz frequency range. The metallization thickness has a large
results presented in the previous section of this paper. The effect upon the inductor quality factor, and a -factor of five
following set of guidelines or “design rules” summarize the is achievable with 1- m thick aluminum top metal. However,
results of this study. a -factor of ten can be achieved if the metal thickness is
1) Maintain a space of at least five line widths (i.e., 5 , or increased to 3 m.
further if possible) between the outer turn of the spiral A substantial improvement in inductor performance can
and any surrounding metal features. Parasitic electric also be realized through careful optimization of other aspects
and magnetic coupling between conductors is inversely of the inductor layout using the lumped-element computer
proportional to the separation. Maintaining sufficient model. A plot of a -factor surface (at 1.9 GHz) that is
space between the inductor and its surroundings will defined by variations in the conductor width and the number
keep unwanted parasitic effects from disturbing the of turns of the spiral is shown in Fig. 11. The substrate
inductor’s electrical characteristics. parameters for the BiCMOS technology given in Table I
2) The magnetic coupling between adjacent metal lines is were used for the simulations, with a 1.5- m line spac-
maximized by using the closest spacing ( ) between ing. The points corresponding to an inductance of 5 nH
lines that is allowed by the technology. The additional are plotted onto the surface with an asterisk. These points
interwinding capacitance from tighter coupling of the indicate that an optimum geometry can be identified which
electric field between adjacent conductors has only a maximizes the inductor -factor for a given inductance.
slight impact on performance, given that metal thickness The spiral geometry which yields the highest -factor at
in most VLSI technologies is usually less than 3 m. 1.9 GHz is also easily identified from this figure. The 3-
Tight coupling of the magnetic field maximizes the - D plot is a powerful design aid which can be used to
factor and reduces the chip area for a given inductor visualize the effects of the many parameters which influence
layout. the inductor performance. A fast and efficient computer-based
3) A strip width of between 10–15 m is close to the model is required in order to generate these types of design
optimum for most inductor designs fabricated with the aids.
technological parameters listed in Table I. Increasing the
conductor width causes a downward shift in the peak
-factor and also makes the -factor more sensitive to IX. CONCLUSIONS
changes in operating frequency. This tradeoff requires A scalable lumped-element computer model has been de-
extensive computer simulation in order to establish the scribed which adequately models the performance of inductors
optimum strip width for a given technology and induc- fabricated in a silicon VLSI process for a wide range of
tance value. layout geometries. Both the measured and simulated results

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368 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 3, MARCH 1997

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LONG AND COPELAND: MONOLITHIC INDUCTORS FOR SILICON RF IC’S 369

John R. Long (M’96) received the Dipl. Tech. in Miles A. Copeland (M’65–SM’85–F’89) received
electronics engineering technology from the South- the B.Sc. degree in electrical engineering from the
ern Alberta Institute of Technology, Calgary, AB, University of Manitoba, Canada, in 1957, and the
Canada, in 1978, the B.Sc. in electrical engineering M.Sc. and Ph.D. degrees in electrical engineering
from the University of Calgary, AB, in 1984, and the from the University of Toronto, ON, Canada, in
M.Eng. and Ph.D. degrees in electronics engineering 1962 and 1965, respectively.
from Carleton University, Ottawa, ON, in 1992 and He has been a Professor in the Department
1996, respectively. of Electronics, Carleton University, Ottawa, ON,
He was employed for ten years by Bell-Northern Canada, for 31 years. He is now officially retired,
Research Ltd., Ottawa, ON, where he was involved but maintaining an office and the honorary title of
in the development of flat panel display and high- Distinguished Research Professor. He is active in
speed printing technologies for facsimile applications, as well as the design research and graduate student supervision and is presently a Consultant with
of GaAs ASIC’s for Gb/s fiber optic transmission systems. In January 1996 Nortel Technology Ltd. and co-investigator at Carleton University in the VLSI
he joined the faculty at the University of Toronto, ON. His current research for Communications Group. A large component of his research is supported
interests include low-power transceiver circuitry for highly integrated radio through cooperative graduate student thesis projects with industry.
applications and circuit design for high-speed data communications systems.

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