Design and Performance Analysis of Low Phase Noise LC-voltage Controlled Oscillator
Design and Performance Analysis of Low Phase Noise LC-voltage Controlled Oscillator
Design and Performance Analysis of Low Phase Noise LC-voltage Controlled Oscillator
Corresponding Author:
Ramchandra Gurjar
Department of Electronics and Instrumentation Engineering
Shri G S Institute of Technology and Science, Indore, India
Email: rcgurjar94@gmail.com
1. INTRODUCTION
The global voltage controlled oscillator (VCO) market is predicted to increase substantially due to
rapid technological advancements in the very large scale integration (VLSI) sector and the wide application
of voltage-controlled oscillation in numerous end-user industries. There is a need for wide tunable reference
frequency in almost all wireless or wireline tasks, which supports multi-standard applications. Despite a large
amount of research and development, radio frequency (RF) designers still find the VCO to be a difficult
component. As the need for wireless communications grows, and new applications enter the market at higher
frequencies, VCOs are subjected to more demanding standards. VCO may be realized with many
configurations according to the applications and performance requirements. The available fundamental
approaches are ring oscillator [1]-[3], inductance-capacitance (LC) oscillator [4], [5] tunable active inductor
(TAI) based oscillator [6], [7], and relaxation oscillator [8]. Apart from the phase noise (PN); tuning range,
power consumption, and output waveform are also necessary VCO specifications. Unfortunately, there are
direct tradeoffs between these specifications like ring oscillator, or TAI-based VCOs have larger tuning range
but lower phase noise while resonator-based oscillators have lower phase noise but suffer in terms of tuning
range. The performance of VCO has a very significant impact on the overall performance of RF front end they are
being used in [9]. In high-performance applications where low PN is required, VCO using LC tank is preferred.
The minimum phase noise requirement in the VCO is set by the specific communication standard. Various low PN
techniques like noise filtering [10]-[12], tail current shaping [13], [14], self-switched bias [15], [16] have been
reported in the literatures. In this paper, we present an inductive source degeneration (ISD) based low PN
technique to improve the PN performance of the LC-VCO. The organization of the paper is as: section 2
discuss the methodology for implementing LC-VCO. Circuit architecture and detailed analysis of the
proposed design are presented in section 3. Section 4 elaborate the layout, post layout simulation and
performance comparison followed by conclusion.
𝑑𝐼𝑑𝑠𝑎𝑡 𝑊
𝐺𝑚𝑛 = = µ𝑛 𝐶𝑂𝑋 (𝑉𝐺𝑆 − 𝑉𝑡ℎ ) (2)
𝑑𝑉𝐺𝑆 𝐿
The minimum length of 180 µm for the transistors has been used.
− Circular spiral inductor
Lesson’s phase noise model [25] suggests large Q of the tank to achieve the lower PN. The selection
of an inductor in the design of VCO is an important aspect. A three terminal circular spiral inductor model
L_SLCR20K_RF from UMC 0.18 µm RF compemetary metal oxide semiconductor (CMOS) process library
in spectre RF has been employed to design the proposed VCO. The various parameters of the spiral inductor
having 7.14 nH inductance is given in Table 1. The inductance value can be adjusted by the number of turns,
width and diameter. The inductance value affects the tank amplitude and start-up constraints.
− MOS varactors
The tuning of a spiral inductor is not possible by some control voltage, so we need some varactor to
implement the VCO. Because of its wider capacitance range compared to junction varactor, the inversion
metal oxide semiconductor (IMOS) varactor has been employed as a tuning element of LC VCO.
Design and performance analysis of low phase noise LC-voltage controlled oscillator (Ramchandra Gurjar)
874 ISSN: 1693-6930
1
𝑓0 ≅ (4)
2𝜋√𝐿(𝐶𝑣 +𝐶𝑎𝑣𝑔 +𝐶𝑝𝑎𝑟 )
Where 𝐶𝑎𝑣𝑔 is the instantaneous average capacitance due to sinusoidal voltage at the gate terminal of
varactor, 𝐶𝑣 is the varactor capacitance and 𝐶𝑝𝑎𝑟 is capacitance due to presence of parasitic. Other than these
capacitances, load capacitance (𝐶𝐿 ) or external capacitance, whose value depends upon the application (buffer),
is also added. These external capacitances also affect the power dissipation. Therefore the value of tuning
elements i.e., 𝐿 or 𝐶 has to be recalculated. This means the VCO requires redesign for different load [1]. This
makes the oscillator design a challenging task. So as this (4) suggests that only inductance or capacitance are
tuning elements. The large tuning indicates better design in terms of controllability.
The PMOS transistors instead of NMOS transistors have been used in the varactor design because of its
low flicker noise. To reduce the flicker (1/f) noise contributed by MOS switches, the device area can be increased
as shown in (5). A larger area means a lower tuning range, so we need to adjust the area properly. The value of
𝐾 for PMOS is 50 times lower than NMOS, so it gives less drain current thermal noise than NMOS.
̅̅̅̅̅
𝑖2 1 =
𝐾 1 2
. . 𝑔𝑚 (5)
𝑛, 𝑊𝐿𝐶𝑜𝑥 𝑓
𝑓
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Where 𝑅𝑛𝑒𝑔 is the equivalent negative resistance offered by double cross-coupled transistor, 𝑅𝑒𝑞 is the
parallel resistance provided by LC tank, 𝑔𝑚𝑛 and 𝑔𝑚𝑝 are the transconductance of NMOS and PMOS
transistor respectively.
In differential CC LC oscillator, tail current generator at source is considered the major source of
flicker noise. The close-in PN is dominated by the up-converted flicker noise of the tail current [30], [32], [33].
Most of the complementary structures either use NMOS or PMOS tail current sources. In any balanced
circuit, even harmonics flow in a common mode path; therefore, there is a need for high impedance to even
harmonics of the oscillation frequency. The high impedance offered by the tail current source also helps to
avoid the degradation of the resonator’s quality factor [12].
Source degeneration scheme is an excellent technique to suppress flicker noise up-conversion into
phase noise [34]. Several circuit structures using source degeneration techniques such as inductive degenerated,
resistive degenerated, capacitive degenerated, and LC filtering technique [12], [31] are presented in various
research papers. By removing the tail current generator in the proposed design, the close in phase noise could be
improved, but this will impair the quality factor of resonator and due to the absence of high impedance,
oscillator will be more sensitive to ground noise. So, instead of tail current generator, an inductor is inserted.
(a) (b)
Figure 2. VCO: (a) traditional implementation of double CC VCO and (b) topology with added ISD
Design and performance analysis of low phase noise LC-voltage controlled oscillator (Ramchandra Gurjar)
876 ISSN: 1693-6930
In perfectly balanced LC-VCO, odd and even harmonics are present. The odd harmonics exist in a
differential path with no current flowing through the tail transistor. Opposite to that, even harmonics flow
from supply to ground path, including the tail transistor. The nonlinearities in the oscillator are responsible
for converting low-frequency noise of the tail transistor into high-frequency noise around the even harmonics
and the down-converting to the PN around the carrier. The effect of higher-order harmonics on the phase
noise is neglected oweing to their low level.
The inductor provides a high impedance common node for differential pairs at the cost of the area.
A spiral inductor (𝐿𝑠 ) is used to resonate in parallel with parasitic capacitance 𝐶𝑝 at source node (𝑆). If the
value of inductor (𝐿𝑠 ) is chosen in such a way that 𝜔𝑠 (resonant frequency at source node) is equal to the
second harmonic frequency (2𝜔𝑜 ) of the oscillator, then impedance (𝑍𝑠 ) at source node seen from
differential transistor is approximately infinite [35]. The Resonant frequency at output node is depicted in
Figure 3(a). The Resonant frequency at source node (𝑆) as shown in Figure 3(b) and Figure 3(c) is:
1
𝜔𝑠 = = 2𝜔𝑜 (7)
√𝐶𝑝 𝐿𝑠
Where 𝜔𝑠 is the resonant frequency at source node, 𝐿𝑠 is the series inductor and 𝐶𝑝 is the total capacitance at
the source terminal (𝑆) of the oscillator including parasitic capacitance and source capacitance of NMOS
transistors. This can be shown:
𝑗2𝜔𝑜 𝐿𝑠 𝑗2𝜔𝑜 𝐿𝑠
𝑍𝑠 = = (2𝜔𝑜 )2
(8)
1−(2𝜔𝑜 )2 𝐿𝑠 𝐶𝑝 1−
(𝜔𝑠 )2
It can been seen from (8), as 𝜔𝑠 (Figure 3(b)) is approximately equal to second harmonic of
oscillator frequency (𝜔𝑜 ) (Figure 3(a)), the impedance 𝑍𝑠 at source node approaches infinity, and the 𝑄 of the
inductance-capacitance tank is maintained. A symmetrical waveform is also helpful to get the lower PN [36].
So in the proposed design, 𝑊/𝐿 ratio of tramsostors of CC is chosen to have equal rise and fall time in the
waveform. To obtain symmetrical waveform, the transconductance of PMOS and NMOS transistors should
be equal. This leads to (9):
𝑊𝑛 𝑊𝑝
√2𝜇𝑛 𝐼𝑑𝑠 𝐿𝑛
𝐶𝑜𝑥 = √2𝜇𝑝 𝐼𝑑𝑠
𝐿𝑝
𝐶𝑜𝑥 (9)
Where 𝜇𝑛 and 𝜇𝑝 are the surface mobilities of NMOS and PMOS channel respectively, 𝐶𝑜𝑥 is the capacitance
𝑊𝑝 𝑊𝑛
per unit area of the gate oxide, and are the effective channel width-length ratio of PMOS and NMOS
𝐿𝑝 𝐿𝑛
device respectively.
Figure 3. Simulated waveform: (a) single-ended output signal (𝜔𝑜 ), (b) second harmonic of oscillating
frequency (2𝜔𝑜 ) at source node (𝑆), and (c) at the source and output node
The higher sensitivity of the oscillating frequency to voltage supply (frequency pushing) can be lowered
by inserting an inductor (𝐿2 ) having 3.5 nH inductance between a supply voltage and resonator. In addition to that,
it also provides a high impedance path between resonant tank and power supply (𝑉𝐷𝐷 ). Variation in the oscillation
frequency has been obtained by varying the control voltage of IMOS varactor consisting of 5 parallel units of two
series connected back to back PMOS transistor.
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Figure 4. Layout of the proposed Figure 5. Tuning range of the Figure 6. PN performance with and
ISD based LC-VCO proposed VCO without ISD technique
At offset frequency of 1 MHz, the PN achieved for this technique is -124.3 dBc/Hz, which can meet
the specification of ISM band applications. Using the proposed technique, PN improvement of -11.7 dBc/Hz
at a frequency offset of 1 MHz is achieved compared to the conventional design. A buffer amplifier is not
considered in the design but output power must have a reasonable value. The output spectrum is shown in
Figure 7. The VCO gain (𝐾𝑉𝐶𝑂 ) with respected to tuning voltage is ploted in Figure 8. The Monte Carlo
(MC) simulation for 1000 sample has been performed to examine the effect of process variation on the phase
noise. The MC simulation based histogram is ploted in Figure 9. The VCO draws a current of 1.166 mA from
the supply voltage of 1.8 V. The performance of VCO may be evaluated in terms of various specifications like
PN, power dissipation, output amplitude, and tuning range. There are several figure of merits (FOMs) to
evaluate the performance metrics of a VCO. The following equation is widely used to evaluate the performance
of VCO [37].
𝑓𝑜 𝑃𝐷𝐶
𝐹𝑂𝑀 = 𝐿(𝑓𝑜𝑓𝑓 ) − 20 𝑙𝑜𝑔 ( ) + 10 𝑙𝑜𝑔 ( ) (10)
𝑓𝑜𝑓𝑓 1𝑚𝑤
Where 𝐿(𝑓𝑜𝑓𝑓 ) represents the PN at offset frequency and 𝑃𝐷𝐶 is the power consumption in mW.
The comparison performance of the proposed works with other state of work is given in Table 3.
Design and performance analysis of low phase noise LC-voltage controlled oscillator (Ramchandra Gurjar)
878 ISSN: 1693-6930
Figure 7. Output power spectrum Figure 8. VCO gain with respect to tuning voltage
5. CONCLUSION
In this paper, the proposed design of LC-VCO was discussed with a focus on phase noise
performance. The basic step in the design of VCO is the selection of a suitable topology. The design
methodology for VCO was presented. The design, implementation, and layout of CMOS LC-VCOs were
accomplished using Virtuoso analog design environment with UMC process parameter, and post layout
simulations were performed using spectre. The low phase noise technique, namely inductive source
degeneration were investigated. With low phase noise ISD, satisfactory performance of the VCO with phase
noise of -124.3 dBc/Hz at 1 MHz offset frequency was obtained. The post layout simulation results confirm
that these VCOs can meet the specification for applications in the 2.2 GHz to 2.7 GHz unlicensed ISM bands.
The performance outcomes validate the effectiveness of the topologies and methodologies used in the design.
ACKNOWLEDGEMENTS
Authors extend thanks to SMDP-C2SD (A Project of Ministry of Electronics and Information
Technology, Govtorment of India) for providing VLSI-Electronic Design Automation tools in the laborotary.
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Design and performance analysis of low phase noise LC-voltage controlled oscillator (Ramchandra Gurjar)
880 ISSN: 1693-6930
BIOGRAPHIES OF AUTHORS
Deepak Kumar Mishra received the B.E. degree in Electronics and M.E. in
Applied Electronics and Servomechanism from the DAVV (Formerly- University of Indore)
Indore in 1979 and 1984 respectively. He obtained his Ph.D. from DAVV, Indore (India). He
is currently professor in SGSITS Indore. His research area includes the design, development
and testing of microprocessor and microcomputer based electronic instrumentation, RF IC
design, analog and mixed signal VLSI circuit design, dynamic testing of high speed A/D
converters, low power VLSI design, and system on chip design for biomedical signal
processing. He can be contacted at email: mishradrc@gmail.com, dmishra@sgsits.ac.in.
TELKOMNIKA Telecommun Comput El Control, Vol. 21, No. 4, August 2023: 872-880