Experiences using PrimeTime

Physically-Aware ECO Technology

Khaled Heloue, Rajit Seahra

Advanced Micro Devices, Inc.

Oct 1st, 2015

SNUG Canada

SNUG 2015 1
 Agenda

Motivation: Speeding up ECO stage

Background: PrimeTime Physically-aware ECO
Evaluation Flow & Experiments
Results
Final Words

SNUG 2015 2
 Motivation
Speeding up design closure!

SNUG 2015 3
 AMD Design Challenges
Obstacles to Closure
• AMD is a developer of CPU, GPU and APU designs with interesting
challenges
– Performance, with CPUs over 3GHz GPUs over 1GHz
– Design size, with the largest designs in production having over 250 million
standard cells and larger designs in flight
– Power, with an increasing focus on ultra low power designs
– Time to market, with hard deadlines for tapeout and production
• We are constantly looking for improved methodologies to make our
design flow more efficient
• PrimeTime Physically-Aware ECO is an interesting technology that
help us improve our schedules by making the ECO stage more
efficient and predictable
– Will share data from our evaluation of this feature for timing, transition, and
noise fixing on a large set of design blocks on a leading FinFet technology
node
SNUG 2015 4
 Background
Physically-Aware PrimeTime ECO

SNUG 2015 5
 PrimeTime ECO
Automated ECO Guidance
• PrimeTime can provide automated guidance to fix timing,
DRC, and noise violations
– Writes ECO change list file to address violations
• ECO guidance can be logical-only (i.e. netlist based) or
physically-aware
• Obvious benefits of physically-aware ECO:
– Considers physical placement and routing
– Improves ECO predictability and fix rate
– Adds placement locations to changed cells
– Avoids large displacements when resizing cells
– Considers available space, placement density, placement
blockages, and wire delay when inserting buffers
– Results in faster ECO convergence
SNUG 2015 6
 Physically-Aware ECO
Inputs
• Requires the following
inputs:
1. Verilog netlist and physical
design information (DEF)
2. Library timing data and
physical cell information
(LEF)
3. Parasitics (SPEF or SBPF)
generated with location
information

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 Physically-aware ECO (1/2)
Mechanics
• Process is relatively straightforward
– Enable parasitics with location data
set_app_var read_parasitics_load_locations true
– Treat filler cells as open sites
set_app_var eco_allow_filler_cells_as_open_sites true
– Specify physical library/design info, filler cells names, output log
set_eco_options \
-physical_lib_path lef_files \
-physical_design_path def_files \
-filler_cell_names cell_names \
-log_file my_log \
– Use fix_eco_drc with –type max_transition or noise or
max_fanout or max_capacitance, and fix_eco_timing with
–type setup or hold, and specify physical mode as either
open_site or occupied_site
SNUG 2015 8
 Physically-aware ECO (2/2)
Mechanics
– Setup fixing supports either size_cell or insert_buffer
– Hold fixing supports any (and all) of size_cell or
insert_buffer or insert_buffer_at_load_pins
– Max transition and noise fixing support both size_cell and
insert_buffer
– After issuing the fixing commands, generate ECO change list by
using write_changes
size_cell U1 AND2X
insert_buffer U2/Z BUF1X -location {212.3 753.2}
add_buffer_on_route net1 BUF2X -location {215.0 853.2} -
no_legalize

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 Evaluation Flow & Experiments

SNUG 2015 10
 Evaluation Flow
Apply ECO, Route/Extract, Generate ECO, repeat…

Baseline
Routed Design
Empty ECO

ICC Apply ICC Apply ICC Apply

ECO ECO ECO
ICC Inc ICC Inc ICC Inc
Route Route Route
Star/ Star/ Star/
PrimeTime PrimeTime PrimeTime

PT ECO PT ECO PT ECO

Baseline Eco1 Eco2

[Generate Eco1] [Generate Eco2] [Generate Eco3]

SNUG 2015 11
 PT ECO Job Features

• Built around PrimeTime distributed multi-scenario analysis

(DMSA)
– Creates a set of distributed PT jobs for different timing scenarios
and uses a master PT run to control the slave jobs
• Essential to enable multi-mode multi-corner fixing across
signoff modes/corners, ensure fixes don’t degrade metrics
in other scenarios, and speed up ECO convergence!

SNUG 2015 12
 Experiments
Scenarios and Design Blocks
• 8 different PT scenarios (4 • 16 design blocks on a
setup, 4 hold) leading FinFet tech node
– Typical, slow, fast process ranging from 250K-1.5M
– Low, mid, high voltage instances
– Low, High temperature Block Number
block_01
Instance Count
1051375
– Typical, worst, best RC block_02
block_03
1360179
834841

• Setup/Hold: 7 scenarios block_04

block_05
1484493
550766
block_06 1204859
• Transition: 7 scenarios block_07 739474
block_08 571305
• Noise: all 8 scenarios block_09
block_10
254776
309161

• PT versions: block_11
block_12
340999
799888
block_13 687778
– 2014.12-SP3 block_14 631185
block_15 824368
– 2015.06 BETA (noise fixing) block_16 565659

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 Results
Physically-Aware PrimeTime ECO

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 Setup Timing Results

• Evaluated insert_buffer and size_cell methods

• Used open_site physical mode to minimize impact from
cell displacement (based on past experience on 28nm)
• Summary:
– insert_buffer:
• TNS reduction of 20% on average, max 96%
• 13 blocks improve, 2 degrade
• Improved over earlier evaluation
– Size_cell:
• TNS reduction of 56% on average, max 99%
• 15 blocks improve, 1 degrade slightly
• Decent results
• Minimal to no-impact of Setup fixing on Hold qor
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 Setup TNS Reduction

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 Hold Timing Results

• Used default fixing method which allows both size_cell

and insert_buffer
• Selected occupied_site physical mode
• Summary:
– Consistent improvement in all 16 design blocks
– Fix rate (by violations count) of 73% on average, max 83%
– Setup TNS is minimally impacted by hold fixing (~1% improvement
on average, with most blocks unchanged)
• Overall, hold fixing rate is very good, and continues to
improve in subsequent ECOs

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 Hold Violations Count Reduction

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 Max Transition Fixing

• Used default fixing method which allows both size_cell

and insert_buffer
• Selected occupied_site physical mode
• Summary:
– Dramatic improvement in all 16 design blocks
– Fix rate (by violations count) of 95% on average, max 100%
– Setup/Hold qor minimally impacted by transition fixing for most
blocks (within ±1% on average)
• Overall, transition fixing is excellent, with majority of the
violations fixed in just one round of ECOs!

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 Transition Violations Reduction

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 Noise Fixing

• Used default fixing method which allows both size_cell

and insert_buffer
• Selected occupied_site physical mode
• Noise analysis mode used report_at_source
• Summary:
– New feature, so pushed two rounds of ECOs
– Dramatic improvement in all 16 design blocks during ECO1
– Fix rate at ECO1 of 95% on average, max 99%
– Cumulative Fix rate at ECO2 at 98%-100% for 15 out of 16 blocks,
and 1 block showing degradation (more on this later)
• Overall, noise fixing is excellent, with majority of the
violations fixed in the first round!
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 Noise Fixing (occupied_site)

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 Noise Fixing (open_site)

• Degradation may be attributed

to aggressive cell sizing
and/or cell displacement,
producing more violations

• ECO2 repeated for block_01

using open_site mode

• As expected, ECO2 results Baseline

lead to more improvement, ECO1

with aggregate fix rate of 97%! ECO2

SNUG 2015 23
 Runtime and Memory

Memory Runtime
Block Number Memory (in MB)
block_01 7271
block_02 9695
block_03 6804
block_04 9715
block_05 4927
block_06 8676
block_07 5556
block_08 5181
block_09 3490
block_10 3728
block_11 4168
block_12 5630
block_13 5885
block_14
block_15
5182
6735
• On average:
block_16 6056
– Setup: ~ 2 hrs
– Hold: ~1 hr
– Typically correlated with – Transition: ~1 hr
block sizes
– Noise: ~1.5 hrs
SNUG 2015 24
 Final Words

SNUG 2015 25
 Conclusions
And Future Work
• Covered PrimeTime physically-aware ECO results on
AMD designs in FinFet tech node
• Overall, very satisfied with the technology and achieved fix
rates
– Improved setup fixing, very good hold fixing, and excellent
transition and noise fixing
• Recommending physically-aware ECO internally for
current and upcoming products
• Working with Synopsys on improved buffering for setup
fixing
– Already showing promising results (doubling insert_buffer fix rate)
• Would like to see ECO capabilities expanded to SI double
switching, and standalone delta delay reduction
SNUG 2015 26
 Thank You

SNUG 2015 27