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    Publish Only 02 Manchuri

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    Publish Only 02 Manchuri

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    Publish Only 02 Manchuri

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    banesh
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    You are on page 1of 7

    Complex SOC design timing closure using ECO Clock optimization

    techniques

    Silpa Manchuri
    Intel Technologies, India

    Page | 1
    Abstract:
    We are working on complex low power SOCs with very tight schedule. As
    designs are highly congested, timing convergence becomes big challenge and we
    cannot completely depend on data ECO flow. In such cases, looking at clock
    optimization techniques becomes imperative for both timing and DRC closure
    with the given power targets.
    In this paper we would like to present the usage of various clock
    optimization techniques. It describes the methods to fix DRC (max_transition and
    max_capacitance) violations and timing violations in clock network using ECO
    features. In addition, we came up with a technique to fix max_capacitance
    violations over sequential cells. And also, we came up with an in-house dynamic
    clock power optimization flow, which performs DRC and timing aware based
    power recovery in the clock network.

    Page | 2
    Table of contents
    1. Introduction ……………………………………………………………………………………………….4
    2. Clock Optimization Methods ………………………………………………………………………5
    2.1.DRC ……………………………………………………………………………………………………..5
    2.2.Timing ………………………………………………………………………………………………….6
    2.3.Power …………………………………………………………………………………………………..7
    3. Summary ……………………………………………………………………………………………………7

    Table of Figures
    1. The flow order to fix all violations for better fixing rate ……………………………..4
    2. DRC fixing flow ……………………………………………………………………………………………5
    3. Timing fixing flow ……………………………………………………………………………………….6

    Table of Tables
    1. DRC data/clock fixing results ……………………………………………………………………..6
    2. Timing fixing results ……………………………………………………………………………………7
    3. Power optimization results ………………………………………………………………………..7

    Page | 3
    1. Introduction
    By default, the ECO fixing makes changes to the design only in data paths through which
    it can optimize timing (Setup and Hold), DRC (max_capacitance, max_transition, max_fanout
    and noise), and Power (leakage). But there are cases in which data path optimization alone
    could not fix all violations in the design. So, the flow came up with an option to fix and make
    changes in clock network. It can fix DRC (max_transition, max_capacitance, and max_fanout)
    violations and timing in clock network.
    The below figure shows the complete flow used to fix all violations in the order. We
    started the flow with buffer removal for area recovery, which allows better optimization for
    DRC and timing violations. And then we followed the order DRC, Setup, Power and Hold fixing.
    For better leakage recovery, we first used swap methodology and followed by downsizing of
    the cells. And it also helped to fix significant amount hold violations without additional buffer
    insertion.

    Fig 1: The flow order to fix all violations for better fixing rate

    Page | 4
    2. Clock Optimization Methods
    The clock optimization feature allows us to fix DRC violations in clock network and
    Timing by changing clock arrival delays. It is supported only in physical aware mode ECO flow.
    In this paper, we will mainly focus on fixing DRC violations (max_capacitance and
    max_transition) and Timing (Setup and Hold) through clock optimization feature.

    2.1. DRC fixing


    In our complex SOC designs, we can observe DRC violations in both data paths and clock
    paths. The default method of ECO flow can fix violations only in data paths and leaves the clock
    paths pin violations as unfixed (reason C). However, we can fix clock DRC violations by enabling
    the physical aware mode and clock network optimization.
    The flow supports sizing, insert_buffer and insert_inverter_pair methods to fix DRC
    violations in clock network. Here, we first fixed the DRC violations in data path and then in clock
    network. The below diagram shows the order of fixing DRC violations for better fixing rate. We
    also came up with a solution to size sequential cells to fix max_cap in clock path, which resulted
    additional max_cap violation fixing.

    Fig 2: DRC fixing flow

    Page | 5
    Results:
    Sized Buffers Max_cap_ Max_trans_ Max_cap_ Max_trans_
    data data clock clock
    Init 18650 1459 1650 20
    DRC_DATA_fix 20865 805 513 433 1650 20
    DRC_CLOCK_fix 1288 42 514 433 582 18
    DRC_CLOCK_sol 451 - 514 433 174 18

    Table 1.1: block-1 DRC data/clock fixing results

    2.2. Timing
    The flow can fix timing (setup and hold) violations by changing clock arrival delays. It
    supports both sizing and buffer insertion. To get better results, we have done clock
    optimization before and after data path fixing. And we restricted clock eco changes by setting
    clock_fixes_per_change.

    Fig3: Timing fixing flow

    Results:
    MaxTNS MaxWNS MaxPaths MinTNS MinWNS MinPaths
    Init -823 -81 20 -62458185 -530 253684
    Eco_fix -36 -36 1 -12043640 -522 93328

    Table 2.1: Timing fixing with useful skew. Clock changes for Setup – 0, Clock changes for Hold –
    77 new buffers

    Page | 6
    MaxTNS MaxWNS MaxPaths MinTNS MinWNS MinPaths
    Init -2123 -140 73 -72621 -301 1009
    Eco_fix -1777 -111 48 -211 -71 4

    Table 2.2: Timing fixing with useful skew. Clock changes for Setup – 0, Clock changes for Hold-1.
    All REG2REG paths for both setup and Hold are fixed.

    2.3. Power
    In addition to DRC and Timing fixing through clock cell changes, our team came up with
    a solution to identify cells in clock network and downsizing them for dynamic power reduction.
    The given solution is Timing (setup) and DRC aware. We have used power fixing methods in the
    order of clock_fix, swap (combinational, and sequential) and size (combinational only) for
    better fixing.

    Results:
    MaxPaths MinPaths Max_cap Max_trans Leakage
    Init 2084 3205 18650 1459 0.2094
    Power(clock) 2026 6424 18658 1459 0.2074
    Power(swap/size) 2001 3361 8422 1216 0.1324

    Table 3.1: Power optimization results

    3. Summary
    The usage of clock ECO optimization methods gave us better fixing with less number of
    changes. It allowed us to fix DRC violations in clock network also with minimal degradation in
    timing. The timing violations, which could not get fixed in data path got fixed by making
    changes in clock arrivals.

    Page | 7

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