19-1105; Rev 0; 8/96

+5V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers
_______________General Description ____________________________Features

MAX534
The MAX534 serial-input, voltage-output, 8-bit quad dig- ♦ +4.5V to +5.5V Single-Supply Operation
ital-to-analog converter (DAC) operates from a single
+4.5V to +5.5V supply. Internal precision buffers swing ♦ Ultra-Low Supply Current:
rail to rail, and the reference input range includes both 0.8mA while Operating
ground and the positive rail. The MAX534 features a 2.5µA in Shutdown Mode
2.5µA shutdown mode. ♦ Ultra-Small 16-Pin QSOP Package
The serial interface is double buffered: a 12-bit input
shift register is followed by four 8-bit buffer registers and ♦ Ground to VDD Reference Input Range
four 8-bit DAC registers. The 12-bit serial word consists ♦ Output Buffer Amplifiers Swing Rail to Rail
of eight data bits and four control bits (for DAC selection
and special programming commands). Both the input ♦ 10MHz Serial Interface Compatible with SPI, QSPI
and DAC registers can be updated independently or (CPOL = CPHA = 0 or CPOL = CPHA = 1), and
simultaneously with a single software command. Two Microwire
additional asynchronous control pins, LDAC and CLR, ♦ Double-Buffered Registers for Synchronous
provide simultaneous updating or clearing of the input
Updating
and DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL = ♦ Serial Data Output for Daisy Chaining
CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A ♦ Power-On Reset Clears Serial Interface and Sets
buffered data output allows daisy chaining of serial All Registers to Zero
devices.
♦ Software Shutdown
In addition to 16-pin DIP and CERDIP packages, the
MAX534 is available in a 16-pin QSOP that occupies the ♦ Software-Programmable Logic Output (µC I/O
same area as an 8-pin SO. Extender)
For operation guaranteed to 2.7V, see the MAX533 ♦ Asynchronous Hardware Clear Resets All Internal
data sheet. Registers to Zero
________________________Applications ______________Ordering Information
Digital Gain and Offset Adjustments
Programmable Attenuators INL
PART TEMP. RANGE PIN-PACKAGE
(LSB)
Programmable Current Sources
MAX534ACPE 0°C to +70°C 16 Plastic DIP ±1
Portable Instruments MAX534BCPE 0°C to +70°C 16 Plastic DIP ±2
__________________Pin Configuration MAX534ACEE 0°C to +70°C 16 QSOP ±1
MAX534BCEE 0°C to +70°C 16 QSOP ±2
TOP VIEW MAX534BC/D 0°C to +70°C Dice* ±2
OUTB 1 16 OUTC MAX534AEPE -40°C to +85°C 16 Plastic DIP ±1
MAX534BEPE -40°C to +85°C 16 Plastic DIP ±2
OUTA 2 15 OUTD
MAX534AEEE -40°C to +85°C 16 QSOP ±1
REF 3 14 AGND
MAX534BEEE -40°C to +85°C 16 QSOP ±2
UPO 4 MAX534 13 VDD MAX534AMJE -55°C to +125°C 16 CERDIP** ±1
PDE 5 12 DGND MAX534BMJE -55°C to +125°C 16 CERDIP** ±2
LDAC 6 11 DIN *Dice are tested at TA = +25°C.
**Contact factory for availability and processing to MIL-STD-883.
CLR 7 10 SCLK
DOUT 8 9 CS
Functional Diagram appears at end of data sheet.

DIP/QSOP

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
ABSOLUTE MAXIMUM RATINGS
MAX534

VDD to DGND ..............................................................-0.3V, +6V Continuous Power Dissipation (TA = +70°C)

VDD to AGND...............................................................-0.3V, +6V Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW
Digital Input Voltage to DGND ....................................-0.3V, +6V QSOP (derate 8.3mW/°C above +70°C) .....................667mW
Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V) CERDIP (derate 10.00mW/°C above +70°C) ..............800mW
AGND to DGND ..................................................................±0.3V Operating Temperature Ranges
REF ................................................................-0.3V, (VDD + 0.3V) MAX534 _ C_ E ..................................................0°C to +70°C
OUT_ ...........................................................................-0.3V, VDD MAX534 _ E_ E ...............................................-40°C to +85°C
Maximum Current into Any Pin............................................50mA MAX534 _ MJE .............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = +5V and TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
Resolution 8 Bits
Integral Nonlinearity MAX534A ±1
INL LSB
(Note 1) MAX534B ±2
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic (all codes) ±1.0 LSB
Zero-Code Error ZCE Code = 00 hex ±20 mV
Zero-Code-Error Supply
Code = 00 hex, VDD = 4.5V to 5.5V 1 LSB
Rejection
Zero-Code Temperature
Code = 00 hex ±10 µV/°C
Coefficient
Full-Scale Error Code = FF hex ±30 mV
Full-Scale Error Supply
Code = FF hex, VDD = 4.5V to 5.5V 1 LSB
Rejection
Full-Scale Temperature
Code = FF hex ±10 µV/°C
Coefficient
REFERENCE INPUTS
Input Voltage Range 0 VDD V
Input Resistance 322 460 598 kΩ
Input Capacitance 10 pF
Channel-to-Channel Isolation (Note 2) -60 dB
AC Feedthrough (Note 3) -60 dB
DAC OUTPUTS
Output Voltage Range RL = open 0 VREF V
Code = FF hex, measured with IL = 0mA to
Load Regulation 0.156 LSB/mA
1.6mA

2 _______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (continued)

MAX534
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = +5V and TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS
Input High Voltage VIH 0.7VDD V
Input Low Voltage VIL 0.3VDD V
Input Current IIN VIN = 0V or VDD ±1.0 µA
Input Capacitance CIN (Note 4) 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 0.2mA VDD - 0.5 V
Output Low Voltage VOL ISINK = 1.6mA 0.4 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate CODE = FF hex 0.6 V/µs
To 1/2LSB, from code 00 to code FF hex
Output Settling Time 8 µs
(Note 5)
Digital Feedthrough and
VREF = 0V, code 00 to code FF hex (Note 6) 5 nV-s
Crosstalk
Digital-to-Analog Glitch Impulse Code 80 hex to code 7F hex 50 nV-s
Signal-to-Noise Plus VREF = 4Vp-p at 1kHz, code = FF hex 80
SINAD dB
Distortion Ratio VREF = 4Vp-p at 10kHz 70
Multiplying Bandwidth VREF = 0.5Vp-p, 3dB bandwidth 380 kHz
Wideband Amplifier Noise 60 µVRMS
POWER SUPPLIES
Power-Supply Voltage VDD 4.5 5.5 V
MAX534C/E 0.8 1.3
Supply Current IDD mA
MAX534M 0.8 1.5
Shutdown Current 2.5 10 µA

TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = +5V and TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Rise to CS Fall Setup Time MAX534C/E 50
tVDCS µs
(Note 4) MAX534M 60
MAX534C/E 40 20
LDAC Pulse Width Low tLDAC ns
MAX534M 50 25
CS Rise to LDAC Fall Setup MAX534C/E 40
tCLL ns
Time (Note 7) MAX534M 50
MAX534C/E 40 20
CLR Pulse Width Low tCLW ns
MAX534M 50 25
MAX534C/E 90
CS Pulse Width High tCSW ns
MAX534M 100

_______________________________________________________________________________________ 3
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
TIMING CHARACTERISTICS (continued)
MAX534

(VDD = +4.5V to +5.5V, VREF = 4.096V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = +5V and TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SERIAL-INTERFACE TIMING
MAX534C/E 10
SCLK Clock Frequency (Note 8) fCLK MHz
MAX534M 8.3
MAX534C/E 40
SCLK Pulse Width High tCH ns
MAX534M 50
MAX534C/E 40
SCLK Pulse Width Low tCL ns
MAX534M 50
CS Fall to SCLK Rise Setup MAX534C/E 40
tCSS ns
Time MAX534M 50

SCLK Rise to CS Rise Hold Time tCSH 0 ns

MAX534C/E 40
DIN to SCLK Rise to Setup Time tDS ns
MAX534M 50
DIN to SCLK Rise to Hold Time tDH 0 ns
SCLK Rise to DOUT Valid MAX534C/E 200
tDO1 ns
Propagation Delay (Note 9) MAX534M 230
SCLK Fall to DOUT Valid MAX534C/E 210
tDO2 ns
Propagation Delay (Note 10) MAX534M 250
MAX534C/E 40
SCLK Rise to CS Fall Delay tCS0 ns
MAX534M 50
CS Rise to SCLK Rise Setup MAX534C/E 40
tCS1 ns
Time MAX534M 50

Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than
or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section.
Note 2: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all other
DAC’s codes to 00 hex.
Note 3: VREF = 4Vp-p, 10kHz. DAC code = 00 hex.
Note 4: Guaranteed by design, not production tested.
Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of VOUT’s final value.
Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other
DAC.
Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for tLDAC or longer after CS goes high.
Note 8: When DOUT is not used. If DOUT is used, fCLK max is 4MHz, due to the SCLK to DOUT propagation delay.
Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).
Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).

4 _______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
__________________________________________Typical Operating Characteristics

MAX534
(VDD = +5V, TA = +25°C, unless otherwise noted.)

DAC ZERO-CODE OUTPUT VOLTAGE vs. DAC FULL-SCALE OUTPUT VOLTAGE vs. SUPPLY CURRENT vs.
OUTPUT SINK CURRENT OUTPUT SOURCE CURRENT TEMPERATURE
1.50 5.0 1000

MAX534-TOC3
MAX534-TOC1

MAX534-TOC2
DAC FULL-SCALE OUTPUT VOLTAGE (V)
DAC ZERO-CODE OUTPUT VOLTAGE (V)

VREF = 5V
DAC CODE = FF HEX
1.25 DAC CODE = 00 HEX 4.5
800
LOAD TO VDD

SUPPLY CURRENT (µA)

1.00 4.0
600
0.75 3.5
DAC CODE = 00 HEX
400
0.50 3.0
VREF = 5V
0.25 DAC CODE = FF HEX 200
2.5
LOAD TO GND
VREF = 4.5V
0 2.0 0
0 1 2 3 4 5 6 7 8 0 2 4 6 8 10 12 -55 -35 -15 5 25 45 65 85 105 125
DAC OUTPUT SINK CURRENT (mA) DAC OUTPUT SOURCE CODE (mA) TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT vs. SUPPLY CURRENT vs.

TEMPERATURE REFERENCE VOLTAGE
5 1000
MAX534-TOC4

MAX534-TOC6
SHUTDOWN SUPPLY CURRENT (µA)

ALL DAC CODES = FF HEX

3 800
SUPPLY CURRENT (µA)

3 600

ALL DAC CODES = 00 HEX

2 400

1 200

0 0
-55 -35 -15 5 25 45 65 85 105 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C) REFERENCE VOLTAGE (V)

_______________________________________________________________________________________ 5
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
MAX534

______________________________________________________________Pin Description

PIN NAME FUNCTION

1 OUTB DAC B Voltage Output
2 OUTA DAC A Voltage Output
3 REF Reference-Voltage Input
4 UPO Software-Programmable Logic Output
5 PDE Power-Down Enable. Must be high to allow software shutdown mode.
Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents
6 LDAC
of each input latch to its respective DAC latch.
Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and
7 CLR
sets all DAC outputs to zero.
Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling
8 DOUT
edge of SCLK (Table 1).
Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are
9 CS
executed when CS returns high.
Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising
10 SCLK
edge (A0 = A1 = 1, see Table 1).
11 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK.
12 DGND Digital Ground
13 VDD Power Supply, +4.5V to +5.5V
14 AGND Analog Ground
15 OUTD DAC D Voltage Output
16 OUTC DAC C Voltage Output

6 _______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

MAX534
INSTRUCTION
EXECUTED

CS

•••

•••
SCLK

DIN •••
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB

DACA DACD

DOUT
MODE 1
•••
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1

DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT

DOUT
MODE 0 •••
(DEFAULT)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1

Figure 1. 3-Wire Interface Timing

CS
tCSW
tCSH
tCS0 tCSS tCH tCP
tCL tCS1

SCLK
tDS
tDH

DIN

tD02
tD01

DOUT

tCLL
tLDAC

LDAC

Figure 2. Detailed Serial-Interface Timing Diagram

_______________________________________________________________________________________ 7
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
_______________Detailed Description Serial Input Data Format and Control Codes
MAX534

The 12-bit serial input format shown in Figure 3 com-

Serial Interface prises two DAC address bits (A1, A0), two control bits
At power-on, the serial interface and all digital-to- (C1, C0), and eight bits of data (D7...D0).
analog converters (DACs) are cleared and set to code The 4-bit address/control code configures the DAC as
zero. The serial data output (DOUT) is set to transition shown in Table 1.
on SCLK’s falling edge.
The MAX534 communicates with microprocessors Load Input Register, DAC Registers Unchanged
through a synchronous, full-duplex, 3-wire interface (Single Update Operation)
(Figure 1). Data is sent MSB first and can be transmit- A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
ted in one 4-bit and one 8-bit (byte) packet or in one
Address 0 1 8-Bit Data
12-bit word. If a 16-bit word is used, the first four bits
are ignored. A 4-wire interface adds a line for LDAC (LDAC = H)
and allows asynchronous updating. The serial clock
(SCLK) synchronizes the data transfer. Data is transmit- When performing a single update operation, A1 and A0
ted and received simultaneously. select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
Figure 2 shows the detailed serial-interface timing.
rent shift-register data. All DAC outputs remain
Please note that the clock should be low if it is stopped
unchanged. This preloads individual data in the input
between updates. DOUT does not go into a high-
register without changing the DAC outputs.
impedance state if the clock idles or CS is high.
Serial data is clocked into the data registers in MSB-first Load Input and DAC Registers
format, with the address and configuration information A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
preceding the actual DAC data. Data is clocked in on
Address 1 1 8-Bit Data
SCLK’s rising edge while CS is low. Data at DOUT is
clocked out 12 clock cycles later, either at SCLK’s falling (LDAC = H)
edge (default or mode 0) or rising edge (mode 1).
Chip select (CS) must be low to enable the DAC. If CS This command directly loads the selected DAC register
is high, the interface is disabled and DOUT remains at CS’s rising edge. A1 and A0 set the DAC address.
unchanged. CS must go low at least 40ns before the Current shift-register data is placed in the selected
first rising edge of the clock pulse to properly clock in input and DAC registers.
the first bit. With CS low, data is clocked into the For example, to load all four DAC registers simultaneously
MAX534’s internal shift register on the rising edge of with individual settings (DAC A = 1V, DAC B = 2V,
the external serial clock. Always clock in the full 12 bits DAC C = 3V, and DAC D = 4V), four commands are
because each time CS goes high the bits currently in required. First, perform three single input register
the input shift register are interpreted as a command. update operations for DACs A, B, and C (C1 = 0). The
SCLK can be driven at rates up to 10MHz. final command loads input register D and updates all
four DAC registers from their respective input registers.

Software “LDAC ” Command

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
THIS IS THE FIRST BIT SHIFTED IN
MSB LSB 0 1 0 0 x x x x x x x x

DOUT A1 A0 C1 C0 D7 D6 ... D1 D0 DIN (LDAC = 1)

When this command is initiated, all DAC registers are
CONTROL AND 8-BIT DAC DATA updated with the contents of their respective input reg-
ADDRESS BITS isters at CS’s rising edge. With the exception of using
CS to execute, this performs the same function as the
asynchronous LDAC.

Figure 3. Serial Input Format

8 _______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

MAX534
Table 1. Serial-Interface Programming Commands
12-BIT SERIAL WORD
LDAC FUNCTION
A1 A0 C1 C0 D7 . . . . . . . . D0
0 0 0 1 8-bit DAC data 1 Load input register A; all DAC outputs unchanged.
0 1 0 1 8-bit DAC data 1 Load input register B; all DAC outputs unchanged.
1 0 0 1 8-bit DAC data 1 Load input register C; all DAC outputs unchanged.
1 1 0 1 8-bit DAC data 1 Load input register D; all DAC outputs unchanged.
0 0 1 1 8-bit DAC data 1 Load input register A; all DAC outputs updated
0 1 1 1 8-bit DAC data 1 Load input register B; all DAC outputs updated
1 0 1 1 8-bit DAC data 1 Load input register C; all DAC outputs updated
1 1 1 1 8-bit DAC data 1 Load input register D; all DAC outputs updated.
Software LDAC commands. Update all DACs from
0 1 0 0 XXXXXXXX 1 their respective input registers. Also bring the part out
of shutdown mode.
Load all DACs with shift-register data. Also bring the
1 0 0 0 8-bit DAC data X
part out of shutdown mode.
1 1 0 0 XXXXXXXX X Software shutdown (provided PDE is high)
0 0 1 0 XXXXXXXX X UPO goes low.
0 1 1 0 XXXXXXXX X UPO goes high.
0 0 0 0 XXXXXXXX X No operation (NOP); shift data in shift registers.
Set DOUT phase—SCLK rising (mode 1). DOUT
1 1 1 0 XXXXXXXX X clocked out on rising edge of SCLK. All DACs updated
from their respective input registers.
Set DOUT phase—SCLK falling (mode 0). DOUT
1 0 1 0 XXXXXXXX X clocked out on falling edge of SCLK. All DACs up-
dated from their respective registers (default).

Load All DACs with Shift-Register Data User-Programmable Output (UPO)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 UPO
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 8-Bit Data Output

(LDAC = X) 0 0 1 0 x x x x x x x x Low
0 1 1 0 x x x x x x x x High
When this command is initiated, all four DAC registers (LDAC = X)
are updated with shift-register data. This command
allows all DACs to be set to any analog value within the This command initiates the user-programmable logic
reference range. It can be used to substitute CLR if output for controlling another device across an isolated
code 00 hex is programmed, which clears all DACs. interface. Example devices are gain control of an amplifi-
er and a polarity output for a motor speed control.
Software Shutdown
No Operation (NOP)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 x x x x x x x x A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 x x x x x x x x
(LDAC = X, PDE = H)
(LDAC = X)
This command shuts down all output buffer amplifiers,
reducing supply current to 10µA max. The NOP command (no operation) allows data to be
shifted through the MAX534 shift register without affect-
ing the input or DAC registers. This is useful in daisy
chaining (also see the Daisy Chaining Devices section).

_______________________________________________________________________________________ 9
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
For this command, the data bits are “Don't Cares.” As Serial Data Output
MAX534

an example, three MAX534s are daisy chained (A, B, DOUT is the internal shift register’s output. DOUT can
and C), and devices A and C need to be updated. The be programmed to clock out data on SCLK’s falling
36-bit-wide command would consist of one 12-bit word edge (mode 0) or rising edge (mode 1). In mode 0, out-
for device C, followed by an NOP instruction for device put data lags input data by 12.5 clock cycles, maintain-
B and a third 12-bit word with data for device A. At CS’s ing compatibility with Microwire and SPI. In mode 1,
rising edge, device B will not change state. output data lags input data by 12 clock cycles. On
power-up, DOUT defaults to mode 0 timing. DOUT
Set DOUT Phase—SCLK Rising (Mode 1) never three-states; it always actively drives either high
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 or low and remains unchanged when CS is high.
1 1 1 0 x x x x x x x x

(LDAC = x)

The mode 1 command resets the serial-output DOUT to

transition at SCLK’s rising edge. Once this command is
issued, DOUT’s phase is latched and will not change SCLK SK
except on power-up or if the specific command to set
the phase to falling edge is issued. MAX534 DIN SO
MICROWIRE
This command also loads all DAC registers with the con- PORT
tents of their respective input registers, and is identical to
the “LDAC” command.
CS I/0
Set DOUT Phase—SCLK Falling (Mode 0, Default)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 x x x x x x x x

(LDAC = x)
Figure 4. Connections for Microwire
This command resets DOUT to transition at SCLK’s
falling edge. The same command also updates all DAC
registers with the contents of their respective input reg-
isters, identical to the “LDAC” command.
LDAC Operation (Hardware)
LDAC is typically used in 4-wire interfaces (Figure 7).
This command is level sensitive, and allows asynchro-
nous hardware control of the DAC outputs. With LDAC MAX534 DIN MOSI
low the DAC registers are transparent, and any time an SPI/QSPI
input register is updated, the DAC output immediately PORT
SCLK SCK
follows.
Clear DACs with CLR CS I/0
Strobing the CLR pin low causes an asynchronous
clear of input and DAC registers and sets all DAC out-
puts to zero. Similar to the LDAC pin, CLR can be
invoked at any time, typically when the device is not
selected (CS = H). When the DAC data is all zeros, this
function is equivalent to the “Update all DACs from Shift Figure 5. Connections for SPI/QSPI
Registers” command.

10 ______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
Interfacing to the Microprocessor Analog Section

MAX534
The MAX534 is Microwire™ and SPI™/QSPI™ compati- DAC Operation
ble (Figures 4 and 5). For SPI and QSPI, clear the The MAX534 uses a matrix decoding architecture for
CPOL and CPHA configuration bits (CPOL = CPHA = the DACs, which saves power in the overall system.
0). The SPI/QSPI CPOL = CPHA = 1 configuration can The external reference voltage is divided down by a
also be used if the DOUT output is ignored. resistor string placed in a matrix fashion. Row and col-
The MAX534 can interface with Intel’s 80C5X/80C3X umn decoders select the appropriate tab from the
family in mode 0 if the SCLK clock polarity is inverted. resistor string to provide the needed analog voltages.
More universally, if a serial port is not available, three The resistor string presents a code-independent input
lines from one of the parallel ports can be used for bit impedance to the reference and guarantees a mono-
manipulation. tonic output. Figure 8 shows a simplified diagram of the
Digital feedthrough at the voltage outputs is greatly four DACs.
minimized by operating the serial clock only to update
Reference Input
the registers. The clock idle state is low.
The voltage at REF sets the full-scale output voltage for
Daisy-Chaining Devices all four DACs. The 460kΩ typical input impedance at
Any number of MAX534s can be daisy-chained by con- REF is code independent. The output voltage for any
necting DOUT of one device to DIN of the following DAC can be represented by a digitally programmable
device in the chain. The NOP instruction (Table 1) voltage source as follows:
allows data to be passed from DIN to DOUT without VOUT = (NB x VREF) / 256
changing the input or DAC registers of the passing where NB is the numerical value of the DAC’s binary
device. A 3-wire interface updates daisy-chained or input code.
individual MAX534s simultaneously by bringing CS
high (Figure 6).

MAX534 MAX534 MAX534

SCLK SCLK SCLK SCLK

DIN DIN DOUT DIN DOUT DIN DOUT

CS CS CS CS
TO OTHER
DEVICE A DEVICE B DEVICE C SERIAL DEVICES

MAX534
SCLK SCLK

DIN DIN

CS CS

Figure 6. Daisy-chained or individual MAX534s are simultaneously updated by bringing CS high. Only three wires are required.

______________________________________________________________________________________ 11
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
MAX534

DIN
SCLK
LDAC
CS1
CS2 TO OTHER
SERIAL
CS3 DEVICES

CS CS CS

LDAC MAX534 LDAC MAX534 LDAC MAX534

SCLK SCLK SCLK

DIN DIN DIN

Figure 7. Multiple MAX534s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an
individual CS.

Output Buffer Amplifiers

REF
All MAX534 voltage outputs are internally buffered by
R0 R1 R15
precision unity-gain followers that slew at about
0.6V/µs. The outputs can swing from GND to VDD. With
a 0V to +4V (or +4V to 0V) output transition, the amplifi-
D7 er outputs will typically settle to 1/2LSB in 8µs when
R16 loaded with 10kΩ in parallel with 100pF.
MSB DECODER

D6 The buffer amplifiers are stable with any combination of

resistive (≥10kΩ) or capacitive loads.
D5

D4 R255

LSB DECODER
D3 D2 D1 D0

DAC A

Figure 8. DAC Simplified Circuit Diagram

12 ______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
__________Applications Information Careful PC board layout minimizes crosstalk among

MAX534
DAC outputs and digital inputs. Figure 10 shows sug-
DAC Linearity and Voltage Offset gested circuit board layout to minimize crosstalk.
The output buffer can have a negative input offset volt-
age that would normally drive the output negative, but Unipolar-Output,
since there is no negative supply the output stays at 0V Two-Quadrant Multiplication
(Figure 9). When linearity is determined using the end- In unipolar operation, the output voltages and the refer-
point method, it is measured between zero code (all ence input are the same polarity. Figure 11 shows the
inputs 0) and full-scale code (all inputs 1) after offset MAX534 unipolar configuration, and Table 2 shows the
and gain error are calibrated out. However, in single- unipolar code.
supply operation the next code after zero may not
change the output, so the lowest code that produces a SYSTEM GND
positive output is the lower endpoint.
Power Sequencing OUTC OUTB
The voltage applied to REF should not exceed VDD at
OUTD OUTA
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and AGND REF
VDD to ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.
Power-Supply Bypassing
and Ground Management
Connect AGND and DGND together at the IC. This
ground should then return to the highest-quality ground
available. Bypass VDD with a 0.1µF capacitor, located Figure 10. Suggested PC Board Layout for Minimizing
as close to VDD and DGND as possible. Crosstalk (Bottom View)

REFERENCE INPUT +3V

3 13
REFAB VDD
MAX534
2
DAC A OUTA

OUTPUT
VOLTAGE 1
DAC B OUTB
SERIAL
INTERFACE
NOT SHOWN
16
0V
DAC C OUTC
NEGATIVE DAC CODE
OFFSET

15
DAC D OUTD

AGND DGND
14 12

Figure 9. Effect of Negative Offset (Single Supply) Figure 11. Unipolar Output Circuit

______________________________________________________________________________________ 13
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
MAX534

Table 2. Unipolar Code Table

DAC CONTENTS ANALOG

MSB LSB OUTPUT

1111 1111 (
255
+VREF –––– )
256

1000 0001 (
129
+VREF –––– )
256

1000 0000 128 = +V––––

+VREF ––––( REF
)
256 2

127
0111 1111 (
+VREF –––– )
256

1
0000 0001 (
+VREF –––– )
256
0000 0000 0V

1 )
Note: 1LSB = (VREF) (2-8) = +VREF (––––
256

_________________________________________________________Functional Diagram

DOUT CLR LDAC UPO PDE VDD REF DGND AGND

DECODE MAX534
CONTROL
OUTA
INPUT DAC
DAC A
REGISTER A REGISTER A

OUTB
12-BIT INPUT DAC
DAC B
SHIFT REGISTER B REGISTER B
REGISTER

OUTC
INPUT DAC
DAC C
REGISTER C REGISTER C

OUTD
SR INPUT DAC
DAC D
CONTROL REGISTER D REGISTER D

CS DIN SCLK

14 ______________________________________________________________________________________
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
___________________Chip Information

MAX534
TRANSISTOR COUNT: 6821

________________________________________________________Package Information
INCHES MILLIMETERS INCHES MILLIMETERS
DIM DIM PINS
MIN MAX MIN MAX MIN MAX MIN MAX
A 0.061 0.068 1.55 1.73 D 16 0.189 0.196 4.80 4.98
D A1 0.004 0.0098 0.127 0.25 S 16 0.0020 0.0070 0.05 0.18
A2 0.055 0.061 1.40 1.55 D 20 0.337 0.344 8.56 8.74
A B 0.008 0.012 0.20 0.31 S 20 0.0500 0.0550 1.27 1.40
C 0.0075 0.0098 0.19 0.25 D 24 0.337 0.344 8.56 8.74
D SEE VARIATIONS S 24 0.0250 0.0300 0.64 0.76
e E 0.150 0.157 3.81 3.99 D 28 0.386 0.393 9.80 9.98
B A1
e 0.25 BSC 0.635 BSC S 28 0.0250 0.0300 0.64 0.76
H 0.230 0.244 5.84 6.20 21-0055A
h 0.010 0.016 0.25 0.41
S
L 0.016 0.035 0.41 0.89
N SEE VARIATIONS
S SEE VARIATIONS
α 0° 8° 0° 8°
E H
QSOP
h x 45°
QUARTER
α
A2 SMALL-OUTLINE
N
PACKAGE
E
C L

______________________________________________________________________________________ 15
 +5V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
________________________________________________________Package Information
MAX534

INCHES MILLIMETERS
DIM
MIN MAX MIN MAX
E1 A – 0.200 – 5.08
B 0.014 0.023 0.36 0.58
D E
A B1 0.038 0.065 0.97 1.65
C 0.008 0.015 0.20 0.38
E 0.220 0.310 5.59 7.87
E1 0.290 0.320 7.37 8.13
e 0.100 2.54
L 0.125 0.200 3.18 5.08
Q 0°-15°
L1 0.150 – 3.81 –
L L1 Q 0.015 0.070 0.38 1.78
e C
B1 S – 0.098 – 2.49
S1 0.005 – 0.13 –
B

S1 S INCHES MILLIMETERS
DIM PINS
MIN MAX MIN MAX
CERDIP
D 8 – 0.405 – 10.29
CERAMIC DUAL-IN-LINE D 14 – 0.785 – 19.94
PACKAGE D 16 – 0.840 – 21.34
D 18 – 0.960 – 24.38
(0.300 in.)
D 20 – 1.060 – 26.92
D 24 – 1.280 – 32.51
21-0045A

INCHES MILLIMETERS
E DIM
MIN MAX MIN MAX
E1 A – 0.200 – 5.08
D
A1 0.015 – 0.38 –
A3 A2 0.125 0.175 3.18 4.45
A3 0.055 0.080 1.40 2.03
A A2
B 0.016 0.022 0.41 0.56
B1 0.045 0.065 1.14 1.65
C 0.008 0.012 0.20 0.30
L A1 D1 0.005 0.080 0.13 2.03
0° - 15°
E 0.300 0.325 7.62 8.26
C E1 0.240 0.310 6.10 7.87
e e 0.100 – 2.54 –
B1 eA
B eA 0.300 – 7.62 –
eB eB – 0.400 – 10.16
L 0.115 0.150 2.92 3.81
D1
INCHES MILLIMETERS
Plastic DIP PKG. DIM PINS
MIN MAX MIN MAX
PLASTIC P D 8 0.348 0.390 8.84 9.91
P D 14 0.735 0.765 18.67 19.43
DUAL-IN-LINE
P D 16 0.745 0.765 18.92 19.43
PACKAGE P D 18 0.885 0.915 22.48 23.24
(0.300 in.) P D 20 1.015 1.045 25.78 26.54
N D 24 1.14 1.265 28.96 32.13
21-0043A

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

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