Unit 3

Addressing Modes of 8086

Addressing modes indicates a way of locating data or operands.
Depending upon the data type used in the instruction and the memory-
addressing mode. any instruction may belong to one or more addressing
modes or some instruction may not belong to any of the addressing
modes.
Thus the addressing modes describe the types of operands and the way
they are accessed for executing an instruction. According to the flow of
instruction execution, the instructions may be categorized as:
(i) Sequential control flow instructions:- Sequential control flow
instructions are the instructions which after execution, transfer the
control to the next instruction appearing immediately after it in the
program e.g. the arithmetic, logical, data transfer and process control
instructions.
(ii) Control transfer instructions:- The control transfer instructions
transfer the control to some predefined address of the memory somehow
specified in the instruction, after their execution e.g. INT, CALL, JMP, RET
etc.
The addressing modes of the sequential control transfer instructions are
given as follows:
1. Immediate addressing mode :
In this mode, the immediate data is the part of the instruction and appear
in the form of successive byte or bytes.
So immediate data may be 8 bit [byte) or 16 bit [word] in length.
Immediate data can be accessed quickly as they are available in an
instruction queue, hence no extra bus cycle is required to read data.
Examples:
MOV AL, 46H AL is loaded with 8 bit immediate data 46H.
MOV BX, 1234 BX is loaded with 16 bit imunediate data 1234H.
2. Direct addressing mode :
In this mode, a 16-bits memory address (offset) of operand is directly
specified in the instruction as a part of it.
The offset of displacement may be either 8 bit or 16 bit which follows the
instruction op-code
So, the physical address is calculated by adding this offset to the base
segment registers ie. CS, DS, ES, SS
Examples:
MOV AL, [3000H] AL will be loaded with the content of memory
location whose offset is 3000H from base
address.
AND AX, [8000H] AX will be ANDed with the content of memory
location whose offset is 8000H from the base.
In above examples, DS is the default base address register
3. Register addressing mode:
In this mode, the data is stored in a registers and it is referred using the
particular register ie. all register except IP may be used in this mode
Register may be source operands, destination operand or both.
The instruction of this addressing mode are compact and faster in
execution as all registers are reside in chip and no external bus is
required to read data.
Registers may be 8 bit or 16 bit.
Examples:
MOV AX, CX Copies the content of CX reg. to AX reg
AND AL, BL ANDing the content of BL with AL, store result in AL
ROR AL, CL Rotate the contents of AL CL times.
4. Register indirect addressing mode:
In this mode, the address of the memory location that contains data or
operand is determined in an indirect way, using offset register such as
BX, SI, Dl register.
The default segment register is either DS or ES.
Examples:
MOV AX, [BX] Copies the contents of memory location whose offset is
in BX register.
SUB [SI], AL Subtract the content of AL from the memory location
whose offset is in Sl register and store result in same
memory location.
5. Indexed addressing modes:
In this mode, the offset of the operand is stored in one of the index
register DS and ES are the default segments for index register SI and Di
respectively.
This mode allows the use of a signed displacement
Examples:
MOV BL, [SI] Copies the byte from memory location whose offset is
in index register Sl to AL
ADD AX, [DI+8] Copies the word from memory location whose offset
will be calculated by adding 8 with the content of DI
register.
6. Register relative addressing mode:
In this mode, the data is available at an effective address formed by
adding 8-bits or 16-bits displacement with content of any one of the
registers such as BX, BP, SI and DI in the default DS and ES segment.
Examples:
MOV AX, 50[BX] Copies the word from memory location whose offset
will be calculated by adding the 50 with the content of
BX register.
ADD AX, 5000[BP] Copies the word from memory location whose offset
will be calculated by adding 5000H to the content of
BP register.
7. Base indexed addressing mode:
In this mode, the effective address of data is formed by adding the
content of a base register BX or BP to the content of an index register SI
or DI with default segment DS and ES.
Examples:
MOV AX,[BX+SI] Copies the word from memory location whose offset is
calculated by adding the content of BX with the
contents of Sl.
ADD AL,[BX+DI] Copies the byte from memory location whose offset is
calculated by adding the content of BX with the
contents of DI
8. Relative base indexed addressing mode:
In this mode, the effective address of data is calculated by adding the 8-
bits or 16-bits displacement with the sum of base register BX or BP and
Index register SI or DI.
Examples:
MOV AX, [BX+SI+60h] Copies word from memory location whose offset
is calculated by adding the 60H with the contents
of BX and St ie. [60+Bx+SI]
9. Implied addressing mode: In this mode, the operands are implied and
are hence not specified in the instruction.
Example:
STC-This sets the carry flag.
CLP - Clears Direction flag

Types of instructions set

1 Data transfer/Copy instructions: These types of instruction are used to
transfer data from source operand to destination operand. All the store,
move, load, exchange, input and output instructions come in this
category.
2. Arithmetic and Logical instructions: These type instructions are used
to perform arithmetic and logical, increment, decrement, compare and
scan operation.
3. Branch Instructions: This type of instruction are used to transfer the
control of execution to the specified address e g. call, jump and return
instructions.
4. Loop instructions: If these instructions have REP prefix with CX used as
count register, they can be used to implement unconditional and
conditional loops The LOOP, a LOOPNZ and LOOPZ instruction belongs to
this category
5. Machine control instructions: These instructions control the status of
machine. NOP, HLT, WAIT and LOCK instructions are the example of this
type
6. Flag manipulation instructions: All the instructions, which directly
affect the flag register, come under this group of instructions such as
CL.D. STD, CLI, STI etc
7. Shift and rotate instructions: These instructions involve the bit-wise
shifting or rotation in either direction with or without a count in CX.
8. String instructions: These instructions are used to perform various
string manipulation operations such as load, move, scan, compare, store
etc
MOV :
Syntax MOV Destination, source.
This instruction copies a word or a byte of data from some source to a
destination.
The destination can be a register or a memory location. The source can
be a register, a memory location, or an immediate number.
Examples:
MOV AX,BX
MOV AX,5000H
MOV AX,[SI]
MOV AX,[2000H]
MOV AX,50H[BX]
MOV [734AH],BX
MOV DS,CX
MOV CL,[357AH]
Direct loading of the segment registers with immediate data is not
permitted.
PUSH : Push to Stack
Syntax PUSH source.
This instruction pushes the contents of the specified register/memory
location on to the stack. The stack pointer is decremented by 2, after
each execution of the instruction.
Examples
PUSH AX
PUSH DS
PUSH [5000H]

Fig. Push Data to stack memory

POP : Pop from Sack

Syntax POP Destination.
This instruction when executed, loads the specified register/memory
location with the contents of the memory location of which the address is
formed using the current stack segment and stack pointer.
The stack pointer is incremented by 2
Example
POP AX
POP DS POP
[5000H]
 Fig. Popping Register Content from Stack Memory
XCHG : Exchange byte or word
Syntax XCHG Destination, source.
This instruction exchange the contents of the specified source and
destination operands
Examples.
XCHG [5000H], AX
XCHG BX, AX

XLAT :
The XLAT instruction replaces a byte in the AL register with byte from a
look up table in memory.
Examples.
LEA BX, TABLE1
MOV AL, 04H
XLAT

Simple input and output port transfer Instructions:

IN:
Syntax IN Accumulator, port.
This instruction Copies a byte or word from specified port to
accumulator which can be AL or AX.
Examples.
IN AL, 03H
IN AX, DX

OUT:
Syntax OUT Port, Accumulator,.
This instruction Copies a byte or word from accumulator to specified
port.
Examples.
OUT 03H, AL
OUT DX, AX
LEA :
Syntax LEA 16 bit register, source.
Load effective address of operand in specified register.
[reg] offset portion of address in DS
Eg. LEA reg, offset
LEA BX, ARRAY.

LDS:
Syntax LDS 16 bit register, memory address of first register.
These instructions copy a word from two consecutive memory locations
into the register specified in the instruction. It then copies a word from
next two consecutive memory location into the DS register.
[reg] [mem]
[DS] [mem + 2]
Examples.
LDS reg, mem
LDS BX, [1234H]

LES:
Syntax LES 16 bit register, memory address of first register.
These instructions copy a word from two consecutive memory locations
into the register specified in the instruction. It then copies a word from
next two consecutive memory location into the ES register.
[reg] [mem]
[ES] [mem + 2]
Examples.
LES reg, mem
LES BX, [1234H]

Flag transfer instructions:

LAHF:
Load (copy to) AH with the lower byte of the 16 bit flag register.
[AH] [ Flags low byte]
Examples.
LAHF

SAHF:
Store (copy) AH register to lower byte of the 16 bit flag register.
[Flags low byte] [AH]
Examples.
SAHF
PUSHF:
This instruction decrements the stack pointer by two and copies the
word in the flag register to the memory locations pointed by the stack
register.
[SP] [SP] – 2
[[SP]] [Flags]
Examples.
PUSHF
POPF :
This instruction copies a word from the memory locations at the top of
stack to the flag register and increment stack pointer by two.
[Flags] [[SP]]
[SP] [SP] + 2
Examples.
POPF

Arithmetic Instructions:
The 8086 provides many arithmetic operations: addition, subtraction,
negation, multiplication and comparing two values.
ADD :
Syntax ADD destination, source.
The add instruction adds the contents of the source operand to the
destination operand & result is store in destination.
Examples.
ADD AL, 74h Add the content of AL & 74h and result is stored in ax
register
ADD AX, BX Add the content of ax & bx and result is stored in ax
register

ADC : Add with Carry

Syntax ADC destination, source.
This instruction performs the same operation as ADD instruction, but
adds the carry flag to the result.
Examples.
ADC AX,BX Add the content of ax & bx along with carry & result is
stored in ax
ADC AX, 1254H Add the content of ax & 1254h along with carry & result
is stored in ax

SUB : Subtract
Syntax SUB destination, source.
The subtract instruction subtracts the source operand from the
destination operand and the result is stored in the destination operand.
Examples.
SUB AX, 0100H Subtract content of ax register to 0100h & result is
stored in ax.
SUB AX, BX Subtract content of ax register to content of bx register
& result is stored in ax

SBB : Subtract with Borrow

Syntax SBB destination, source.
The subtract with borrow instruction subtracts the source operand and
the borrow flag (CF) generated due to the previous calculations, from the
destination operand
Examples.
SBB AX,BX Subtract content of ax register to content of bx register along
with borrow from carry flag & result is stored in ax
SBB AL, [SI] Subtract content of al register to content of number whose
offset is SI, along with borrow from carry flag.

INC : Increment
Syntax INC destination.
This instruction adds 1 to the contents of the specified Register or
memory location.
Immediate data cannot be operand of this instruction.
Examples
INC AX Increment the content of ax register by 1
INC [BX] Increment the content by 1

DEC : Decrement
Syntax DEC destination.
The decrement instruction subtracts 1 from the contents of the specified
register or memory location.
Examples
DEC AX Decrement the content of ax register by 1
DEC [5000H] Decrement the content by 1

NEG : Negate
Syntax NEG destination.
The negate instruction forms 2`s complement of the specified
destination in the instruction. The destination can be a register or a
memory location. This instruction can be implemented by inverting each
bit and adding 1 to it.
Examples
NEG AL
Before- AL = 0011 0101 35H Replace number in AL with its 2‟s
complement
After- AL = 1100 1011 CBH

CMP : Compare
Syntax CMP destination, destination
This instruction compares a data from source with a the data from
destination. The comparison is actually done by non-destructive
subtraction of the source byte or word from the destination byte or word
i.e. the source and the destination will not changed, but the flags will set
to indicate the results of the comparison.
Operation:
(a) If destination > source then CF=0, ZF=0, SF=0
(b) If destination < source then CF=1, ZF=0, SF=1
(c) If destination = source then CF=0, ZF=1 , SF=0
Examples:
CMP AL, OFFH Compare AL with immediate number FFH
CMP AX, BX Compare AX with BX
MUL :Unsigned Multiplication Byte or Word
This instruction multiplies an unsigned byte or word by the contents of
AL/AX. If source is of 8 bits, it will multiply with AL and result will be
stored in AX register.
If source is of 16 bits, it will multiply with AX and result will be stored in
DX & AX registers.

Example
MUL BH Multiply AH by BH, result in AX.
MUL CX Multiply Ax by Cx, result in DX & AX.
MUL WORD PTR [SI] Multiply AL by bytes in Ds pointed by SI, result in ax

IMUL :Signed Multiplication

This instruction multiplies a signed byte in source operand by a signed
byte in AL or a signed word in source operand by a signed word in AX. If
source is of 8 bits, it will multiply with AL and result will be stored in AX
register.
If source is of 16 bits, it will multiply with AX and result will be stored in
DX & AX registers.

Example
IMUL BH Multiply AH by BH, result in AX.
IMUL CX Multiply Ax by Cx, result in DX & AX.
MUL WORD PTR [SI] Multiply AL by bytes in Ds pointed by SI, result in ax

DIV : Unsigned division

This Instruction performs Division. It Divides a word by byte and a
Double word by word. If divisor is of 8 bits, it will divides with AX and
result of quotient will be there in AL register & reminder will be stored in
AH register. If divisor is of 16 bits, it will divides with DX-AX double word
and result of quotient will be there in AX register & reminder will be
stored in DX register.

Example
MUL BL Divide AL by BL, Quotient in AL & remainder in AH.
MUL CX Divide AL by BL, Quotient in AX & remainder in DX.
MUL WORD PTR [SI] Divide AL by bytes in DS pointed by SI.

CBW : Convert Signed Byte to Word

Syntax CBW
This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said to be signed extension of AL.
Eg. CBW
AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX.
Result in AX = 1111 1111 1001 1000
CWD : Convert Signed Word to Double Word
Syntax CWD
This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said to be signed extension of AL.
Eg. CWD
Convert signed word in AX to signed double word in DX : AX
DX= 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

AAA : ASCII Adjust After Addition

Syntax AAA
The AAA instruction is executed after an ADD instruction that adds two
ASCII coded operand to give a byte of result in AL. The AAA instruction
converts the resulting contents of Al to a unpacked decimal digits.
The higher nibble of the AL register is filled with zeros.
Operation:
1. Clear the high order nibble of AL i.e. AL-AL AND OF.
2 If lower nibble of AL>9 or AI=I then.
(a) AL=AL+6
(b) AH=AH+I
(c) AF=CF=I
(d) AL=AL, AND 0Fh
Example:
AAA
Before the execution of AAA, suppose AH=00H AL=0HH
After the execution of AAA AH=0111~AL=01H

AAS : ASCII Adjust AL after Subtraction

Syntax AAS
This instruction corrects the result in AL register after subtracting two
unpacked ASCII operands. The higher nibble of the Al register is filled
with zeros. This instruction should be executed after the SUB instruction
and the result is placed in the AL register.
Operation:
1 Clear the higher order nibble of i.e.AL=AL AND OF
2 If lower nibble of AL>9 or AF=1 then
(a) AL= AL-6
(b) AH= AH-1
(c) AF= CF= 1
(d) AL=AL AND 0Fh.
Example:
AAS
Before the execution of AAS suppose AH=02H AL=0BH
After the execution of AAS AH=01H, AL=05H

AAM : ASCII Adjust after Multiplication

Syntax AAM
This instruction, after execution, converts the product available In AL
into unpacked BCD format.
This instruction should be issued after the multiplication instruction.
Example
AAM

AAD : ASCII Adjust before Division

Syntax AAD
This instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before
dividing the two unpacked BCD digits in AX by an unpacked BCD byte.
This instruction is used after division
Example
AX 05 08
AAD result in AL 00 3A 58D = 3A H in AL
The result of AAD execution will give the hexadecimal number 3A in AL
and 00 in AH. Where 3A is the hexadecimal Equivalent of 58 (decimal).

DAS (Decimal adjust after subtraction):

Syntax DAS
This instruction is used to convert the result of the subtraction of two
packed BCD numbers to a valid BCD number.
The working of DAS instruction is given below.
(a) If lower nibble of AL > 9 or AF=1, then AL=AL - 06.
(b) If higher nibble of AL > 9 or CF=1, then AL = AL - 60.
(c) If both above condition are satisfied, then AL = AL - 66.

DAA (Decimal adjust after Addition):

Syntax DAA
This instruction is used to convert the result of the Addition of two
packed BCD numbers to a valid BCD number.
The working of DAS instruction is given below.
(a) If lower nibble of AL > 9 or AF=1, then AL=AL + 06.
(b) If higher nibble of AL > 9 or CF=1, then AL = AL + 60.
(c) If both above condition are satisfied, then AL = AL + 66.

Logical Instructions

AND : Logical AND

Syntax AND destination, source.
This instruction bit by bit ANDs the source operand that may be an
immediate register or a memory location to the destination operand that
may a register or a memory location. The result is stored in the
destination operand.
Example
AND AX, 0008H AND word in AX with word 0008h, result stored in AX
AND Ah, Bh AND byte in Ah with byte in Bh, result stored in Ah
OR : Logical OR
Syntax OR destination, source.
This instruction bit by bit ORs the source operand that may be an
immediate, register or a memory location to the destination operand that
may a register or a memory location. The result is stored in the
destination operand.
Example
OR AX, 0008H OR word in AX with word 0008h, result stored in AX
OR AX, BX OR byte in Ah with byte in Bh, result stored in Ah

NOT : Logical Invert

Syntax NOT destination.
This instruction complements the contents bit by bit of an operand
register or a memory location.
Example
NOT AX Converts the content of AX into its 1`s complement
NOT [5000H] Converts the content of the memory location 5000h
into its 1`s complement

XOR : Logical Exclusive OR

Syntax XOR destination, source.
This instruction bit by bit XORs the source operand that may be an
immediate, register or a memory location to the destination operand that
may a register or a memory location. The result is stored in the
destination operand.
Example
XOR AX, 0098H XOR word in AX with word 0008h, result stored in AX
XOR Ah, Bh XOR byte in Ah with byte in Bh, result stored in Ah

TEST : Logical Compare Instruction

Syntax TEST destination, source.
The TEST instruction performs a bit by bit logical AND operation on the
two operands. The result of this ANDing operation is not available for
further use, but flags are affected. TEST instructions often used to set the
flags before a conditional jump instruction
Example
TEST AX, BX AND word in AX with word in BX, no result, update flag-
PF, SF, ZF.
TEST Bh, 06H AND byte in Bh with byte 06h, no result, update flag-
PF, SF, ZF.
SHIFT AND ROTATE INTRUCTIONS
ROR [Rotate right without Carry]
Syntax ROR destination, count.
This instruction rotates all of the bits of the specified byte or word
count times toward right. The bit moved out of LSB is rotated around into
the MSB and also copied to CF.
Examples
ROR BL, 1 Rotate all bits in BL, right by one bit position
Before: CF-0 BL=0011 1011
After: CF-1 BL=1001 1101

RCR [Rotate right with Carry]

Syntax RCR destination, count.
This instruction rotates all of the bits of the specified byte or word count
times toward right. i.e. The LSB of the operand is rotated into carry flag &
the bit in carry flag is moved to MSB of the operand.
Examples
RCR BL, 1 Rotate all bits in BL right by one bit position
Before: CF-0 BL=1011 1011
After: CF-1 BL=0101 1101

ROL [Rotate LEFT without Carry]

Syntax ROL destination, count.
This instruction rotates all of the bits of the specified byte or word
count times toward left. The bit moved out of MSB is rotated around into
the LSB and also copied to CF.
Examples
ROL BL, 1 Rotate all bits in BL, left by one bit position
Before: CF-0 BL=0011 1011
After: CF-1 BL=0111 0110

RCL [Rotate LEFT with Carry]

Syntax RCL destination, count.
This instruction rotates all of the bits of the specified byte or word count
times toward left. i.e. The MSB of the operand is rotated into carry flag &
the bit in carry flag is moved to LSB of the operand.
Examples
RCL BL, 1 Rotate all bits in BL, right by one bit position
Before: CF-0 BL=1011 1011
After: CF-1 BL=0111 0110

SAL/SHL :
Syntax SAL/SHL destination, count.
SAL and SHL are two mnemonics for the same instruction. This
instruction shifts each bit in the specified destination to the left and 0 is
stored at LSB position. The MSB is shifted into the carry flag. The
destination can be a byte or a word. It can be in a register or in a memory
location. The number of shifts is indicated by count.
CF --- MSB -------------- LSB-----0

Examples.
SAL BX, 1 Shift the content of BX register by one toward left.
Before: CF-0 BL=1011 1011
----------
After: CF-1 BL=0111 0110

SHR :
Syntax SHR destination, count
This instruction shifts each bit in the specified destination to the right
and 0 is stored at MSB position. The LSB is shifted into the carry flag. The
destination can be a byte or a word. It can be a register or in a memory
location. The number of shifts is indicated by count.
0 -- MSB ------------- LSB---CF

Example.
SHR BX, 1 Shift the content of BX register by one toward right.
Before: CF-0 BL=1011 1011
-------------
After: CF-1 BL=0101 1101

SAR :
Syntax SAR destination, count
This instruction shifts each bit in the specified destination some number
of bit positions to the right. As a bit is shifted out of the MSB position, a
copy of the old MSB is put in the MSB position i.e the sign bit is copied
into MSB. The LSB will be shifted into CF.

------
-- MSB ------------- LSB---CF
Example
SAR BX, 1 Shift the content of BX register by one toward right.
Before: CF-0 BL=1011 1011
 -------------
After: CF-1 BL=1101 1101

Unconditional Branch Instructions :

In Unconditional control transfer instructions, the execution control is
transferred to the specified location independent of any status or
condition. The CS and IP are unconditionally modified to the new CS and
IP.

CALL : Unconditional Call

This instruction is used to call a Subroutine (Procedure) from a main
program. Address of procedure may be specified directly or indirectly.
There are two types of procedure depending upon whether it is available
in the same segment or in another segment.
i. Near CALL i.e., ±32K displacement.
ii. For CALL i.e., anywhere outside the segment.
On execution this instruction stores the incremented IP & CS onto the
stack and loads the CS & IP registers with segment and offset addresses
of the procedure to be called.

RET: Return from the Procedure.

At the end of the procedure, the RET instruction must be executed. When
it is executed, the previously stored content of IP and CS along with Flags
are retrieved into the CS, IP and Flag registers from the stack and
execution of the main program continues further.

INT N: Interrupt Type N.

In the interrupt structure of 8086, 256 interrupts are defined
corresponding to the types from 00H to FFH. When INT N instruction is
executed, the type byte N is multiplied by 4 and the contents of IP and CS
of the interrupt service routine will be taken from memory block in 0000
segment.

INTO: Interrupt on Overflow

This instruction is executed, when the overflow flag OF is set. This is
equivalent to a Type 4 Interrupt instruction.

JMP: Unconditional Jump

This instruction unconditionally transfers the control of execution to the
specified address using an 8-bit or 16-bit displacement. No Flags are
affected by this instruction.

IRET: Return from ISR

When it is executed, the values of IP, CS and Flags are retrieved from the
stack to continue the execution of the main program.
LOOP : LOOP Unconditionally
This instruction executes the part of the program from the Label or
address specified in the instruction upto the LOOP instruction CX number
of times. At each iteration, CX is decremented automatically and JUMP IF
NOT ZERO structure.
Example:
MOV CX, 0004H
MOV BX, 7526H
Label 1 MOV AX, CODE
OR BX, AX
LOOP Label 1
CONDITIONAL BRANCH INSTRUCTION
JMP LABLE : It will jump program control to LABLE (Address). There are
many conditional jump instructions with 8086.
JC (Jump If Carry = 1)
JNC (Jump If Carry = 0)
JZ (Jump If Zero = 1)
JNZ (Jump If Zero = 0}
JP (Jump If Parity = 1)
JNP (Jump If Parity = 0}
JO (Jump If Overflow = 1)
JNO (Jump If Overflow = 0}
JS (Jump If Sign = 1}
JNS (Jump If Sign = 0}
CALL LABLE
It will jump program control to LABLE (Address). Before that it stores
return address on stack. This instruction is used to execute subroutine
(FUNCTION).

String Manipulation Instructions

A series of data byte or word available in memory at consecutive
locations, to be referred as Byte String or Word String. A String of
characters may be located in consecutive memory locations, where each
character may be represented by its ASCII equivalent.
The 8086 supports a set of more powerful instructions for string
manipulations for referring to a string, two parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
The length of the string is usually stored as count in the CX register.The
incrementing or decrementing of the pointer, in string instructions,
depends upon the Direction Flag (DF) Status. If it is a Byte string
operation, the index registers are updated 14 by one. On the other hand,
if it is a word string operation, the index registers are updated by two.

REP : Repeat Instruction Prefix

This instruction is used as a prefix to other instructions, the instruction
to which the REP prefix is provided, is executed repeatedly until the CX
register becomes zero (at each iteration CX is automatically decremented
by one).
i. REPE / REPZ- repeat operation while equal / zero.
ii. REPNE / REPNZ - repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.

MOVSB / MOVSW :Move String Byte or String Word

Suppose a string of bytes stored in a set of consecutive memory locations
is to be moved to another set of destination locations.The starting byte of
source string is located in the memory location whose address may be
computed using SI (Source Index) and DS (Data Segment) contents. The
starting address of the destination locations where this string has to be
relocated is given by DI (Destination Index) and ES (Extra Segment)
contents.

CMPS : Compare String Byte or String Word

The CMPS instruction can be used to compare two strings of byte or
words. The length of the string must be stored in the register CX. If both
the byte or word strings are equal, zero Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter)
becomes zero or the condition specified by the REP Prefix is False.

SCAN : Scan String Byte or String Word

This instruction scans a string of bytes or words for an operand byte or
word specified in the register AL or AX. The String is pointed to by ES:DI
register pair. The length of the string s stored in CX. The DF controls the
mode for scanning of the string. Whenever a match to the specified
operand, is found in the string, execution stops and the zero Flag is set.
If no match is found, the zero flag is reset.

LODS : Load String Byte or String Word

The LODS instruction loads the AL / AX register by the content of a string
pointed to by DS : SI register pair. The SI is modified automatically
depending upon DF, If it is a byte transfer (LODSB), the SI is modified by
one and if it is a word transfer (LODSW), the SI is modified by two. No
other Flags are affected by this instruction.

STOS : Store String Byte or String Word

The STOS instruction Stores the AL / AX register contents to a location in
the string pointer by ES : DI register pair. The DI is modified accordingly,
No Flags are affected by this instruction. The direction Flag controls the
String instruction execution, The source index SI and Destination Index
DI are modified after each iteration automatically. If DF=1, then the
execution follows autodecrement mode, SI and DI are decremented
automatically after each iteration. If DF=0, then the execution follows
autoincrement mode. In this mode, SI and DI are incremented
automatically after each iteration.

Flag Manipulation and a Processor Control Instructions

These instructions control the functioning of the available hardware
inside the processor chip. These instructions are categorized into two
types:
1. Flag Manipulation instructions.
2. Machine Control instructions.

Flag Manipulation instructions

The Flag manipulation instructions directly modify some of the Flags of
8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.

Machine Control instructions

The Machine control instructions control the bus usage and execution

WAIT:
The instruction WAIT causes processor to enter into an ideal state or a
wait state and continues to remain in that the processor receives state
until one of the following signal.
1. Signal on processor TEST pin.
2. A valid interrupt on INTR pin.
3. A valid interrupt on NMI pin.
This signal is used to synchronize with other external hardware such as
math co-processor 8087.

LOCK:
This instruction prevents other processors to take the control of shared
resources. In multiprocessor system, the individual processors have their
own local buses and memory and then processor are connected together
by a system bus to access the shared system resources such as disk
drives or memory or DMA.
Example:
LOCK IN AL, 80H

HLT: Halt
The instruction HLT causes the processor to enter the halt state. The CPU
stops fetching and executing of the instruction.
The CPU can be brought out of the halt state with the occurrence of any
one of the following events.
1. Interrupt signal on INTR pin.
2. Interrupt signal on NMI pin.
3. Reset signal on RESET pin.

NOP: No Operation:
This instruction is used to add wait state of three-clock cycles and during
these three clock cycles CPU dose not perform any operation. This
instruction can be used to add delay loop in the program and delaying
the operation before proceeding to read or write from the port.