VNH7070BAS

Automotive fully integrated H-bridge motor driver

Datasheet - production data

Description
The device is a full bridge motor driver intended
SO-16N for a wide range of automotive applications. The
device incorporates a dual monolithic high-side
GAPGCFT00648 driver and two low-side switches.
Both switches are designed using
Features STMicroelectronics’ well known and proven
proprietary VIPower® M0-7 technology that allows
to efficiently integrate on the same die a true
Type RDS(on) Iout VCCmax Power MOSFET with an intelligent
70 mtyp signal/protection circuitry. The three dies are
VNH7070BAS 15 A 38 V assembled in SO-16N package on electrically
per leg)
isolated lead-frames.

 AEC-Q100 qualified Moreover, its fully symmetrical mechanical design

allows superior manufacturability at board level.
 Output current: 15 A The input signals INA and INB can directly
 3 V CMOS-compatible inputs interface the microcontroller to select the motor
 Undervoltage shutdown direction and the brake condition. A SEL0 pin is
available to address the information available on
 Overvoltage clamp the CS to the microcontroller. The CS pin allows
 Thermal shutdown to monitor the motor current by delivering a
 Cross-conduction protection current proportional to the motor current value.
The PWM, up to 20 kHz, allows to control the
 Current and power limitation speed of the motor in all possible conditions. In all
 Very low standby power consumption cases, a low level state on the PWM pin turns off
 Protection against loss of ground and loss of both the LSA and LSB switches.
VCC
 PWM operation up to 20 kHz Table 1. Device summary

 CS diagnostic functions Order codes

Package
– Analog motor current feedback Tube Tape and reel
– Output short to ground detection
SO-16N — VNH7070BASTR
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
 Output protected against short to ground and
short to VCC
 Standby Mode
 Half Bridge Operation
 Package: ECOPACK®

March 2017 DocID029595 Rev 2 1/38

This is information on a product in full production. www.st.com
Contents VNH7070BAS

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 OFF-state open-load detection – External circuitry dimensioning . . . . . . 23
3.3 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24
3.4 Device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 SO16-N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1 Thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28
4.2.2 Thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1 SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/38 DocID029595 Rev 2

VNH7070BAS List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs (INA, INB) (VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . 10
Table 8. Switching (VCC = 13 V, RLOAD = 3.7 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C). . . . . . . . . . . . . 11
Table 10. CS (7 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. On-state fault conditions- truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Off-state -truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Thermal model for junction temperature calculation in steady-state conditions . . . . . . . . . 29
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. SO-16N carrier tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DocID029595 Rev 2 3/38

3
List of figures VNH7070BAS

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input reset time for HSD - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input reset time for LSD - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . . . 17
Figure 12. Normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. OUT shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Application schematic with reverse battery protection connected to Vbatt . . . . . . . . . . . . . 22
Figure 16. Application schematic with reverse battery protection connected to GND . . . . . . . . . . . . . 22
Figure 17. Suggested PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Multi-motors configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2 . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. PCB 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Chipset configuration in steady state conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air condition . . . . . . . . 29
Figure 25. HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 26. LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. Electrical equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 28. SO-16N package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 29. SO-16N reel 13” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 30. SO-16N rcarrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 31. SO-16N schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 32. SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/38 DocID029595 Rev 2

VNH7070BAS Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V CC

POWER
LIMITATION

LSA_OVERTEMPERATURE LSB_OVERTEMPERATURE

HSA_OVERTEMPERATURE UV HSB_OVERTEMPERATURE

CLAMP HS A CLAMP HS B

HS A DRIVER DRIVER HS B
HS A
LOGIC HS B

Open-load Open-load
OFF-state A CURRENT CURRENT OFF-state B
LIMITATION A LIMITATION B
FAULT
OUT A 1/K 1/K OUT B
DETECTION
CLAMP LS A CLAMP LS B

DRIVER DRIVER
LS A LS B
LS A LS B
MUX

OVERLOAD OVERLOAD
DETECTOR A DETECTOR B

GND A IN A CS SEL0 INB PWM GND B

GAPGCFT01189

Table 2. Block description

Name Description

Allows the turn-on and the turn-off of the high-side and the
Logic control
low-side switches according to the truth table.
Undervoltage Shuts down the device for battery voltage lower than 4 V.
Protect the high-side and the low-side switches from the
High-side and low-side clamp voltage
high voltage on the battery line.
Drive the gate of the concerned switch to allow a proper
High-side and low-side driver
Ron for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
High-side and low-side overtemperature
temperature, it shuts down the concerned driver to prevent
protection
degradation and to protect the die.
Detects when low side current exceeds shutdown current
Low-side overload detector
and latches off the concerned Low side.

DocID029595 Rev 2 5/38

37
Block diagram and pin description VNH7070BAS

Table 2. Block description (continued)

Name Description

Signalizes the abnormal behavior of the switch through CS

Fault detection
pin.
Limits the power dissipation of the high-side driver inside
Power limitation
safe range in case of short to ground condition.

Figure 2. Configuration diagram (top view)

*1'$   *1'$
287$   287$
,1 $   6(/ 
9&&   &6
621
9&&   9&&
,1%   3:0
287%   287%
*1'%   *1'%

*$3*&)7

Table 3. Pin definitions and functions

Pin N° Symbol Function

1, 16 GNDA Source of low-side switch A

2, 15 OUTA Source of high-side switch A / drain of low-side switch A
3 INA Clockwise input
4, 5, 12 VCC Power supply voltage
6 INB Counter clockwise input
7, 10 OUTB Source of high-side switch B / drain of low-side switch B
8, 9 GNDB Source of low-side switch B
Voltage controlled input pin with hysteresis, CMOS compatible. Gates
11 PWM of low-side FETS get modulated by the PWM signal during their on
phase allowing speed control of the motor
Multiplexed analog sense output pin; it delivers a current proportional
13 CS
to the motor current according to the leg selection.
Active high compatible with 3 V and 5 V CMOS outputs pin; in
14 SEL0 combination with INA, INB, it addresses the CurrentSense information
delivered to the micro according to the operative truth table.

6/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

*4
**/"
*065" 7$$
*/" 7$$
**/# 065"
*065#
*/# 065#
*4&- *4&/4& 7065"
4&-















$4
*18. 7065#
18. 74&/4&
(/%

*(/%
7*/" 7*/# 74&- 718.

("1($'5

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Supply voltage 38 V

-VCC Reverse DC Supply Voltage 0.3 V
Imax Maximum output current (continuous) Internally limited A
IR Reverse output current (continuous) -15 A
Maximum transient supply voltage (ISO 16750-2:2010
VCCPK 40 V
Test B clamped to 40 V; RL = 4 )
Maximum jump start voltage for single pulse short circuit
VCCJS 28 V
protection
IIN Input current (INA and INB pins) -1 to 10 mA
ISEL0 SEL0 DC input current -1 to 10 mA
IPWM PWM input current -1 to 10 mA
CS pin DC output current (VGND = VCC and VSENSE < 0 V 10
ISENSE mA
CS pin DC output current in reverse (VCC < 0 V) -20

DocID029595 Rev 2 7/38

37
Electrical specifications VNH7070BAS

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge
(Human body model: R = 1.5 k; C = 100 pF)
– INA, INB, PWM 2
VESD – SEL0 2 kV
– CS 2
– VCC 4
– Output 4
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tc Junction operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C

2.2 Thermal data

Table 5. Thermal data
Symbol Parameter Max. value Unit

HSD 31 °C/W
Rthj-pin Thermal resistance junction-pin
LSD 44 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(1) See Figure 24 °C/W
HSD 39.5 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2)
LSD 55 °C/W
1. Device mounted on two-layers 2s0p PCB.
2. Device mounted on four-layers 2s2p PCB.

8/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C, unless
otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply
VCC 4 28 V
voltage
Off-state - standby; INA = INB = 0;
SEL0 = 0; PWM = 0; Tj = 25 °C; 1 μA
VCC = 13 V
Off-state - standby; INA = INB = 0;
SEL0 = 0; PWM = 0; VCC = 13 V; 1 μA
Tj = 85 °C
Off-state - standby; INA = INB = 0;
IS Supply current SEL0 = 0; PWM = 0; VCC = 13 V; 3 μA
Tj = 125 °C
Off-state (no standby);
INA = INB = 0; SEL0 = 5 V; 2 4 mA
PWM = 0
On-state: INA or INB = 5 V;
PWM = 0 V or PWM=5 V; 3.5 6 mA
SEL0 = X
VCC =13 V;
Standby mode blanking
tD_sdby(1) INA = INB= PMW = 0 V; 0.2 1 1.8 ms
time
VSEL0 from 5 V to 0 V

Static high-side IOUT = 3.5 A; Tj = 25°C 42 m

RONHS
resistance IOUT = 3.5 A; Tj = -40 to 150°C 85 m

Static low-side IOUT = 3.5 A; Tj = 25°C 30 m

RONLS
resistance IOUT = 3.5 A; Tj = -40°C to 150°C 60 m
Free-wheeling diode
Vf IOUT = -3.5 A; Tj = 150°C 0.7 0.9 V
forward voltage
INA = INB = 0; PWM = 0;
0 0.5 μA
Off-state output current VCC = 13 V; Tj = 25 °C
IL(off)
of one leg INA = INB = 0; PWM = 0;
0 3 μA
VCC = 13 V; Tj = 125 °C
Off-state output current
INA = 0; INB = 5 V; PWM = 0;
IL(off_h) of one leg with other 20 60 μA
VCC = 13 V
HSD on
1. To power on the device from the standby, it is recommended to:
— toggle INA or INB or SEL0 from 0 to 1 first to come out from STBY mode
— toggle PWM from 0 to 1 with a delay of 20 μs
this avoids any over-stress on the device in case of existing short-to-battery.

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37
Electrical specifications VNH7070BAS

Table 7. Logic inputs (INA, INB) (VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

VIH Input high level voltage 2.1 V
VIHYST Input hysteresis voltage 0.2 V
IIN = 1 mA 5.3 7.2 V
VICL Input clamp voltage
IIN = -1 mA -0.7 V
IINL Input current VIN = 0.9 V 1 μA
IINH Input current VIN = 2.1 V 10 μA

SEL0 (VCC = 7 V up to 18 V; -40°C < Tj < 150°C)

VSELL Input low level voltage 0.9 V

ISELL Low level input current VSEL = 0.9 V 1 μA
VSELH Input high level voltage 2.1 V
ISELH High level input current VSEL = 2.1 V 10 μA
VSEL(hyst) Input hysteresis voltage 0.2 V
ISEL = 1 mA 5.3 7.5 V
VSELCL Input clamp voltage
ISEL = -1 mA -0.7 V

PWM (VCC= 7 V up to 28 V; -40°C < Tj < 150°C)

VPWM Input low level voltage 0.9 V

IPWM Low level input current VPMW = 0.9 V 1 μA
VPWM Input high level voltage 2.1 V
IPWMH High level input current VPMW = 2.1 V 10 μA
VPWM(hyst) Input hysteresis voltage 0.2 V
IPMW = 1 mA 5.3 7.2 V
VPMWCL Input clamp voltage
IPMW = -1 mA -0.7 V

Table 8. Switching (VCC = 13 V, RLOAD = 3.7 Ω)

Symbol Parameter Test conditions Min. Typ. Max. Unit

f(1) PWM frequency 0 20 kHz

Input rise time < 1μs
td(on) Turn-on delay time 25 μs
(see Figure 6)
Input rise time < 1μs
td(off) Turn-off delay time 15 μs
(see Figure 6)
tr Rise time See Figure 5 0.7 1.5 μs
tf Fall time See Figure 5 0.2 0.5 μs
Low-side turn-on delay Input rise time < 1 μs (see
tcross 40 140 350 μs
time Figure 7)
1. Parameter guaranteed by design and characterization; not subjected to production test.

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VNH7070BAS Electrical specifications

Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VUSD Undervoltage shutdown 4 V

Undervoltage shutdown
VUSDreset 5 V
reset
Undervolatge shutdown
VUSDHyst 0.4 V
Hysteresis
High-side current
ILIM_H 15 22 30 A
limitation
ISD_LS Shutdown LS current 18 27 36 A
Time to shutdown for the INA = 5 V; INB = 0 V;
tSD_LS 5 μs
low-side PWM = 5 V (see Figure 8)
High-side clamp voltage
VCL_HSD (VCC to OUTA = 0 or IOUT = 100 mA; tclamp = 1 ms 38 46 V
OUTB = 0)
Low-side clamp voltage
VCL_LSD (OUTA = VCC or IOUT = 100 mA; tclamp = 1 ms 38 46 V
OUTB = VCC to GND)
High-side thermal
TTSD_HS INx = 2.1 V 150 175 200 °C
shutdown temperature
High-side thermal reset
TTR_HS 135 °C
temperature
High-side thermal
THYST_HS hysteresis (TSD_HS - T 7 °C
R_HS)

Low-side thermal
TTSD_LS INx = 0 V 150 175 200 °C
shutdown temperature
Total clamp voltage
VCL IOUT = 100 mA; tclamp = 1 ms 38 46 52 V
(VCC to GND)
INA = INB = 0 V; PWM = 0;
OFF-state open-load
VSEL0 = 5 V for CHA;
VOL voltage detection 2 3 4 V
VSEL0 = 0 V and within
threshold
td_stby for CHB
INA = INB = 0; VOUT = VOL;
PWM = 0 V;
OFF-state output sink
IL(off2) VSEL0 = 5 V for CHA; -100 -15 μA
current
VSEL0 = 0 V and within
td_stby for CHB
OFF-state diagnostic
INA = 5 V to 0 V; INB = 0;
delay time from falling
tDSTKON VSEL0 = 5 V; PWM = 0; 40 140 350 μs
edge of INPUT (see
IOUT = 0 A; VOUTA = 4 V
Figure 4)

DocID029595 Rev 2 11/38

37
Electrical specifications VNH7070BAS

Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit

INA = INB = 0 V; PWM = 0;

OFF-state diagnostic
VOUTx = 0 V to 4 V;
delay time from rising
tD_VOL VSEL0 = 5 V for CHA; 5 30 μs
edge of VOUT (see
VSEL0 = 0 V and within
Figure 11)
td_stby for CHB
Input reset time for high
VINx = 5 V to 0 V; HSDx
tLATCH_RST_HS(1) side fault unlatch (see 3 10 20 μs
faulting
Figure 9)
Input reset time for low
VINx = 0 V to 5 V; LSDx
tLATCH_RST_LS(1) side fault unlatch (see 3 10 20 μs
faulting
Figure 10)
1. Parameter guaranteed by design and characterization; not subjected to production test.

Table 10. CS (7 V < VCC < 18 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Multisense clamp VCC = 18 V; ISENSE = -5 mA 11

VSENSE_CL
voltage VCC = 18 V; ISENSE = 5 mA -13 -9 V
IOUT = 0.05 A; VSENSE = 0.5 V;
K0 IOUT/ISENSE 665
Tj = -40°C to 150°C
IOUT = 0.2 A; VSENSE = 0.5 V;
K1 IOUT/ISENSE 1083 1900 2716
Tj = -40°C to 150°C
IOUT = 3.5 A; VSENSE = 4 V;
K2 IOUT/ISENSE 1315 1540 1779
Tj = -40°C to 150°C
IOUT = 5.5 A; VSENSE = 4 V;
K3 IOUT/ISENSE 1357 1540 1727
Tj = -40°C to 150°C
Analog sense IOUT = 0.05 A; VSENSE = 0.5 V;
dK0/K0(1)(2) -25 25 %
current drift Tj = -40°C to 150°C
Analog sense IOUT = 0.2 A; VSENSE = 0.5 V;
dK1/K1(1)(2) -21 21 %
current drift Tj = -40°C to 150°C
Analog sense IOUT = 3.5 A; VSENSE = 4 V;
dK2/K2(1)(2) -5 5 %
current drift Tj = -40°C to 150°C
Analog sense IOUT = 5.5 A; VSENSE = 4 V;
dK3/K3(1)(2) -4 4 %
current drift Tj = -40°C to 150°C
VCC = 7; RSENSE = 10 kΩ;
Max analog sense VSEL0 = 5 V; IOUTA = 5.5 A;
VSENSESAT 5 V
output voltage VINA = 5 V; PWM = 0;
Tj = 150°C
VCC = 13 V; VINA = 5 V;
CurrentSense
ISENSE_SAT(2) VINB = 0 V; VSENSE = 4 V; 4.6 mA
saturation current
VSEL0 = 5 V; Tj = 150°C
VCC = 13 V; VSENSE = 4 V;
Output saturation
IOUT_SAT(2) VINA = 5 V; VINB = 0 V; 8 A
current
VSEL0 = 5 V; Tj = 150°C

12/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

Table 10. CS (7 V < VCC < 18 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Output Voltage for VINA = 5 V; VINB = 0 V;

VOUT_MSD(2) MultiSense VSEL0 = 5 V; RSENSE = 2.7 kΩ; 5 V
shutdown IOUT = 3.5 A
IOUT = 0 A; VSENSE = 0 V;
INx = 0 V; SEL0 = 0; 0 0.5 μA
Tj = -40°C to 150°C (Standby)
IOUT = 0 A; VSENSE = 0 V;
ISENSE0 CS leakage current INx = 0 V; SEL0 = 5 V;
0 0.5 μA
Tj = -40°C to 150°C
(No Standby)
INx = 5 V; PWM = 5 V;
0 5 μA
IOUT = 0 A; Tj = -40°C to 150°C
VCC = 13 V; RSENSE = 1 kΩ;
CS output voltage in – E.g: OutA in open-load:
VSENSEH 5 7 V
fault condition VINA = 0 V; IOUTA = 0 A;
VOUTA = 4 V; VSEL0 = 5 V
CS output current in 9 V < VCC < 18 V;
ISENSEH 10 20 30 mA
fault condition VSENSE = VSENSEH
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and 9 V < VCC <
18 V) with respect to its value measured at Tj = 25 °C, VCC = 13 V.
2. Parameter guaranteed by design and characterization; not subjected to production test.

Figure 4. TDSTKON
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DocID029595 Rev 2 13/38

37
Electrical specifications VNH7070BAS

Figure 5. Definition of the low-side switching times

PWM

VOUTA, B
90% 80%

tf tr t
20% 10%

Figure 6. Definition of the high-side switching times

VINA tD(on) tD(off)

t
VOUTA

90%

10%

14/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

Figure 7. Low-side turn-on delay time

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Figure 8. Time to shutdown for the low-side driver

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DocID029595 Rev 2 15/38

37
Electrical specifications VNH7070BAS

Figure 9. Input reset time for HSD - fault unlatch

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Figure 10. Input reset time for LSD - fault unlatch

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16/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL)

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DocID029595 Rev 2 17/38

37
Electrical specifications VNH7070BAS

Table 11. Operative condition - truth table

Pin status HSDs and LDSs status

INA INB SEL0 PWM CS HSDA LSDA HSDB LSDB

1 Current Monitoring HSDA

1 1 x On Off On Off
0 Current Monitoring HSDB
1 On Off Off On
1 0 1 Current Monitoring HSDA
0 On Off Off Off
1 On Off Off On
1 0 0 Hi-Z
0 On Off Off Off
1 Off On On Off
0 1 1 Hi-Z
0 Off Off On Off
1 Off On On Off
0 1 0 Current Monitoring HSDB
0 Off Off On Off
1
0 0 1 Hi-Z Off On Off On
0
1 Off Off Off Off
0 0 0 x(1)
(2)
0 Off Off Off Off
1. Refer to Table 13: Off-state -truth table
2. For INA = INB = SEL0 = PWM = 0, the device enters in standby after TD_sdby

Table 12. On-state fault conditions- truth table

Digital Input pins
CS Comment
INA INB PWM SEL0

0 0 1 0 VsenseH LSB protection triggered; LSB latched off

0 0 1 1 VsenseH LSA protection triggered; LSA latched off
0 1 X 0 VsenseH HSB protection triggered; HSB latched off
0 1 1 1 VsenseH LSA protection triggered; LSA latched off
1 0 1 0 VsenseH LSB protection triggered; LSB latched off
1 0 X 1 VsenseH HSA protection triggered; HSA latched off
1 1 X 0 VsenseH HSB protection triggered; HSB latched off
1 1 X 1 VsenseH HSA protection triggered; HSA latched off

Note: Other logic combinations on digital input pins not reported on the above table don’t allow to
detect a latched off channel.

18/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

Table 13. Off-state -truth table

INA INB SEL0 PWM OutA OutB CS Description

Off-state diagnostic

Case 1. OutA shorted to VCC if no

pull-up is applied
Case 2. No open-load in full bridge
configuration with an external
VoutA>VOL x VSENSEH pull-up on OutB
Case 3. open-load in half bridge
configuration with an external
pull-up on OutA(motor connected
1 between OutA and Ground)
Case 1. Open-load in full Bridge
configuration with an external
pull-up on OutB
VoutA<VOL x Hi-Z Case 2. No open-load in half Bridge
configuration with external pull-up
on OutA (motor connected between
OutA and Ground)
0 0 0
Case 1. OutB shorted to VCC if no
pull-up is applied
Case 2. No open-load in full bridge
configuration with external pull-up
X VoutB>VOL VSENSEH on Out
A
Case 3. Open-load in half bridge
configuration with external pull-up
0(1)(2) on OutB (motor connected between
OutB and Ground)
Case1. Open-load in full Bridge
configuration with an external
pull-up on OutA
X VoutB<VOL Hi-Z Case 2. No open-load in half Bridge
configuration with external pull-up
on OutB (motor connected between
OutB and Ground)
1. The device enters standby mode after TD_sdby.
2. To power on the device from the standby, it is recommended to toggle INA or INB from 0 to 1 first and then
PWM from 0 to 1 to avoid any over-stress on the device in case of short-to-battery.

DocID029595 Rev 2 19/38

37
Electrical specifications VNH7070BAS

2.4 Waveforms
Figure 12. Normal operative conditions
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Figure 13. OUT shorted to ground and short clearing

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20/38 DocID029595 Rev 2

VNH7070BAS Electrical specifications

Figure 14. OUT shorted to Vcc and short clearing

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DocID029595 Rev 2 21/38

37
Application information VNH7070BAS

3 Application information

Here following there is the typical application schematic suggested for a proper operation of
the device in DC or PWM conditions.

Figure 15. Application schematic with reverse battery protection connected to Vbatt
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22/38 DocID029595 Rev 2

VNH7070BAS Application information

Figure 17. Suggested PCB layout

Note: PCB layout recommendation:

Optimized connection (short) between Drain LSD and Source HSD
Optimized GNDa and GNDb connection (symmetric connection)

3.1 Reverse battery protection

Three possible solutions can be considered:
 A Schottky diode D connected to VCC pin
 An N-channel MOSFET connected to the GND pin
 A P-channel MOSFET connected to the VCC pin
In case the reverse battery protection is not present, the device sustains no more than -15 A
because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery
condition the I/Os of the device is pulled down to the VCC line (approximately -1.5 V).
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is:

V IOs – V CC
R = ------------------------------
I Rmax

3.2 OFF-state open-load detection – External circuitry

dimensioning
The detection of an open-load in off state requires an external circuitry to be connected
between Output and VBATT.
For the detection it is necessary to put one network on each leg in case of Half Bridge
operation or one network on one of the output in case of full bridge (see Table 13: Off-state
-truth table).
The external circuitry is made up by an external pull-up resistor Rpull_up connecting the
output to a positive supply voltage VPU (VBatt).

DocID029595 Rev 2 23/38

37
Application information VNH7070BAS

It is preferable to switch-off VPU by using an external pull_up switch to reduce the overall
standby current during he module standby mode.
Rpull_up must be dimensioned to ensure that in normal operative conditions VOUT > VOLmax.
To satisfy this condition the Rpull_up must be selected according to:
 if the device is used in half bridge configuration, the equation is:

V BATTmin – V OLmax
R pull_up  -------------------------------------------------------
-
I L(off2)min[@VOLmax]
 if the device is used in H-bridge configuration, the equation is:

V BATTmin – V OLmax
R pull_up  -------------------------------------------------------------
-
2  I L(off2)min[@VOLmax]

3.3 Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 14.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.

Table 14. ISO 7637-2 - electrical transient conduction along supply line
Test pulse severity
Test
level with Status II Minimum Burst cycle / pulse
Pulse Pulse duration and
functional performance number of repetition time
2011(E) pulse generator
status pulses or test
internal impedance
time
Level US(1) min max

1 III -112 V 500 pulses 0,5 s 2ms, 10 

2a III +55 V 500 pulses 0,2 s 5s 50μs, 2 
3a IV -220 V 1h 90 ms 100 ms 0.1μs, 50 
3b IV +150 V 1h 90 ms 100 ms 0.1μs, 50 
(2)
4 IV -7 V 1 pulse 100ms, 0.0 1

Load dump according to ISO 16750-2:2010

Test B(3) 40 V 5 pulse 1 min 400 ms, 2 

1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

24/38 DocID029595 Rev 2

VNH7070BAS Application information

2. Test pulse from ISO 7637-2:2004(E).

3. With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).

3.4 Device configurations

Figure 18. Half-bridge configuration (case a)

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Note: The VNH7070BAS can be used in half bridge configuration as the two legs can be
independently driven. The SEL0 pin can be used to address the diagnostic on the CS
according to the operative truth table.

Figure 19. Half-bridge configuration (case b)

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Note: The VNH7070BAS can be used in applications where an half-bridge with a resistance of
50 mΩ per leg is needed.

DocID029595 Rev 2 25/38

37
Application information VNH7070BAS

Figure 20. Multi-motors configuration

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Note: The VNH7070BAS can easily be designed in multi motor driving configuration in the
applications where only one motor at a time must be activated. The SEL0 pin can be used to
read the diagnostic on the CS according to the operative truth table.

26/38 DocID029595 Rev 2

VNH7070BAS Package and PCB thermal data

4 Package and PCB thermal data

4.1 SO16-N thermal data

Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2

DocID029595 Rev 2 27/38

37
Package and PCB thermal data VNH7070BAS

Figure 22. PCB 4 layer

Note: Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board
dimension 77x86 mm; Board Material FR4; Cu thickness 0.070mm (outer layers); Cu
thickness 0.035mm (inner layers); Thermal vias separation 1.2 mm; Thermal via diameter
0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm.

4.2 Package thermal data

4.2.1 Thermal characterization in steady state conditions

Figure 23. Chipset configuration in steady state conditions

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28/38 DocID029595 Rev 2

VNH7070BAS Package and PCB thermal data

Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air
condition


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Table 15. Thermal model for junction temperature calculation in steady-state

conditions
Chip 1 Chip 2 Chip 3 Tjchip1 Tjchip2 Tjchip3

Pdchip1 • RthA + Pdchip3 Pdchip1 • RthAB + Pdchip3 Pdchip1 • RthAC + Pdchip3

ON OFF ON
• RthAC + Tamb • RthBC + Tamb • RthC + Tamb
Pdchip1 • RthA + Pdchip2 Pdchip1 • RthAB + Pdchip2 Pdchip1 • RthAC + Pdchip2
ON ON OFF
• RthAB + Tamb • RthB + Tamb • RthBC + Tamb
ON OFF OFF Pdchip1 • RthA+ Tamb Pdchip1 • RthAB + Tamb Pdchip1 • RthAC + Tamb
Pdchip1 • RthA + (Pdchip2 Pdchip2 • RthB + Pdchip1 • Pdchip1 • RthAB + Pdchip2
ON ON ON + Pdchip3) • RthAB + T RthAB + Pdchip3 • RthBC • RthBC + Pdchip3 • RthC
amb + Tamb + Tamb

4.2.2 Thermal characterization during transients

Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zlsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zlsls + Tamb

DocID029595 Rev 2 29/38

37
Package and PCB thermal data VNH7070BAS

Figure 25. HSD thermal impedance junction ambient single pulse

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Figure 26. LSD thermal impedance junction ambient single pulse

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30/38 DocID029595 Rev 2

VNH7070BAS Package and PCB thermal data

Figure 27. Electrical equivalent model

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Table 16. Thermal parameters

Area/island 2Layer PCB
2) 4Layer PCB
(cm FP 2 8

R1 (°C/W) 2.4 2.4 2.4 2.4

R2 (°C/W) 12 12 12 12
R3 (°C/W) 30 25 25 30
R4 (°C/W) 42 12 12 5
R5 (°C/W) 85 45 30 17
R6 (°C/W) 2.4 2.4 2.4 2.4
R7 (°C/W) 4 4 4 4
R8 (°C/W) 12 12 12 12
R9 (°C/W) 30 30 30 42
R10 (°C/W) 68 52 48 10
R11 (°C/W) 75 80 60 26
R12 (°C/W) 4 4 4 4
R13 (°C/W) 12 12 12 12
R14 (°C/W) 30 30 30 42
R15 (°C/W) 68 52 48 10
R16 (°C/W) 75 80 60 26
R17 (°C/W) 120 100 100 100
R18 (°C/W) 120 100 100 100
R19 (°C/W) 180 170 170 170
R20 (°C/W) 180 170 170 170

DocID029595 Rev 2 31/38

37
Package and PCB thermal data VNH7070BAS

Table 16. Thermal parameters (continued)

Area/island 2Layer PCB
4Layer PCB
(cm2) FP 2 8

C1 (W·s/°C) 0.0008 0.0008 0.0008 0.0008

C2 (W·s/°C) 0.01 0.01 0.01 0.01
C3 (W·s/°C) 0.08 0.1 0.1 0.1
C4 (W·s/°C) 0.2 0.5 1 1
C5 (W·s/°C) 1.5 2 6 12
C6 (W·s/°C) 0.0008 0.0008 0.0008 0.0008
C7 (W·s/°C) 0.001 0.001 0.001 0.001
C8 (W·s/°C) 0.012 0.012 0.012 0.012
C9 (W·s/°C) 0.05 0.05 0.05 0.05
C10 (W·s/°C) 0.08 0.1 0.2 0.5
C11 (W·s/°C) 1 2.5 3 6
C12 (W·s/°C) 0.001 0.001 0.001 0.001
C13 (W·s/°C) 0.012 0.012 0.012 0.012
C14 (W·s/°C) 0.05 0.05 0.05 0.05
C15 (W·s/°C) 0.08 0.1 0.2 0.5
C16 (W·s/°C) 1 2.5 3 6

32/38 DocID029595 Rev 2

VNH7070BAS Package and packing information

5 Package and packing information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.1 SO-16N mechanical data

Figure 28. SO-16N package dimensions

("1($'5

DocID029595 Rev 2 33/38

37
Package and packing information VNH7070BAS

Table 17. SO-16N mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.75

A1 0.10 0.25

A2 1.25

b 0.31 0.51

c 0.17 0.25

D 9.80 9.90 10.00

E 5.80 6.00 6.20

E1 3.80 3.90 4.00

e 1.27

h 0.25 0.50

L 0.40 1.27

k 0° 8°

ccc 0.1

5.2 SO-16N packing information

Figure 29. SO-16N reel 13”

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34/38 DocID029595 Rev 2

VNH7070BAS Package and packing information

Table 18. Reel dimensions

Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2 /-0) 16.4
W2 (max) 22.4
1. All dimensions are in mm.

Figure 30. SO-16N rcarrier tape

("1($'5

Table 19. SO-16N carrier tape dimensions

Description Value
A0 6.55 ± 0.1
B0 10.38 ± 0.1
K0 2.10 ± 0.1
K1 1.80 ± 0.1
F 7.50 ± 0.1

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Package and packing information VNH7070BAS

Table 19. SO-16N carrier tape dimensions (continued)

Description Value
P1 8.00 ± 0.1
W 16.00 ± 0.3

Figure 31. SO-16N schematic drawing of leader and trailer tape

5.3 SO-16N marking information

Figure 32. SO-16N marking information

.BSLJOH
BSFB

           

4QFDJBM
GVODUJPO
EJHJU
&4
&OHJOFFSJOH
TBNQMF
CMBOL
$PNNFSDJBM
TBNQMF

40/
501
7*&8

OPU
JO
TDBMF
("1($'5

Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run
a qualification activity.

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VNH7070BAS Revision history

6 Revision history

Table 20. Document revision history

Date Revision Changes

23-Aug-2016 1 Initial release.

Document status promoted from target specification to production data.
Updated:
– VCCmax value in cover page;
– Added as first feature “AEC-Q100 qualified“ in cover page;
24-Mar-2017 2 – Note 1 of the Table 6: Power section on page 9;
– Table 10: CS (7 V < VCC < 18 V) on page 12, ISENSEH parameter;
– Table 12: On-state fault conditions- truth table on page 18;
– Figure 25, Figure 26 and Figure 27;
– Table 16: Thermal parameters on page 31.

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 VNH7070BAS

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