Multi-Band RF Frequency Synthesizer With Integrated Vcos: Features
Multi-Band RF Frequency Synthesizer With Integrated Vcos: Features
Multi-Band RF Frequency Synthesizer With Integrated Vcos: Features
Features
■ Integer-N frequency synthesizer
■ Dual differential integrated VCOs with
automatic center frequency calibration:
– 3000 - 3620 MHz (direct output)
– 4000 - 4650 MHz (direct output)
– 1500 - 1810 MHz (internal divider by 2)
– 2000 - 2325 MHz (internal divider by 2)
– 750 - 905 MHz (internal divider by 4)
– 1000 - 1162.5 MHz (internal divider by 4)
Applications
■ Excellent integrated phase noise ■ 2.5G and 3G cellular infrastructure equipment
■ Fast lock time: 150 µs ■ CATV equipment
■ Dual modulus programmable prescaler (16/17 ■ Instrumentation and test equipment
or 19/20) ■ Other wireless communication systems
■ 2 programmable counters to achieve a
feedback division ratio from 256 to 65551 Description
(prescaler 16/17) and from 361 to 77836
(prescaler 19/20). The STMicroelectronics STW81102 is an
integrated RF synthesizer with voltage controlled
■ Programmable reference frequency divider (10
oscillators (VCOs). Showing high performance,
bits)
high integration, low power, and multi-band
■ Phase frequency comparator and charge pump performances, the STW81102 is a low-cost one-
■ Programmable charge pump current chip alternative to discrete PLL and VCOs
solutions.
■ Digital lock detector
■ Dual digital bus Interface: SPI and I2C bus with The STW81102 includes an Integer-N frequency
3 bit programmable address (1100A2A1A0) synthesizer and two fully integrated VCOs
featuring low phase noise performance and a
■ 3.3V power supply noise floor of -155 dBc/Hz.
■ Power down mode (HW and SW)
The combination of wide frequency range VCOs
■ Small size exposed pad VFQFPN28 package (using center-frequency calibration over 32 sub-
5x5x1.0mm bands) and multiple output options (direct output,
■ Process: BICMOS 0.35 µm SiGe divided by 2 or divided by 4) allows coverage from
750 MHz to 905 MHz and 1000MHz to 1162.5
MHz, from 1500MHz to 1810 MHz and 2000 MHz
to 2325MHz, from 3000 MHz to 3620 MHz and
4000MHz to 4650 MHz bands.
The STW81102 is designed with
STMicroelectronics advanced 0.35µm SiGe
process.
Contents
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.1 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.2 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.3 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.1 Output Buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 External VCO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/53
STW81102 Contents
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.4 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
List of tables STW81102
List of tables
4/53
STW81102 List of figures
List of figures
5/53
Block diagram and pin configuration STW81102
OUTBUFN
OUTBUFP
REF_CLK
VDD_PLL
VSS_PLL
REXT
VDD_OUTBUF
VSS_OUTBUF
BUF
VDD_DIV4
BUF
VCO
DIV4
DIV2
BUF
BUF
VSS_DIV4
VDD_DIV2 VSS_CP
REF VDD_CP
VSS_DIV2
DIV4
DIV2
Divider
P UP
C
VDD_BUFVCO F
P
ICP
VCO DN
VSS_BUFVCO D
BUF
Divider
LOCK_DET
EXTVCO_INP EXT
VCO
EXTVCO_INN BUF DBUS_SEL
SCL / CLK
DBUS SDA / DATA
ADD0 / LOAD
VCO ADD1
VDD_VCOA BUFF ADD2
VSS_VCOA VCO
VDD_VCOB Calibrator
VSS_VCOB VDD_DBUS
VSS_DBUS
VDD_ESD
VSS_ESD
VCTRL
TEST1
TEST2
EXT_PD
6/53
STW81102 Block diagram and pin configuration
ADD0/LOAD
VDD_DBUS
SDA/DATA
SCL/CLK
EXT_PD
ADD2
ADD1
VDD_VCOA DBUS_SEL
VDD_DIV2 VDD_BUFVCO
VDD_OUTBUF EXTVCO_INP
OUTBUFP
VFQFPN28 EXTVCO_INN
QFN 28
OUTBUFN VDD_PLL
VDD_DIV4 REF_CLK
VDD_CP
VCTRL
TEST1
REXT
ICP
7/53
Block diagram and pin configuration STW81102
8/53
STW81102 Electrical specifications
2 Electrical specifications
9/53
Electrical specifications STW81102
10/53
STW81102 Electrical specifications
11/53
Electrical specifications STW81102
External VCO
Frequency range 0.625 5 GHz
Input level -10 +6 dBm
Current consumption VCO internal buffer 28 mA
PLL miscellaneous
Input buffer, prescaler, digital
IPLL Current consumption 12 mA
dividers, misc.
25kHz PLL bandwidth; within
tlock Lock up time (5), (7) 150 µs
1 ppm of frequency error
1. In order to achieve best phase noise performance 1V peak level is suggested.
2. The frequency step is related to the PFD input frequency as follows:
- FSTEP = FPFD for direct output
- FSTEP = FPFD/2 for divided by 2 output
- FSTEP = FPFD/4 for divided by 4 output
3. See relationship between ICP and REXT in Section 5.7: Charge pump.
4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop
BW.
5. Guaranteed by design and characterization.
6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range
for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating
temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in
either direction) is within the limit specified by ΔTLK, provided that the final temperature T1 is still inside the nominal range.
If higher ΔT are required the ”VCO calibration auto-restart“ feature can be enabled, thus allowing to re-start the VCO
calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal)
7. Frequency jump from 2300 to 2150 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with
FPFD=400kHz).
12/53
STW81102 Electrical specifications
13/53
Electrical specifications STW81102
14/53
STW81102 Typical performance characteristics
Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop
measurements are done with FSTEP=200 kHz, with the FPFD and charge pump current
properly set. The loop filter configuration is depicted in Figure 36: Typical application
diagram, and the reference clock signal is at 76.8 MHz with phase noise of -135 dBc/Hz at
1kHz offset, -145 dBc/Hz at10 kHz offset and -149.5 dBc/Hz of noise floor.
Figure 3. VCO A (direct output) open loop Figure 4. VCO B (direct output) open loop
phase noise phase noise
Figure 5. VCO A (direct output) closed loop Figure 6. VCO B (direct output) closed loop
phase noise at 3.6GHz phase noise at 4.3GHz
(FSTEP=200kHz; FPFD=200kHz; (FSTEP=200kHz; FPFD=200kHz;
ICP=3mA) ICP=4mA)
15/53
Typical performance characteristics STW81102
Figure 7. VCO A (div. by 2 output) closed Figure 8. VCO B (div. by 2 output) closed
loop phase noise at 1.65GHz loop phase noise at 2.15GHz
(FSTEP=200kHz; FPFD=400kHz; (FSTEP=200kHz; FPFD=400kHz;
ICP=2mA) ICP=3mA)
Figure 9. VCO A (div. by 4 output) closed Figure 10. VCO B (div. by 4 output) closed
loop phase noise at 825MHz loop phase noise at 1.075GHz
(FSTEP=200kHz; FPFD=800kHz; (FSTEP=200kHz; FPFD=800kHz;
ICP=1.5mA) ICP=2.5mA)
0.24° rms
0.2 ° rms
16/53
STW81102 Typical performance characteristics
Figure 11. PFD frequency spurs (direct Figure 12. PFD frequency spurs (div. by 2
output; FPFD=200kHz) output; FPFD=400kHz)
Figure 13. PFD frequency spurs (div. by 4 Figure 14. Settling time (final frequency=2.15
output; FPFD=800kHz) GHz; FPFD=400kHz; ICP=3mA)
-91 dBc
@800KHz
17/53
General description STW81102
4 General description
Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N
PLL frequency synthesizer.
The STW81102 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a
divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit
programmable reference divider, two programmable counters and a programmable dual-
modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual-
modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P
+A. The division ratio of both reference and VCO dividers is controlled through the selected
digital interface (I2C bus or SPI).
The digital interface type is selected by the proper hardware connection of the pin
DBUS_SEL (0 V for I2C bus, 3.3 V for SPI).
All devices operate with a power supply of 3.3 V and can be powered down when not in use.
18/53
STW81102 Circuit description
5 Circuit description
F
ref
INV BUF
Power Down
5.3 Prescaler
The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it
down to a manageable frequency for the CMOS A and B counters. The modulus P is
programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5
core whose division ratio depends on the state of the modulus input.
19/53
Circuit description STW81102
( B × P + A ) × Fref
F = ---------------------------------------------------
VCO R
where:
FVCO: output frequency of VCO
P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)
B: division ratio of the main counter
A: division ratio of the swallow counter
Fref: input reference frequency
R: division ratio of reference counter
N: division ratio of PLL
For a correct working of the VCO divider, B must be strictly higher than A. A can take any
value ranging from 0 to 31. The range of N can vary from 256 to 65551 (P=16) or from 361
to 77836 (P=19).
16/17 or 19/20
VCOBUF+
To PFD
modulus
5-bit 12-bit
A-counter B-counter
20/53
STW81102 Circuit description
VDD
D FF Up
Fref
R
Delay
R
Fref
VDD D FF
Down
ABL
21/53
Circuit description STW81102
0 0 0 IMIN 0.5 mA
0 0 1 2*IMIN 1.0 mA
0 1 0 3*IMIN 1.5 mA
0 1 1 4*IMIN 2.0 mA
1 0 0 5*IMIN 2.5 mA
1 0 1 6*IMIN 3.0 mA
1 1 0 7*IMIN 3.5 mA
1 1 1 8*IMIN 4.0 mA
Note: The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are
forced to VDD/2
VDD
VCTRL
BUF C3 R3
Charge
Pump ICP
R1
C2
C1
BUF
Cal bit
22/53
STW81102 Circuit description
23/53
Circuit description STW81102
The SERCAL bit should be set to 1 at each division ratio change. VCO calibration procedure
takes approximately 7 periods of the PFD frequency.
The maximum allowed FPFD to perform the calibration process is 1 MHz. When using a
higher FPFD, follow the steps below:
1. Calibrate the VCO at the desired frequency with an FPFD less than 1 MHz.
2. Set the A, B and R divider ratios for the desired FPFD.
00 1.1 16 -125
01 1.3 18 -126
10 1.9 27 -128.5
11 2.1 30 -129
24/53
STW81102 Circuit description
00 1.1 11 -124
01 1.3 14 -125
10 1.9 20 -127.5
11 2.1 22 -128
EXT_PD = 0V Î Device ON
0 Device hardware power down
EXT_PD = 3.3V Î Device OFF
EXT_PD = 0V Î Output Stage ON
1 Output Buffer control
EXT_PD = 3.3V Î Output Stage OFF
25/53
Circuit description STW81102
26/53
STW81102 I2C bus interface
The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V.
Data is transmitted from microprocessor to the STW81102 through the 2-wire (SDA and
SCL) I2C bus interface. The STW81102 is always a slave device.
The I2C bus protocol defines any device that sends data on the bus as a transmitter, and
any device that reads the data as a receiver. The device controlling the data transfer is the
master, and the others are slaves. The master always initiates the transfer and provides the
serial clock for synchronization.
SDA
SCL
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the
clock signal SCL is stable in the high state. A STOP condition terminates communications
between the STW81102 and the bus master.
27/53
I2C bus interface STW81102
SCL
SDA
START STOP
SCL 1 2 3 7 8 9
//
SDA MSB
//
START Acknowledgement
from receiver
28/53
STW81102 I2C bus interface
29/53
I2C bus interface STW81102
SDA
SCL
t
cwl
t t t
cs ch cwh
SDA
SCL
t t
start stop
30/53
STW81102 I2C bus interface
SDA
8 9
SCL
t d1 t d2
PC
31/53
I2C bus interface STW81102
0x00 0 FUNCTIONAL_MODE
0x01 1 B_COUNTER
0x02 2 A_COUNTER
0x03 3 REF_DIVIDER
0x04 4 CONTROL
0x05 5 CALIBRATION
FUNCTIONAL_MODE
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
CAL_AUT
OUTBUF_
OSTART_ PD4 PD3 PD2 PD1 PD0 B11
CTRL_EN
EN
The bits PD[4:0] allow to select different functional modes for the STW81102 synthesizer
according to the Table 18.
32/53
STW81102 I2C bus interface
B_COUNTER
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
B10 B9 B8 B7 B6 B5 B4 B3
B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)
A_COUNTER
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
B2 B1 B0 A4 A3 A2 A1 A0
REF_DIVIDER
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
R9 R8 R7 R6 R5 R4 R3 R2
Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).
CONTROL
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
R1 R0 PLL_A1 PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL
The CONTROL register is used to set the charge pump current, the VCO output voltage
amplitude and the prescaler modulus:
PLL_A[1:0]: VCO amplitude
CPSEL[2:0]: charge pump output current
PSC_SEL: prescaler modulus select ('0' for P=16, '1' for P=19)
33/53
I2C bus interface STW81102
The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:
F REF – CLK
F OUT = D R × ( B × P + A ) × -------------------------------
R
1 for direct output
where DR equals
{ 0.5 for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
CALIBRATION
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0
This register controls the VCO calibrator using the following values:
INITCAL: for test purposes only; must be set to 0.
SERCAL: at 1, starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)
SELEXTCAL: for test purposes only; must be set to 0
CAL[4:0]: for test purposes only; must be set to 0
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
DEV_ID1 DEV_ID0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0
This register is automatically addressed in the 'current byte address read mode', using the
following values:
DEV_ID[1:0]: device identifier bits; returns 01
LOCK_DET: 1 when PLL is locked
INTCAL[4:0]: internal value of the VCO control word
34/53
STW81102 I2C bus interface
35/53
SPI digital interface STW81102
DATA
A1
LOAD
Address
decoder
D23 (MSB)
LOAD #4
D0 (LSB)
Reg.#0
Reg.#1
Reg.#4
36/53
STW81102 SPI digital interface
A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data bits
A1 A0 No Name Function
D23-D0
tclk_loadf
Clock
tdk
Load
t
clk_loadr tload
37/53
SPI digital interface STW81102
[23] R9
[22] R8
[21] R7
[20] R6
[19] R5
Reference clock divider ratio
[18] R4
[17] R3
[16] R2
[15] R1
[14] R0
[13] PLL_A1
VCO amplitude control
[12] PLL_A0
[11] CPSEL2
[10] CPSEL1 Charge pump output current control
[9] CPSEL0
[8] PSC_SEL Prescaler modulus select (0 for P=16, 1 for P=19)
[7] INITCAL For test purposes only; must be set to 0
[6] SERCAL Enable VCO calibration (see Section 7.4)
[5] SELEXTCAL For test purposes only; must be set to 0
[4] CAL4
[3] CAL3
[2] CAL2 For test purposes only; must be set to 0
[1] CAL1
[0] CAL0
38/53
STW81102 SPI digital interface
39/53
SPI digital interface STW81102
The LO output frequency is programmed by setting the proper values for A, B and R
according to the following formula:
F REF – CLK
F OUT = D R × ( B × P + A ) × -----------------------------------
R
1 for direct output
where DR equals
{ 0.5 for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
40/53
STW81102 Application information
8 Application information
The STW81102 features three different alternately selectable bands: direct output (3.0 to
3.62 GHz and 4.0 to 4.65 GHz), divided by 2 (1.5 to 1.81 GHz and 2.0 to 2.325 GHz) and
divided by 4 (750 to 905 MHz and 1000 to 1162.5 MHz). To achieve a suitable power level, a
good matching network is necessary to adapt the output stage to a 50 Ω load. Moreover,
since most commercial RF components have single-ended input and output terminations, a
differential to single-ended conversion may be required.
The different matching configurations shown below for each of the three bands are
suggested as a guideline when designing your own application board.
Inside the evaluation kit is the ADS design for each matching configuration suggested in this
chapter. The name of the corresponding ADS design is given in each figure.
The ADS designs provide only a first indication of the output stage matching, and should be
reworked according to the choices of layout, board substrate, components and so on.
The ADS designs of the evaluation boards are provided with a complete electromagnetic
modelling (board, components, and so on).
10pF
RF
OUTN
50 ohm
100 ohm 5.5nH
Vcc
Since most discrete components for microwave applications are single-ended, you can
easily use one of the two outputs and terminate the other one to 50 Ω with a 3 dB power
loss.
41/53
Application information STW81102
Alternatively, you can combine the two outputs in other ways. A first topology for the direct
output (3 GHz to 4.65 GHz) is suggested in Figure 29. It basically consists of a simple LC
balun and a matching network to adapt the output to a 50 Ω load. The two LC networks shift
output signal phase of -90° and +90°, thus combining the two outputs. This topology,
designed for a center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is
tuned at a single frequency. If the application requires a different sub-band, the LC combiner
can be easily tuned to the frequency of interest.
50 ohm 0.8pF
1.9nH 1.9nH
RF
OUTP
0.8pF 2.5pF
1.9nH 50 ohm
RF
OUTN
0.8pF
50 ohm 1.9nH 0.8pF
Vcc
The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well
as a matching element along with the other components. The 1.9 nH series inductors are
used to resonate the parasitic capacitance of the chip.
For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and
0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths
to minimize losses and undesired impedance shift.
An alternative topology that permits a more broadband matching as well as balanced to
unbalanced conversion, is shown in Figure 30.
42/53
STW81102 Application information
50 ohm 5.5nH
12pF
12pF 4.7pF
RF
OUTP
2:1
12pF 1pF 1pF 1.2pF 1.2pF 50 ohm
RF
OUTN
50 ohm 5.5nH
Vcc
50 ohm 22nH
50 ohm
10pF
RF
OUTP
10pF
RF
OUTN
50 ohm
50 ohm 22nH
Vcc
43/53
Application information STW81102
A first solution to combine the differential outputs is the lumped LC type balun tuned in the
2 GHz band (Figure 32).
50 ohm 2pF
2.7nH 2.7nH
RF
OUTP
2pF 3pF
2.7nH
50 ohm
3nH
RF
OUTN
2pF
50 ohm 2.7nH 2pF
Vcc
The same recommendation for the SMD components also applies to the divided by 2 output.
Another topology suited to combining the two outputs for the divided by 2 frequencies is
represented in Figure 33.
50 ohm 5.5nH
22pF
22pF 1.9nH
RF
OUTP
2:1
22pF 1.2pF 50 ohm
RF
OUTN
50 ohm 5.5nH
Vcc
44/53
STW81102 Application information
RF
OUTP
4pF 6pF
RF
OUTN
4pF
25 ohm 5.5nH 4pF
Vcc
If you prefer to use an RF balun, you can adapt the topology depicted in Figure 33, and
change the balun and the matching components (Figure 35). The suggested balun for the
0.75 - 1.17 GHz frequency range is the 1:1 Johanson 900BL15C050.
45/53
Application information STW81102
25 ohm 18nH
8.2pF
22pF 2.1nH
RF
OUTP
1:1
8.2pF 0.5pF 50 ohm
RF
OUTN
25 ohm 18nH
Vcc
The three evaluation kits differ only for the output stage network and can be adapted from
one frequency band variant to a different one replacing properly the matching components
and the balun.
46/53
STW81102 Application diagrams
9 Application diagrams
VDD1 I2C
VDD_DBUS
ADD0/LOAD
EXT_PD
SCL/CLK
ADD2
ADD1
SDA/DATA
1n 22p 10P
VDD_VCOA DBUS_SEL SPI
VDD_DIV2 VDD_BUFVCO
VDD1 VDD2
VDD_OUTBUF EXTVCO_INP
OUTBUFP
STW81103
STW81102 EXTVCO_INN
OUTBUFN VDD_PLL
ref clk
VDD_DIV4 REF_CLK
VDD1
LOCK_DET
1.8n 51
VDD_VCOB TEST2
VDD _CP
TEST1
VCTR L
VDD_ESD
REXT
ICP
VDD1
1n 22p 10P
4.7K
VDD1
2.2K
8.2K 1n 22p 10µ
270p 68p
loop filter 2.7n
to microcontroller
Note: 1 See Chapter 8: Application information for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly
on the board.
3 Loop filter values are for FSTEP = 200 kHz.
4 For best performance VDD1 must be a low noise supply (20 μVRMS in 10 Hz-100 kHz BW).
47/53
Application diagrams STW81102
ORRSILOWHU
WRPLFURFRQWUROOHU
Q
N
9''B
N
9''B(6'
/2&.B'(7
QSM
9&75/
,&3
5(;7
9''B&3
7(67
9''B 7(67
9''B9&2% Q
287%8)1 9''B3//
287%8)3
67:
'HYLFH /RFNHGDW)UHT ) (;79&2B,11
2XWSXW%XIIHU&RQWURO0RGHHQDEOHG
9''
9''B287%8) (;79&2B,13
QSM QSM
9''B',9 9''B%8)9&2
$''/2$'
6'$'$7$
6&/&/.
(;7B3'
9''B9&2$ '%86B6(/ 63,
$''
$''
9''B
9'' 9''B'%86
,&
UHIFON
5)2XW QSM
9''B
2XWSXW%XIIHU
PLFURFRQWUROOHU +:&RQWURO
9''B
QSM
9''
9''B (;7B3' ,&
$''
$''
$''/2$'
9''B'%86
6'$'$7$
6&/&/.
9''B9&2% Q
7(67
7(67
9&75/
5(;7
9''B(6'
9''B
,&3
QSM
N
N
9''B
S S
QSM
Q
ORRSILOWHU WRPLFURFRQWUROOHU
Note: 1 See Chapter 8: Application information for further information on output matching topology.
2 EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly
on the board.
3 Loop filter values are for FSTEP = 200 kHz.
4 For best performance VDD1_1 and VDD1_2 must be low noise supplies (20 μVRMS in 10 Hz-
100 kHz BW).
48/53
STW81102 Application diagrams
Figure 38. Application diagram with external VCO (LO output from STW81102)
)URPWR PLFURFRQWUROOHU
QSM
9''
9''B'%86
,&
$''/2$'
(;7B3'
6&/&/.
$''
$''
6'$'$7$
9''B9&2$ '%86B6(/ 63,
9''B',9 9''B%8)9&2
9''
QSM
9''
9''B287%8) (;79&2B,13
/22XW
287%8)3 67: (;79&2B,11
287
9&75/
9'' UHIFON
9''B',9 5()B&/.
/2&.B'(7
Q
9''B9&2% 7(67
9''B&3
9''
7(67
9&75/
9''B(6'
5(;7
,&3
&
5
5
QSM &
N
9''
&
QSM
WR PLFURFRQWUROOHU
ORRSILOWHU
Note: See Chapter 8: Application information for further information on output matching topology.
Figure 39. Application diagram with external VCO (LO output from VCO)
)URPWR PLFURFRQWUROOHU
QSM
9'' /22XW
9''B'%86
,&
$''/2$'
(;7B3'
6&/&/.
$''
$''
6'$'$7$
9''B287%8) (;79&2B,13
UHIFON
9''B',9 5()B&/.
/2&.B'(7
Q
9''B9&2% 7(67
9''B&3
7(67
9&75/
9''B(6'
5(;7
,&3
&
5
5
&
N
9''
&
QSM
WR PLFURFRQWUROOHU
ORRSILOWHU
49/53
Package mechanical data STW81102
Note: 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.
(Very thin: A=1.00 Max)
2 Details of the terminal 1 identifier are optional, but if given, must be located on the top
surface of the package by using either a mold or marked features.
50/53
STW81102 Package mechanical data
51/53
Ordering information STW81102
11 Ordering information
12 Revision history
52/53
STW81102
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
53/53