MPC 5565 PDF

Freescale Semiconductor
Data Sheet: Technical Data

Contents
Freescale Semiconductor, Inc., 2008. All rights reserved.
Document Number: MPC5565
Rev. 2.0, 11/2008
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5565
microcontroller device. For functional characteristics,
refer to the MPC5565 Microcontroller Reference
Manual.
1 Overview
The MPC5565 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architecture embedded technology. This
family of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original Power PC user instruction set
architecture (UISA). The embedded architecture
enhancements improve the performance in embedded
applications. The core also has additional instructions,
including digital signal processing (DSP) instructions,
beyond the original Power PC instruction set.
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 VRC and POR Electrical Specifications . . . . . . . . . 9
3.7 Power-Up/Down Sequencing. . . . . . . . . . . . . . . . . 10
3.8 DC Electrical Specifications . . . . . . . . . . . . . . . . . 13
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 MPC5565 324 PBGA Pinouts . . . . . . . . . . . . . . . . 46
4.2 MPC5565 324-Pin Package Dimensions. . . . . . . . 47
5 Revision History for the MPC5565 Data Sheet . . . . . . . 49
5.1 Changes to Revision 1.0 in Revision 2.0. . . . . . . . 49
5.2 Changes to Revision 0.0 in Revision 1.0. . . . . . . . 52
MPC5565
Microcontroller Data Sheet
by: Microcontroller Division
MPC5565 Microcontroller Data Sheet, Rev. 2.0
Overview
Freescale Semiconductor 2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The host processor core of the MPC5565 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The MPC5565 has two levels of memory hierarchy. The fastest accesses are to the 8-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 80-KB on-chip internal SRAM and
two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5565 are performed by an enhanced time processor
unit (eTPU) engine. The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is
programmed using a high-level programming language.
The less complex timer functions of the MPC5565 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 324 package
has 40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
Ordering Information
2 Ordering Information
Figure 1. MPC5500 Family Part Number Example
Unless noted in this data sheet, all specifications apply from T
L
to T
H
.
Table 1. Orderable Part Numbers
Freescale Part Number
1
1
All devices are PPC5565, rather than MPC5565 or SPC5565, until product qualifications are complete. Not all configurations are
available in the PPC parts.
Package Description
Speed (MHz) Operating Temperature
2
2
The lowest ambient operating temperature is referenced by T
L
; the highest ambient operating temperature is referenced by T
H
.
Nominal Max.
3
(f
MAX
)
3
Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and
135 MHz parts allow for 132 MHz system clock + 2% FM.
Min. (T
L
) Max. (T
H
)
MPC5565MVZ132
MPC5565 324 package
Lead-free (PbFree)
132 135
40 C 125 C MPC5565MVZ112 112 114
MPC5565MVZ80 80 82
MPC5565MZQ132
MPC5565 324 package
Leaded (SnPb)
132 135
40 C 125 C MPC5565MZQ112 112 114
MPC5565MZQ80 80 82
M PC M 80 R
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = 40 C to 125 C
Package Identifier
ZQ = 324PBGA SnPb
VZ = 324PBGA Pb-free
Operating Frequency
80 = 80 MHz
112 = 112 MHz
132 = 132 MHz
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
5565 ZQ
Note: Not all options are available on all devices. Refer to Table 1.
Electrical Characteristics
3 Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1 Maximum Ratings
Table 2. Absolute Maximum Ratings
1

Spec Characteristic Symbol Min. Max. Unit
1 1.5 V core supply voltage
2
V
DD
0.3 1.7 V
2 Flash program/erase voltage V
PP
0.3 6.5 V
4 Flash read voltage V
FLASH
0.3 4.6 V
5 SRAM standby voltage V
STBY
0.3 1.7 V
6 Clock synthesizer voltage V
DDSYN
0.3 4.6 V
7 3.3 V I/O buffer voltage V
DD33
0.3 4.6 V
8 Voltage regulator control input voltage V
RC33
0.3 4.6 V
9 Analog supply voltage (reference to V
SSA
) V
DDA
0.3 5.5 V
10 I/O supply voltage (fast I/O pads)
3
V
DDE
0.3 4.6 V
11 I/O supply voltage (slow and medium I/O pads)
3
V
DDEH
0.3 6.5 V
12 DC input voltage
4
V
DDEH
powered I/O pads
V
DDE
powered I/O pads
V
IN
1.0
5
1.0
5
6.5
6
4.6
7
V
13 Analog reference high voltage (reference to V
RL
) V
RH
0.3 5.5 V
14 V
SS
to V
SSA
differential voltage V
SS
V
SSA
0.1 0.1 V
15 V
DD
to V
DDA
DD
V
DDA
V
DDA
V
DD
V
16 V
REF
RH
V
RL
0.3 5.5 V
17 V
RH
to V
DDA
RH
V
DDA
5.5 5.5 V
18 V
RL
to V
SSA
RL
V
SSA
0.3 0.3 V
19 V
DDEH
to V
DDA
DDEH
V
DDA
V
DDA
V
DDEH
V
20 V
DDF
to V
DD
DDF
V
DD
0.3 0.3 V
21 V
RC33
to V
DDSYN
differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a.
22 V
SSSYN
to V
SS
SSSYN
V
SS
0.1 0.1 V
23 V
RCVSS
to V
SS
RCVSS
V
SS
0.1 0.1 V
24 Maximum DC digital input current
8

(per pin, applies to all digital pins)
4
I
MAXD
2 2 mA
25 Maximum DC analog input current
9

(per pin, applies to all analog pins)
I
MAXA
3 3 mA
26 Maximum operating temperature range
10

Die junction temperature
T
J
T
L
150.0
o
C
27 Storage temperature range T
STG
55.0 150.0
o
C
3.2 Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer board.
28 Maximum solder temperature
11
Lead free (Pb-free)
Leaded (SnPb)
T
SDR
260.0
245.0
o
C
29 Moisture sensitivity level
12
MSL 3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability
or cause permanent damage to the device.
2
1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150
o
C.
3
All functional non-supply I/O pins are clamped to V
SS
and V
DDE
, or V
DDEH
.
4
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
5
Internal structures hold the voltage greater than 1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
voltage greater than 0.6 V on SINB during the internal power-on reset (POR) state.
6
Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDEH
supplies, if the
maximum injection current specification is met (2 mA for all pins) and V
DDEH
is within the operating voltage specifications.
7
Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
DDE
supplies, if the maximum
injection current specification is met (2 mA for all pins) and V
DDE
is within the operating voltage specifications.
8
Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
9
Total injection current for all analog input pins must not exceed 15 mA.
10
Lifetime operation at these specification limits is not guaranteed.
11
Moisture sensitivity profile per IPC/JEDEC J-STD-020D.
12
Moisture sensitivity per JEDEC test method A112.
Table 3. MPC5565 Thermal Characteristics
Spec MPC5565 Thermal Characteristic Symbol 324 PBGA Unit
1 Junction to ambient
1, 2
, natural convection (one-layer board)
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
R
JA
29 C/W
2 Junction to ambient
1, 3
, natural convection (four-layer board 2s2p)
3
Per JEDEC JESD51-6 with the board horizontal.
R
JA
19 C/W
3 Junction to ambient (@200 ft./min., one-layer board) R
JMA
23 C/W
4 Junction to ambient (@200 ft./min., four-layer board 2s2p) R
JMA
16 C/W
5 Junction to board
4
(four-layer board 2s2p)
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
R
JB
10 C/W
6 Junction to case
5
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
R
JC
7 C/W
7 Junction to package top
6
, natural convection
6
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
JT
2 C/W
Table 2. Absolute Maximum Ratings
1
(continued)
3.2.1 General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, T
J
, can be obtained from the equation:
T
J
=T
A
+(R
J A
P
D
)
where:
T
A
=ambient temperature for the package (
o
C)
R
J A
=junction to ambient thermal resistance (
o
C/W)
P
D
=power dissipation in the package (W)
The thermal resistance values used are based on the J EDEC J ESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm
2
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T
J
=T
B
+(R
J B
P
D
)
where:
T
J
=junction temperature (
o
C)
T
B
=board temperature at the package perimeter (
o
C/W)
R
J B
=junction-to-board thermal resistance (
o
C/W) per J ESD51-8
P
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
R
J A
=R
J C
+R
CA
where:
R
J A
=junction-to-ambient thermal resistance (
o
C/W)
R
J C
=junction-to-case thermal resistance (
o
C/W)
R
CA
=case-to-ambient thermal resistance (
o
C/W)
R
J C
is device related and is not affected by other factors. The thermal environment can be controlled to
change the case-to-ambient thermal resistance, R
CA
. For example, change the air flow around the device,
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter (
J T
) to determine the junction temperature by measuring the
temperature at the top center of the package case using the following equation:
T
J
=T
T
+(
J T
P
D
)
where:
T
T
=thermocouple temperature on top of the package (
o
C)
J T
=thermal characterization parameter (
o
C/W)
P
D
The thermal characterization parameter is measured in compliance with the J ESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Rd.
San J ose, CA., 95134
(408) 943-6900
MIL-SPEC and EIA/J ESD (J EDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
J EDEC specifications are available on the web at http://www.jedec.org.
1. C.E. Triplett and B. J oiner, An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp. 4754.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applica-
tions, Electronic Packaging and Production, pp. 5358, March 1998.
3. B. J oiner and V. Adams, Measurement and Simulation of J unction to Board Thermal Resistance and
Its Application in Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212220.
3.3 Package
The MPC5565 is available in packaged form. Read the package options in Section2, Ordering
Information. Refer to Section4, Mechanicals, for pinouts and package drawings.
3.4 EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications
1
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
Spec Characteristic Minimum Typical Maximum Unit
1 Scan range 0.15 1000 MHz
2 Operating frequency f
MAX
MHz
3 V
DD
operating voltages 1.5 V
4 V
DDSYN
, V
RC33
, V
DD33
, V
FLASH
, V
DDE
5 V
PP
, V
DDEH
, V
DDA
6 Maximum amplitude 14
2
32
3
2
Measured with the single-chip EMI program.
3
Measured with the expanded EMI program.
dBuV
7 Operating temperature 25
o
C
3.5 ESD (Electromagnetic Static Discharge) Characteristics
3.6 Voltage Regulator Controller (V
RC
) and
Power-On Reset (POR) Electrical Specifications
The following table lists the V
RC
and POR electrical specifications:
Table 5. ESD Ratings
1,

2
1
All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
Device failure is defined as: If after exposure to ESD pulses, the device does not meet the device specification requirements,
which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Characteristic Symbol Value Unit
ESD for human body model (HBM) 2000 V
HBM circuit description
R1 1500
C 100 pF
ESD for field induced charge model (FDCM)
500 (all pins)
V
750 (corner pins)
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)

1
1
Interval of pulses 1 second

Table 6. V
RC
and POR Electrical Specifications
Spec Characteristic Symbol Min. Max. Units
1 1.5 V (V
DD
) POR
1
Negated (ramp up)
Asserted (ramp down)
V
POR15
1.1
1.1
1.35
1.35
V
2 3.3 V (V
DDSYN
) POR
1
Asserted (ramp up)
Negated (ramp up)
Negated (ramp down)
V
POR33
0.0
2.0
2.0
0.0
0.30
2.85
2.85
0.30
V
3
RESET pin supply
(V
DDEH6
) POR
1, 2
Negated (ramp up)

V
POR5
2.0
2.0
2.85
2.85
V
4
V
RC33
voltage
Before V
RC
allows the pass
transistor to start turning on
V
TRANS_START
1.0 2.0 V
5
When V
RC
allows the pass
transistor to completely turn on
3,

4
V
TRANS_ON
2.0 2.85 V
6
When the voltage is greater than
the voltage at which the V
RC
keeps
the 1.5 V supply in regulation
5, 6
V
VRC33REG
3.0 V
Current can be sourced 40
o
C 11.0 mA
7 by V
RCCTL
at Tj: 25
o
C I
VRCCTL
7
9.0 mA
150
o
C 7.5 mA
8
Voltage differential during power up such that:
V
DD33
can lag V
DDSYN
or V
DDEH6
before V
DDSYN
and V
DDEH6
reach the
V
POR33
and V
POR5
minimums respectively.
V
DD33_LAG
1.0 V
3.7 Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and V
DDSYN
or the RESET power supplies is required
if using an external 1.5 V power supply with V
RC33
tied to ground (GND). To avoid power-sequencing,
V
RC33
must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section3.7.2, Power-Up Sequence (VRC33 Grounded), and
Section3.7.3, Power-Down Sequence (VRC33 Grounded).
Power sequencing requires that V
DD33
must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section3.7.1, Input Value of Pins During POR Dependent on
VDD33.
Although power sequencing is not required between V
RC33
and V
DDSYN
during power up, V
RC33
must
not lead V
DDSYN
by more than 600 mV or lag by more than 100 mV for the V
RC
stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if V
RC33
leads or lags
V
DDSYN
by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by V
RC33
. If V
RC33
lags V
DDSYN
by more than 100 mV, the increase in current
consumed can drop V
DD
low enough to assert the 1.5 V POR again. Oscillations are possible when the
1.5V POR asserts and stops the system clock, causing the voltage on V
DD
to rise until the 1.5V POR
negates again. All oscillations stop when V
RC33
is powered sufficiently.
9 Absolute value of slew rate on power supply pins 50 V/ms
10
Required gain at Tj:
I
DD
I
VRCCTL
(@ f
sys
= f
MAX
)
6, 7, 8, 9
40
o
C
BETA
10
40
25
o
C 45
150
o
C 55 500
1
The internal POR signals are V
POR15
, V
POR33
, and V
POR5
. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
2
V
IL_S
(Table 9, Spec15) is guaranteed to scale with V
DDEH6
down to V
POR5
.
3
Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
4
It is possible to reach the current limit during ramp updo not treat this event as short circuit current.
5
At peak current for device.
6
Requires compliance with Freescales recommended board requirements and transistor recommendations. Board signal
traces/routing from the V
RCCTL
package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the V
DD
package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 ). V
RCCTL
must have a nominal 1 F phase compensation capacitor to ground. V
DD
must have a 20 F (nominal)
bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the V
DD
supply signals.
7
I
VRCCTL
is measured at the following conditions: V
DD
= 1.35 V, V
RC33
= 3.1 V, V
VRCCTL
= 2.2 V.
8
Refer to Table 1 for the maximum operating frequency.
9
Values are based on I
DD
from high-use applications as explained in the I
DD
Electrical Specification.
10
BETA is the worst-case external transistor BETA. It is measured on a per-part basis and calculated as (I
DD
I
VRCCTL
).
Table 6. V
RC
and POR Electrical Specifications (continued)
Spec Characteristic Symbol Min. Max. Units
When powering down, V
RC33
and V
DDSYN
have no delta requirement to each other, because the bypass
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between V
RC33
and V
DDSYN
is required for the V
RC
to operate within specification.
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
The values in Table7 and Table8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the
internal POR negates, the functional state of the signal during reset applies and the weak-pull devices
(up or down) are enabled as defined in the device reference manual. If V
DD
is too low to correctly
propagate the logic signals, the weak-pull devices can pull the signals to V
DDE
and V
DDEH
.
To avoid this condition, minimize the ramp time of the V
DD
supply to a time period less than the time
required to enable the external circuitry connected to the device outputs.
Table 7. Pin Status for Fast Pads During the Power Sequence
V
DDE
V
DD33
V
DD
POR
Pin Status for Fast Pad Output Driver
pad_fc (fast)
Low Asserted Low
V
DDE
Low Low Asserted High
V
DDE
Low V
DD
Asserted High
V
DDE
V
DD33
Low Asserted High impedance (Hi-Z)
V
DDE
V
DD33
V
DD
Asserted Hi-Z
V
DDE
V
DD33
V
DD
Negated Functional
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
V
DDEH
V
DD
POR
Pin Status for Medium and Slow Pad Output Driver
pad_mh (medium) pad_sh (slow)
Low Asserted Low
V
DDEH
Low Asserted High impedance (Hi-Z)
V
DDEH
V
DD
Asserted Hi-Z
V
DDEH
V
DD
Negated Functional
3.7.1 Input Value of Pins During POR Dependent on V
DD33
When powering up the device, V
DD33
must not lag the latest V
DDSYN
or RESET power pin (V
DDEH6
) by
more than the V
DD33
lag specification listed in Table6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V
DD33
can lag V
DDSYN
or the RESET power
pin (V
DDEH6
), but cannot lag both by more than the V
DD33
lag specification. This V
DD33
lag specification
applies during power up only. V
DD33
has no lead or lag requirements when powering down.
3.7.2 Power-Up Sequence (V
RC33
Grounded)
The 1.5V V
DD
power supply must rise to 1.35V before the 3.3V V
DDSYN
power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5V power supply does
not begin to operate below the specified operation range lower limit of 1.35V. Because the internal 1.5V
POR is disabled, the internal 3.3V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0V, V
DD
must be within specification before the 3.3V POR and the RESET
POR negate.
Figure 2. Power-Up Sequence (V
RC33
Grounded)
3.7.3 Power-Down Sequence (V
RC33
Grounded)
The only requirement for the power-down sequence with V
RC33
grounded is if V
DD
decreases to less than
its operating range, V
DDSYN
or the RESET power must decrease to less than 2.0V before the V
DD
power
increases to its operating range. This ensures that the digital 1.5V logic, which is reset only by an ORed
POR and can cause the 1.5V supply to decrease less than its specification value, resets correctly. See
Table6, footnote 1.
V
DDSYN
and RESET Power
V
DD
2.0 V
1.35 V
V
DD
must reach 1.35 V before V
DDSYN
and the RESET power reach 2.0 V
3.8 DC Electrical Specifications
Table 9. DC Electrical Specifications (T
A
= T
L
to T
H
)
Spec Characteristic Symbol Min Max. Unit
1 Core supply voltage (average DC RMS voltage) V
DD
1.35 1.65 V
2 Input/output supply voltage (fast input/output)
1
V
DDE
1.62 3.6 V
3 Input/output supply voltage (slow and medium input/output) V
DDEH
3.0 5.25 V
4 3.3 V input/output buffer voltage V
DD33
3.0 3.6 V
5 Voltage regulator control input voltage V
RC33
3.0 3.6 V
6 Analog supply voltage
2
V
DDA
4.5 5.25 V
8 Flash programming voltage
3
V
PP
4.5 5.25 V
9 Flash read voltage V
FLASH
3.0 3.6 V
10 SRAM standby voltage
4
V
STBY
0.8 1.2 V
11 Clock synthesizer operating voltage V
DDSYN
3.0 3.6 V
12 Fast I/O input high voltage V
IH_F
0.65 V
DDE
V
DDE
+ 0.3 V
13 Fast I/O input low voltage V
IL_F
V
SS
0.3 0.35 V
DDE
V
14 Medium and slow I/O input high voltage V
IH_S
0.65 V
DDEH
V
DDEH
+ 0.3 V
15 Medium and slow I/O input low voltage V
IL_S
V
SS
0.3 0.35 V
DDEH
V
16 Fast input hysteresis V
HYS_F
0.1 V
DDE
V
17 Medium and slow I/O input hysteresis V
HYS_S
0.1 V
DDEH
V
18 Analog input voltage V
INDC
V
SSA
0.3 V
DDA
+ 0.3 V
19 Fast output high voltage ( I
OH_F
= 2.0 mA ) V
OH_F
0.8 V
DDE
V
20 Slow and medium output high voltage
I
OH_S
= 2.0 mA
I
OH_S
= 1.0 mA
V
OH_S
0.80 V
DDEH
0.85 V
DDEH
V
21 Fast output low voltage ( I
OL_F
= 2.0 mA ) V
OL_F
0.2 V
DDE
V
22 Slow and medium output low voltage
I
OL_S
= 2.0 mA
I
OL_S
= 1.0 mA
V
OL_S
0.20 V
DDEH
0.15 V
DDEH
V
23 Load capacitance (fast I/O)
5

DSC (SIU_PCR[8:9] ) = 0b00
= 0b01
= 0b10
= 0b11
C
L
10
20
30
50
pF
pF
pF
pF
24 Input capacitance (digital pins) C
IN
7 pF
25 Input capacitance (analog pins) C
IN_A
10 pF
26 Input capacitance:
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
C
IN_M
12 pF
27a Operating current 1.5 V supplies @ 135 MHz:
6
V
DD
(including V
DDF
max current) @1.65 V typical use
7, 8
V
DD
(including V
DDF
7, 8
V
DD
(including V
DDF
max current) @1.65 V high use
8, 9

V
DD
(including V
DDF
8, 9
I
DD
I
DD
I
DD
I
DD
460
10
360
10
510
10
410
10
mA
mA
mA
mA
27b Operating current 1.5 V supplies @ 114 MHz:
6
V
DD
(including V
DDF
max current)@1.65 V typical use
7, 8
V
DD
(including V
DDF
max current)

@1.35 V typical use
7, 8
V
DD
(including V
DDF
8, 9
V
DD
(including V
DDF
8, 9
I
DD
I
DD
I
DD
I
DD
410
10
310
10
460
10
370
10
mA
mA
mA
mA
27c Operating current 1.5 V supplies @ 82 MHz:
6
V
DD
(including V
DDF
7, 8
V
DD
(including V
DDF
7, 8
V
DD
(including V
DDF
8, 9
V
DD
(including V
DDF
8, 9
I
DD
I
DD
I
DD
I
DD
330
10
225
10
385
10
290
10
mA
mA
mA
mA
27d Refer to Figure 3 for an interpolation of this data.
11
I
DD_STBY
@ 25
o
C
V
STBY
@ 0.8 V
V
STBY
@ 1.0 V
V
STBY
@ 1.2 V
I
DD_STBY
@ 60
o
C
V
STBY
@ 0.8 V
V
STBY
@ 1.0 V
V
STBY
@ 1.2 V
I
DD_STBY
@ 150
o
C (Tj)
V
STBY
@ 0.8 V
V
STBY
@ 1.0 V
V
STBY
@ 1.2 V
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
I
DD_STBY
20
30
50
70
100
200
1200
1500
2000
A
A
A
A
A
A
A
A
A
28 Operating current 3.3 V supplies @ f
MAX
MHz
V
DD33
12
I
DD_33
2 + (values
derived from
procedure of
footnote
12
)
mA
V
FLASH
I
VFLASH
10 mA
V
DDSYN
I
DDSYN
15 mA
29 Operating current 5.0 V supplies (12 MHz ADCLK):
V
DDA
(V
DDA0
+ V
DDA1
)
Analog reference supply current (V
RH
, V
RL
)
V
PP
I
DD_A
I
REF
I
PP
20.0
1.0
25.0
mA
mA
mA
A
= T
L
to T
H
) (continued)
30 Operating current V
DDE
supplies:
13
V
DDEH1
V
DDE2
V
DDE3
V
DDEH4
V
DDE5
V
DDEH6
V
DDE7
V
DDEH8
V
DDEH9
I
DD1
I
DD2
I
DD3
I
DD4
I
DD5
I
DD6
I
DD7
I
DD8
I
DD9
Refer to
Footnote
13
mA
mA
mA
mA
mA
mA
mA
mA
mA
31 Fast I/O weak pullup current
14
1.621.98 V
2.252.75 V
3.003.60 V
I
ACT_F
10
20
20
110
130
170
A
A
A
Fast I/O weak pulldown current
14
1.621.98 V
2.252.75 V
3.003.60 V
10
20
20
100
130
170
A
A
A
32 Slow and medium I/O weak pullup/down current
14
3.03.6 V
4.55.5 V
I
ACT_S
10
20
150
170
A
A
33 I/O input leakage current
15
I
INACT_D
2.5 2.5 A
34 DC injection current (per pin) I
IC
2.0 2.0 mA
35 Analog input current, channel off
16
I
INACT_A
150 150 nA
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15])
I
INACT_AD
2.5 2.5 A
36 V
SS
to V
SSA
differential voltage
17
V
SS
V
SSA
100 100 mV
37 Analog reference low voltage V
RL
V
SSA
0.1 V
SSA
+ 0.1 V
38 V
RL
RL
V
SSA
100 100 mV
39 Analog reference high voltage V
RH
V
DDA
0.1 V
DDA
+ 0.1 V
40 V
REF
RH
V
RL
4.5 5.25 V
41 V
SSSYN
to V
SS
SSSYN
V
SS
50 50 mV
42 V
RCVSS
to V
SS
RCVSS
V
SS
50 50 mV
43 V
DDF
to V
DD
DDF
V
DD
100 100 mV
43a V
RC33
to V
DDSYN
RC33
V
DDSYN
0.1 0.1
18
V
44 Analog input differential signal range (with common mode 2.5 V) V
IDIFF
2.5 2.5 V
45 Operating temperature range, ambient (packaged) T
A
= (T
L
to T
H
) T
L
T
H
C
46 Slew rate on power-supply pins 50 V/ms
1
V
DDE2
and V
DDE3
are limited to 2.253.6 V only if SIU_ECCR[EBTS] = 0; V
DDE2
and V
DDE3
have a range of 1.63.6 V if
SIU_ECCR[EBTS] = 1.
A
= T
L
to T
H
) (continued)
2
| V
DDA0
V
DDA1
| must be < 0.1 V.
3
V
PP
can drop to 3.0 V during read operations.
4
If standby operation is not required, connect V
STBY
to ground.
5
Applies to CLKOUT, external bus pins, and Nexus pins.
6
Maximum average RMS DC current.
7
Average current measured on automotive benchmark.
8
Peak currents can be higher on specialized code.
9
High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents can occur if an idle loop that crosses cache lines is run from cache.
Design and write code to avoid this condition.
10
Final values listed in specs 27a 27c are based on characterization.
11
Figure 3 shows an illustration of the I
DD_STBY
values interpolated for these temperature values.
12
Power requirements for the V
DD33
supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Table 11 for values to calculate the power dissipation for a specific operation.
13
Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
14
Absolute value of current, measured at V
IL
and V
IH
.
15
Weak pullup/down inactive. Measured at V
DDE
= 3.6 V and V
DDEH
= 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
16
Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8
o
C
to 12
o
C, in the ambient temperature range of 50
o
C to 125
o
C. Applies to pad types: pad_a and pad_ae.
17
V
SSA
refers to both V
SSA0
and V
SSA1
. | V
SSA0
V
SSA1
| must be < 0.1 V.
18
Up to 0.6 V during power up and power down.
Figure3 shows an approximate interpolation of the I
STBY
worst-case specification to estimate values at
different voltages and temperatures. The vertical lines shown at 25
C, 60
C, and 150
C in Figure3 are
the actual I
DD_STBY
specifications (27d) listed in Table9.
Figure 3. I
STBY
Worst-case Specifications
Ist by vs. Junct ion Temp
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Temp (C)
u
A
0.8V
1.0V
1.2V
A
3.8.1 I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a segment. The output pin current can be
calculated from Table10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table10.
Table 10. I/O Pad Average DC Current (T
A
= T
L
to T
H
)
1

1
These values are estimates from simulation and are not tested. Currents apply to output pins only.
Spec Pad Type Symbol
Frequency
(MHz)
Load
2
(pF)
2
All loads are lumped.
Voltage (V)
Drive Select /
Slew Rate
Control Setting
Current (mA)
1
Slow I
DRV_SH
25 50 5.25 11 8.0
2 10 50 5.25 01 3.2
3 2 50 5.25 00 0.7
4 2 200 5.25 00 2.4
5
Medium I
DRV_MH
50 50 5.25 11 17.3
6 20 50 5.25 01 6.5
7 3.33 50 5.25 00 1.1
8 3.33 200 5.25 00 3.9
9
Fast I
DRV_FC
66 10 3.6 00 2.8
10 66 20 3.6 01 5.2
11 66 30 3.6 10 8.5
12 66 50 3.6 11 11.0
13 66 10 1.98 00 1.6
14 66 20 1.98 01 2.9
15 66 30 1.98 10 4.2
16 66 50 1.98 11 6.7
17 56 10 3.6 00 2.4
18 56 20 3.6 01 4.4
19 56 30 3.6 10 7.2
20 56 50 3.6 11 9.3
21 56 10 1.98 00 1.3
22 56 20 1.98 01 2.5
23 56 30 1.98 10 3.5
24 56 50 1.98 11 5.7
25 40 10 3.6 00 1.7
26 40 20 3.6 01 3.1
27 40 30 3.6 10 5.1
28 40 50 3.6 11 6.6
29 40 10 1.98 00 1.0
30 40 20 1.98 01 1.8
31 40 30 1.98 10 2.5
32 40 50 1.98 11 4.0
3.8.2 I/O Pad V
DD33
Current Specifications
The power consumption of the V
DD33
supply dependents on the usage of the pins on all I/O segments. The
power consumption is the sum of all input and output pin V
DD33
currents for all I/O segments. The output
pin V
DD33
current can be calculated from Table11 based on the voltage, frequency, and load on all fast
(pad_fc) pins. The input pin V
DD33
current can be calculated from Table11 based on the voltage,
frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table11.
Table 11. V
DD33
Pad Average DC Current (T
A
= T
L
to T
H
)
1

1
These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
Spec Pad Type Symbol
Frequency
(MHz)
Load
2
(pF)
2
All loads are lumped.
V
DD33

(V)
V
DDE
(V)
Drive
Select
Current
(mA)
Inputs
1 Slow I
33_SH
66 0.5 3.6 5.5 NA 0.003
2 Medium I
33_MH
66 0.5 3.6 5.5 NA 0.003
Outputs
3
Fast I
33_FC
66 10 3.6 3.6 00 0.35
4 66 20 3.6 3.6 01 0.53
5 66 30 3.6 3.6 10 0.62
6 66 50 3.6 3.6 11 0.79
7 66 10 3.6 1.98 00 0.35
8 66 20 3.6 1.98 01 0.44
9 66 30 3.6 1.98 10 0.53
10 66 50 3.6 1.98 11 0.70
11 56 10 3.6 3.6 00 0.30
12 56 20 3.6 3.6 01 0.45
13 56 30 3.6 3.6 10 0.52
14 56 50 3.6 3.6 11 0.67
15 56 10 3.6 1.98 00 0.30
16 56 20 3.6 1.98 01 0.37
17 56 30 3.6 1.98 10 0.45
18 56 50 3.6 1.98 11 0.60
19 40 10 3.6 3.6 00 0.21
20 40 20 3.6 3.6 01 0.31
21 40 30 3.6 3.6 10 0.37
22 40 50 3.6 3.6 11 0.48
23 40 10 3.6 1.98 00 0.21
24 40 20 3.6 1.98 01 0.27
25 40 30 3.6 1.98 10 0.32
26 40 50 3.6 1.98 11 0.42
3.9 Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(V
DDSYN
= 3.03.6 V; V
SS
= V
SSSYN
= 0.0 V; T
A
= T
L
to T
H
)
Spec Characteristic Symbol Minimum Maximum Unit
1
PLL reference frequency range:
1
Crystal reference
2
External reference
2
Dual controller (1:1 mode)
f
ref_crystal

f
ref_ext

f
ref_1:1

8
8
24
20
20
f
sys
2
MHz
2 System frequency
3
f
sys
f
ICO(MIN)
2
RFD
f
MAX

4
MHz
3 System clock period t
CYC
1 f
sys
ns
4 Loss of reference frequency
5
f
LOR
100 1000 kHz
5 Self-clocked mode (SCM) frequency
6
f
SCM
7.4 17.5 MHz
6
EXTAL input high voltage crystal mode
7
All other modes
[dual controller (1:1), bypass, external reference]
V
IHEXT

V
IHEXT
V
XTAL
+ 0.4 V
(V
DDE5
2) + 0.4 V
V
V
7
EXTAL input low voltage crystal mode
8
All other modes
[dual controller (1:1), bypass, external reference]
V
ILEXT

V
ILEXT

V
XTAL
0.4 V
(V
DDE5
2) 0.4 V
V
V
8 XTAL current
9
I
XTAL
2 6 mA
9 Total on-chip stray capacitance on XTAL C
S_XTAL
1.5 pF
10 Total on-chip stray capacitance on EXTAL C
S_EXTAL
1.5 pF
11
Crystal manufacturers recommended capacitive
load
C
L
Refer to crystal
specification
Refer to crystal
specification
pF
12
Discrete load capacitance to connect to EXTAL C
L_EXTAL
(2 C
L
)

C
S_EXTAL
C
PCB_EXTAL
10
pF
13
Discrete load capacitance to connect to XTAL C
L_XTAL
(2 C
L
)

C
S_XTAL

C
PCB_XTAL
10
pF
14 PLL lock time
11
t
lpll
750 s
15
Dual controller (1:1) clock skew
(between CLKOUT and EXTAL)
12, 13
t
skew
2 2 ns
16 Duty cycle of reference

t
DC
40 60 %
17 Frequency unLOCK range f
UL
4.0 4.0 % f
SYS
18 Frequency LOCK range f
LCK
2.0 2.0 % f
SYS
19
CLKOUT period jitter,

measured at f
SYS
max:
14, 15
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
C
JITTER

5.0
0.01
%
f
CLKOUT
20
Frequency modulation range limit
16
(do not exceed f
sys
maximum)
C
MOD
0.8 2.4
%f
SYS
21
ICO frequency
f
ico
= [ f
ref_crystal
(MFD + 4) ] (PREDIV + 1)
17
f
ico
= [ f
ref_ext
(MFD + 4) ] (PREDIV + 1)
f
ico
48 f
MAX
MHz
22 Predivider output frequency (to PLL) f
PREDIV
4 20
18
MHz
1
Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2
The 820 MHz crystal or external reference values have PLLCFG[2] pulled low. PLLCFG[2] is not supported pulled high.
3
All internal registers retain data at 0 Hz.
4
Up to the maximum frequency rating of the device (refer to Table 1).
5
Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
6
The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f
LOR
. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
7
Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (V
extal
V
xtal
) must be 400 mV for the oscillators comparator to produce the output clock.
8
Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (V
xtal
V
extal
) must be 400 mV for the oscillators comparator to produce the output clock.
9
I
xtal
is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
10
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
11
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
12
PLL is operating in 1:1 PLL mode.
13
V
DDE
= 3.03.6 V.
14
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
DDSYN
and V
SSSYN
and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider is set to divide-by-two.
15
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod).
16
Modulation depth selected must not result in f
sys
value greater than the f
sys
maximum specified value.
17
f
sys
= f
ico
(2
RFD
).
18
Maximum value for dual controller (1:1) mode is (f
MAX
2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).
Table 12. FMPLL Electrical Specifications (continued)
(V
DDSYN
= 3.03.6 V; V
SS
= V
SSSYN
= 0.0 V; T
A
= T
L
to T
H
)
3.10 eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (T
A
= T
L
to T
H
)
1 ADC clock (ADCLK) frequency
1
1
Conversion characteristics vary with F
ADCLK
rate. Reduced conversion accuracy occurs at maximum F
ADCLK
rate. The
maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a
maximum 16 factor.
F
ADCLK
1 12 MHz
2
Conversion cycles
Differential
Single ended
CC
13 + 2 (15)
14 + 2 (16)
13 + 128 (141)
14 + 128 (142)
ADCLK
cycles
3 Stop mode recovery time
2
2
Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform
conversions.
T
SR
10 s
4 Resolution
3
3
At V
RH
V
RL
= 5.12 V, one least significant bit (LSB) = 1.25, mV = one count.
1.25 mV
5 INL: 6 MHz ADC clock INL6 4 4 Counts
3
6 INL: 12 MHz ADC clock INL12 8 8 Counts
7 DNL: 6 MHz ADC clock DNL6 3
4
4
Guaranteed 10-bit mono tonicity.
3
4
Counts
8 DNL: 12 MHz ADC clock DNL12 6
4
6
4
Counts
9 Offset error with calibration OFFWC 4
5
5
The absolute value of the offset error without calibration 100 counts.
4
5
Counts
10 Full-scale gain error with calibration GAINWC 8
6
6
The absolute value of the full scale gain error without calibration 120 counts.
8
6
Counts
11 Disruptive input injection current
7, 8, 9, 10
7
Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than
V
RH
, and 0x000 for values less than V
RL
. This assumes that V
RH
V
DDA
and V
RL
V
SSA
due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8
Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not
affect device reliability or cause permanent damage.
9
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using V
POSCLAMP
= V
DDA
+ 0.5 V and V
NEGCLAMP
= 0.3 V, then use the larger of the calculated values.
10
This condition applies to two adjacent pads on the internal pad.
I
INJ
1 1 mA
12
Incremental error due to injection current. All channels are
10 k < Rs <100 k
Channel under test has Rs = 10 k,
I
INJ
= I
INJMAX
, I
INJMIN
E
INJ
4 4 Counts
13
Total unadjusted error (TUE) for single ended conversions
with calibration
11, 12,

13, 14, 15
11
The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12
TUE does not apply to differential conversions.
13
Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: 16 counts < TUE < 16 counts.
14
TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref).
15
Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can
affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15].
TUE 4 4 Counts
3.11 H7Fa Flash Memory Electrical Characteristics
Table 14. Flash Program and Erase Specifications (T
A
= T
L
to T
H
)
Spec Flash Program Characteristic Symbol Min. Typical
1
1
Typical program and erase times are calculated at 25
o
C operating temperature using nominal supply values.
Initial
Max.
2
2
Initial factory condition: 100 program/erase cycles, 25
o
C, using a typical supply voltage measured at a minimum system
frequency of 80 MHz.
Max.
3
3
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
Unit
3 Doubleword (64 bits) program time
4
4
Actual hardware programming times. This does not include software overhead.
T
dwprogram
10 500 s
4 Page program time
4
T
pprogram
22 44
5
5
Page size is 256 bits (8 words).
500 s
7 16 KB block pre-program and erase time T
16kpperase
265 400 5000 ms
48kpperase
345 400 5000 ms
64kpperase
415 500 5000 ms
128kpperase
500 1250 7500 ms
11
Minimum operating frequency for program and erase
operations
6
6
The read frequency of the flash can range up to the maximum operating frequency. There is no minimum read frequency
condition.
25 MHz
Table 15. Flash EEPROM Module Life (T
A
= T
L
to T
H
)
Spec Characteristic Symbol Min. Typical
1
1
Typical endurance is evaluated at 25
o
C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for
Nonvolatile Memory.
Unit
1a
Number of program/erase cycles per block for 16 KB, 48 KB, and
64 KB blocks over the operating temperature range (T
J
)
P/E 100,000 cycles
1b
Number of program/erase cycles per block for 128 KB blocks over the
operating temperature range (T
J
)
P/E 1000 100,000 cycles
2
Data retention
Blocks with 01,000 P/E cycles
Blocks with 1,001100,000 P/E cycles
Retention
20
5
years
Table16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference
manual for definitions of these bit fields.
3.12 AC Specifications
3.12.1 Pad AC Specifications

Table 16. FLASH_BIU Settings vs. Frequency of Operation
1
1
Illegal combinations exist. Use entries from the same row in this table.
Maximum Frequency (MHz) APC RWSC WWSC DPFEN
2
2
For maximum flash performance, set to 0b11.
IPFEN
2
PFLIM
3
3
BFEN
4
4
Up to and including 82 MHz
5
5
82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
0b001 0b001 0b01 0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
6
6
0b001 0b010 0b01 0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
7
7
0b010 0b011 0b01 0b00
0b01
0b11
0b00
0b01
0b11
0b000
to
0b110
0b0
0b1
Default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0
Table 17. Pad AC Specifications (V
DDEH
= 5.0 V, V
DDE
= 1.8 V)
1
Spec Pad
SRC / DSC
(binary)
Out Delay
2, 3, 4

(ns)
Rise / Fall
4, 5

(ns)
Load Drive
(pF)
1 Slow high voltage (SH)
11
26 15 50
82 60 200
01
75 40 50
137 80 200
00
377 200 50
476 260 200
2 Medium high voltage (MH)
11
16 8 50
43 30 200
01
34 15 50
61 35 200
00
192 100 50
239 125 200

3 Fast
00
3.1
2.7 10
01 2.5 20
10 2.4 30
11 2.3 50
4 Pullup/down (3.6 V max) 7500 50
1
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
V
DD
= 1.351.65 V; V
DDE
= 1.621.98 V; V
DDEH
= 4.55.25 V; V
DD33
and V
DDSYN
= 3.03.6 V; and T
A
= T
L
to T
H
.
2
This parameter is supplied for reference and is guaranteed by design (not tested).
3
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock,
add a maximum of one system clock to the output delay.
4
The output delay and rise and fall are measured to 20% or 80% of the respective signal.
5
This parameter is guaranteed by characterization rather than 100% tested.
Table 18. Derated Pad AC Specifications (V
DDEH
= 3.3 V, V
DDE
= 3.3 V)
1
1
These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at:
V
DD
= 1.351.65 V; V
DDE
= 3.03.6 V; V
DDEH
= 3.03.6 V; V
DD33
and V
DDSYN
= 3.03.6 V; and T
A
= T
L
to T
H
.
Spec Pad
SRC/DSC
(binary)
Out Delay
2,

3, 4
(ns)
2
This parameter is supplied for reference and guaranteed by design (not tested).
Rise / Fall
3, 5
(ns)
Load Drive
(pF)
1 Slow high voltage (SH)
11
39 23 50
120 87 200
01
101 52 50
188 111 200
00
507 248 50
597 312 200
2 Medium high voltage (MH)
11
23 12 50
64 44 200
01
50 22 50
90 50 200
00
261 123 50
305 156 200
3 Fast
00
3.2
2.4 10
01 2.2 20
10 2.1 30
11 2.1 50
Table 17. Pad AC Specifications (V
DDEH
= 5.0 V, V
DDE
= 1.8 V)
1
(continued)
Spec Pad
SRC / DSC
(binary)
Out Delay
2, 3, 4

(ns)
Rise / Fall
4, 5

(ns)
Load Drive
(pF)
Figure 4. Pad Output Delay
3.13 AC Timing
3.13.1 Reset and Configuration Pin Timing
3
The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal.
4
The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one
system clock to the output delay.
5
This parameter is guaranteed by characterization rather than 100% tested.
Table 19. Reset and Configuration Pin Timing
1
1
Reset timing specified at: V
DDEH
= 3.05.25 V and T
A
= T
L
to T
H
.
1 RESET pulse width t
RPW
10 t
CYC
2 RESET glitch detect pulse width t
GPW
2 t
CYC
3 PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid t
RCSU
10 t
CYC
4 PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid t
RCH
0 t
CYC
V
DD
2
V
OH
V
OL
Rising-edge
out delay
Falling-edge
Pad
internal data
Pad
output
out delay
input signal
Figure 5. Reset and Configuration Pin Timing
3.13.2 IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics
1

1
These specifications apply to JTAG boundary scan only. JTAG timing specified at: V
DDE
= 3.03.6 V and T
A
= T
L
to T
H
.
Refer to Table 21 for Nexus specifications.
1 TCK cycle time t
JCYC
100 ns
2 TCK clock pulse width (measured at V
DDE
2) t
JDC
40 60 ns
3 TCK rise and fall times (40% to 70%) t
TCKRISE
3 ns
4 TMS, TDI data setup time t
TMSS,
t
TDIS
5 ns
5 TMS, TDI data hold time t
TMSH,
t
TDIH
25 ns
6 TCK low to TDO data valid t
TDOV
20 ns
7 TCK low to TDO data invalid t
TDOI
0 ns
8 TCK low to TDO high impedance t
TDOHZ
20 ns
9 JCOMP assertion time t
JCMPPW
100 ns
10 JCOMP setup time to TCK low t
JCMPS
40 ns
11 TCK falling-edge to output valid t
BSDV
50 ns
12 TCK falling-edge to output valid out of high impedance t
BSDVZ
50 ns
13 TCK falling-edge to output high impedance (Hi-Z) t
BSDHZ
50 ns
14 Boundary scan input valid to TCK rising-edge t
BSDST
50 ns
15 TCK rising-edge to boundary scan input invalid t
BSDHT
50 ns
1
2
RESET
RSTOUT
WKPCFG
PLLCFG
3
4
BOOTCFG
RSTCFG
Figure 6. JTAG Test Clock Input Timing
Figure 7. JTAG Test Access Port Timing
TCK
1
2
2
3
3
TCK
4
5
6
7 8
TMS, TDI
TDO
Figure 8. JTAG JCOMP Timing
TCK
JCOMP
9
10
Figure 9. JTAG Boundary Scan Timing
TCK
Output
signals
Input
signals
Output
signals
11
12
13
14
15
3.13.3 Nexus Timing
Figure 10. Nexus Output Timing
Table 21. Nexus Debug Port Timing
1

1
JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of
MCKO and 50% of the respective signal. Nexus timing specified at V
DD
= 1.351.65 V, V
DDE
= 2.253.6 V,
V
DD33
and V
DDSYN
= 3.03.6 V, T
A
= T
L
to T
H
, and CL = 30 pF with DSC = 0b10.
1 MCKO cycle time t
MCYC
1
2
2
The Nexus AUX port runs up to 82 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency
is greater than 82 MHz.
8 t
CYC
2 MCKO duty cycle t
MDC
40 60 %
3 MCKO low to MDO data valid
3
3
MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs.
t
MDOV
1.5 3.0 ns
4 MCKO low to MSEO data valid
3
t
MSEOV
1.5 3.0 ns
5 MCKO low to EVTO data valid
3
t
EVTOV
1.5 3.0 ns
6 EVTI pulse width t
EVTIPW
4.0 t
TCYC
7 EVTO pulse width t
EVTOPW
1 t
MCYC
8 TCK cycle time t
TCYC
4
4
4
Limit the maximum frequency to approximately 16 MHz (V
DDE
= 2.253.0 V) or 20 MHz (V
DDE
= 3.03.6 V) to meet the timing
specification for t
JOV
of [0.2 x t
JCYC
] as outlined in the IEEE-ISTO 5001-2003 specification.
t
CYC
9 TCK duty cycle t
TDC
40 60 %
10 TDI, TMS data setup time t
NTDIS,
t
NTMSS
8 ns
11 TDI, TMS data hold time t
NTDIH,
t
NTMSH
5 ns
12
TCK low to TDO data valid t
JOV
V
DDE
= 2.253.0 V 0 12 ns
V
DDE
= 3.03.6 V 0 10 ns
13 RDY valid to MCKO
5
5
The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly.

1
2
3 4
5
MCKO
MDO
MSEO
EVTO
Output Data Valid
Figure 11. Nexus TDI, TMS, TDO Timing
TDO
10
11
TMS, TDI
12
TCK
3.13.4 External Bus Interface (EBI) Timing
Table22 lists the timing information for the external bus interface (EBI).
Table 22. Bus Operation Timing
1

Spec
Characteristic
and
Description
Symbol
External Bus Frequency
2,

3
Unit Notes
40 MHz 56 MHz 66 MHz
Min. Max. Min. Max. Min. Max.
1 CLKOUT period T
C
24.4 17.5 14.9 ns
Signals are measured
at 50% V
DDE
.
2 CLKOUT duty cycle t
CDC
45% 55% 45% 55% 45% 55% T
C
3 CLKOUT rise time t
CRT

4

4

4
ns
4 CLKOUT fall time t
CFT

4

4

4
ns
5
CLKOUT positive edge to output
signal invalid or Hi-Z (hold time)
External bus interface
CS[0:3]
ADDR[8:31]
DATA[0:31]
5
BDIP
OE
RD_WR
TA
TEA
6
TS
WE/BE[0:3]
7
t
COH
1.0
8
1.5
1.0
8
1.5
1.0
8

1.5
ns
EBTS = 0
EBTS = 1
Hold time selectable
via SIU_ECCR
[EBTS] bit.
signal invalid or Hi-Z (hold time)
Calibration bus interface
CAL_CS[0, 2:3]
CAL_ADDR[10:30]
CAL_DATA[0:15]
CAL_OE
CAL_RD_WR
CAL_TS
CAL_WE/BE[0:1]
t
CCOH
1.0
8
1.5
1.0
8
1.5
1.0
8

1.5
ns
EBTS = 0
EBTS = 1
Hold time selectable
via SIU_ECCR
[EBTS] bit.
6
signal valid (output delay)
CS[0:3]
ADDR[8:31]
DATA[0:31]
5
BDIP
OE
RD_WR
TA
TEA
6
TS
WE/BE[0:3]
7
t
COV
10.0
8

11.0
7.5
8

8.5
6.0
8

7.0
ns
EBTS = 0
EBTS = 1
Output valid time
selectable via
SIU_ECCR
[EBTS] bit.
6a
signal valid (output delay)
CAL_CS[0, 2:3]
CAL_ADDR[10:30]
CAL_DATA[0:15]
CAL_OE
CAL_RD_WR
CAL_TS
CAL_WE/BE[0:1]
t
CCOV
11.0
8

12.0
8.5
8

9.5
7.0
8

8.0
ns EBTS = 0
EBTS = 1
Output valid time
selectable via
SIU_ECCR
[EBTS] bit.
7
Input signal valid to CLKOUT
positive edge (setup time)
ADDR[8:31]
DATA[0:31]
5
RD_WR
TA
TEA
6
TS
t
CIS
10.0 7.0 5.0 ns
Input signal valid to CLKOUT
positive edge (setup time)
CAL_ADDR[10:30]
CAL_DATA[0:15]
CAL_RD_WR
CAL_TS
t
CCIS
11.0 8.0 6.0 ns
1
(continued)
Spec
Characteristic
and
Description
Symbol
2,

3
Unit Notes
Figure 12. CLKOUT Timing
8
CLKOUT positive edge to input
signal invalid (hold time)
ADDR[8:31]
DATA[0:31]
5
RD_WR
TA
TEA
6
TS
t
CIH
1.0 1.0 1.0 ns
CLKOUT positive edge to input
signal invalid (hold time)
CAL_ADDR[10:30]
CAL_DATA[0:15]
CAL_RD_WR
CAL_TS
t
CCIH
1.0 1.0 1.0 ns
1
EBI timing specified at: V
DDE
= 1.63.6 V (unless stated otherwise); T
A
= T
L
to T
H
; and CL = 30 pF with DSC = 0b10.
2
3
The external bus is limited to half the speed of the internal bus.
4
Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V).
5
Due to pin limitations, the DATA[16:31] signals are not available on the 324 package.
6
Due to pin limitations, the TEA signal is not available on the 324 package.
7
Due to pin limitations, the WE/BE[2:3] signals are not available on the 324 package.
8
SIU_ECCR[EBTS] = 0 timings are tested and valid at V
DDE
= 2.253.6 V only; SIU_ECCR[EBTS] = 1 timings are tested and
valid at V
DDE
= 1.63.6 V.
1
(continued)
Spec
Characteristic
and
Description
Symbol
2,

3
Unit Notes
1
2
2
3
4
CLKOUT
V
DDE
2
Vol_f
Voh_f
Figure 13. Synchronous Output Timing
6
5
5
CLKOUT
bus
5
Output
signal
Output
V
DDE
2
V
DDE
2
V
DDE
2
V
DDE
2
6
5
Output
signal
V
DDE
2
6
Figure 14. Synchronous Input Timing
3.13.5 External Interrupt Timing (IRQ Signals)
Table 23. External Interrupt Timing
1
1
IRQ timing specified at: V
DDEH
= 3.05.25 V and T
A
= T
L
to T
H
.
1 IRQ pulse-width low t
IPWL
3 t
CYC
2 IRQ pulse-width high T
IPWH
3 t
CYC
3 IRQ edge-to-edge time
2
2
Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both.
t
ICYC
6 t
CYC
7
8
CLKOUT
Input
bus
7
8
Input
signal
V
DDE
2
V
DDE
2
V
DDE
2
Figure 15. External Interrupt Timing
3.13.6 eTPU Timing
Figure 16. eTPU Timing
Table 24. eTPU Timing
1
1
eTPU timing specified at: V
DDEH
= 3.05.25 V and T
A
= T
L
to T
H
.
Spec Characteristic Symbol Min. Max Unit
1 eTPU input channel pulse width t
ICPW
4 t
CYC
2 eTPU output channel pulse width t
OCPW
2
2
2
This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
t
CYC
IRQ
1 2
3
1
2
eTPU
output
eTPU input
and TCRCLK
3.13.7 eMIOS Timing
Figure 17. eMIOS Timing
3.13.8 DSPI Timing
Table 25. eMIOS Timing
1
1
eMIOS timing specified at: V
DDEH
= 3.05.25 V and T
A
= T
L
to T
H
.
1 eMIOS input pulse width t
MIPW
4 t
CYC
2 eMIOS output pulse width t
MOPW
1
2
2
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).
t
CYC
Table 26. DSPI Timing
1

2
Spec Characteristic Symbol
Unit
1 SCK cycle time
3, 4
t
SCK
24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms
2 PCS to SCK delay
5
t
CSC
23 15 13 ns
3 After SCK delay
6
t
ASC
22 14 12 ns
4
SCK duty cycle
t
SDC
(t
SCK
2)
2 ns
(t
SCK
2)
+ 2 ns
(t
SCK
2)
2 ns
(t
SCK
2)
+ 2 ns
(t
SCK
2)
2 ns
(t
SCK
2)
+ 2 ns
ns
5
Slave access time
(SS active to SOUT driven)
t
A
25 25 25 ns
6
Slave SOUT disable time
(SS inactive to SOUT Hi-Z, or invalid)
t
DIS
25 25 25 ns
7 PCSx to PCSS time t
PCSC
4 4 4 ns
8 PCSS to PCSx time t
PASC
5 5 5 ns
1
2
eMIOS
output
eMIOS input
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
7
t
SUI
20
2
4
20
20
2
3
20
20
2
6
20
ns
ns
ns
ns
10
Data hold time for inputs
Master (MTFE = 0)
Slave
7
t
HI
4
7
21
4

4
7
14
4

4
7
12
4

ns
ns
ns
ns
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
t
SUO
5
25
18
5
5
25
14
5
5
25
13
5
ns
ns
ns
ns
12
Data hold time for outputs
Master (MTFE = 0)
Slave
t
HO
5
5.5
8
5
5
5.5
4
5
5
5.5
3
5
ns
ns
ns
ns
1
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types
of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: V
DDEH
= 3.05.25 V;T
A
= T
L
to T
H
;
and CL = 50 pF with SRC = 0b11.
2
3
The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4
The actual minimum SCK cycle time is limited by pad performance.
5
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7
This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
Table 26. DSPI Timing
1

2
(continued)
Spec Characteristic Symbol
Unit
Figure 18. DSPI Classic SPI TimingMaster, CPHA = 0
Figure 19. DSPI Classic SPI TimingMaster, CPHA = 1
Data Last data First data
First data Data Last data
SIN
SOUT
PCSx
SCK output
4
9
12
1
11
10
4
SCK output
(CPOL=0)
(CPOL=1)
3 2
Data
Last data First data SIN
SOUT
12
11
10
Last data Data
First data
SCK output
SCK output
PCSx
9
(CPOL=0)
(CPOL=1)
Figure 20. DSPI Classic SPI TimingSlave, CPHA = 0
Figure 21. DSPI Classic SPI TimingSlave, CPHA = 1
Last data First data
3
4
1
Data
Data
SIN
SOUT
SS
4
5
6
9
11
10
12
SCK input
First data Last data
SCK input
2
(CPOL=0)
(CPOL=1)
5
6
9
12
11
10
Last data
Last data SIN
SOUT
SS
First data
First data
Data
Data
SCK input
SCK input
(CPOL=0)
(CPOL=1)
Figure 22. DSPI Modified Transfer Format TimingMaster, CPHA = 0
Figure 23. DSPI Modified Transfer Format TimingMaster, CPHA = 1
PCSx
3
1
4
10
4
9
12
11
SCK output
SCK output
SIN
SOUT
2
(CPOL=0)
(CPOL=1)
PCSx
10
9
12 11
SCK output
SCK output
SIN
SOUT
(CPOL=0)
(CPOL=1)
Figure 24. DSPI Modified Transfer Format TimingSlave, CPHA = 0
Figure 25. DSPI Modified Transfer Format TimingSlave, CPHA = 1
Figure 26. DSPI PCS Strobe (PCSS) Timing
Last data First data
3
4
1
Data
Data
SIN
SOUT
SS
4
5
6
9
11
10
SCK input
First data Last data
SCK input
2
(CPOL=0)
(CPOL=1)
12
5
6
9
12
11
10
Last data
Last data SIN
SOUT
SS
First data
First data
Data
Data
SCK input
SCK input
(CPOL=0)
(CPOL=1)
PCSx
7
8
PCSS
3.13.9 eQADC SSI Timing
Figure 27. EQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics
Spec Rating Symbol Minimum Typical Maximum Unit
2 FCK period (t
FCK
= 1 f
FCK
)
1, 2
1
SS timing specified at V
DDEH
= 3.05.25 V, T
A
= T
L
to T
H
, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
2
FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
t
FCK
2 17 t
SYS_CLK
3 Clock (FCK) high time t
FCKHT
t
SYS_CLK
6.5 9 (t
SYS_CLK
+ 6.5) ns
4 Clock (FCK) low time t
FCKLT
t
SYS_CLK
6.5 8 (t
SYS_CLK
+ 6.5) ns
5 SDS lead / lag time t
SDS_LL
7.5 +7.5 ns
6 SDO lead / lag time t
SDO_LL
7.5 +7.5 ns
7 EQADC data setup time (inputs) t
EQ_SU
22 ns
8 EQADC data hold time (inputs) t
EQ_HO
1 ns
1st (MSB) 2nd
25th
26th
1st (MSB) 2nd 25th 26th
8
7
5 6
4 5
4
2
3
FCK
SDS
SDO
External device data sample at
SDI
EQADC data sample at
FCK falling-edge
FCK rising-edge
Mechanicals
4 Mechanicals
4.1 MPC5565 324 PBGA Pinouts
Figure28 is a pinout for the MPC5565 324 PBGA package.
NOTE
The MPC5500 devices are pin compatible for software portability and use
the primary function names to label the pins in the BGA diagram. Although
some devices do not support all the primary functions shown in the BGA
diagram, the muxed and GPIO signals on those pins remain available. See
the signals chapter in the device reference manual for the signal muxing.
Figure 28. MPC5565 324 Package
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AN28 VDD VSTBY AN37 AN11 VDDA1 AN1 AN5 VRH VRL AN27 AN35 VSSA0 MDO10 MDO8 VDD VDD33 VSS A
VDD33 AN31 VSS VDD AN36 AN39 AN19 AN0 AN23 AN26 AN32 VSSA0 MDO9 MDO7 MDO4 MDO0 VSS VDDE7 B
AN30 VSS VDD AN8 AN17 AN21 AN3 AN7 AN22 AN25 AN33 VDDA0 AN14 MDO5 MDO2 MDO1 VSS VDDE7 VDD C
AN29 VSS VDD AN38 AN10 AN18 AN2 AN6 AN24 AN15 MDO6 VSS VDDE7 TCK TDI D
VDDE7 TMS TDO TEST E
VDDE7 J COMP EVTI EVTO F
RDY G
VSS VSS VSS VSS VSS VDDE7
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
SINB H
VSS VDDE2 VDDE2 VSS VSS VSS
SOUTB PCSB3 PCSB0 PCSB1 J
VSS VSS VSS VDDE2 VSS VSS
PCSA3 PCSB4 SCKB PCSB2 K
VSS VSS VSS VDDE2 VSS VSS
PCSB5 SOUTA SINA SCKA L
BDIP CS1 CS0 PCSA1 PCSA0 PCSA2 VPP M
CS2 WE1 WE0 PCSA4 TXDA PCSA5 VFLASH N
RD_WR CNTXC RXDA RSTOUT P
RXDB
CNRXC TXDB RESET R
TS T
EXTAL U
VDDE2
VDD XTAL V
VSS VDD VDDE2 VDDE5 NC VSS VDD VRC33 W
VSS VDD CNTXA VDDE5 NC VSS VDD VDD33 Y
VSS VDD CNRXA VDDE5 CLKOUT VSS VDD AA
VSS VDD
VDDE2 VDDE2
CNTXB CNRXB VDDE5 VSS AB
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AN9
AN20
AN16
VSSA1
ETPUA
28
ETPUA
29
ETPUA
25
ETPUA
24
ETPUA
27
ETPUA
23
ETPUA
22
ETPUA
17
ETPUA
20
ETPUA
19
ETPUA
14
ETPUA
13
ETPUA
16
ETPUA
15
ETPUA
10
VDDEH
1
ETPUA
6
GPIO
204
GPIO
203
VDDEH
10
ADDR
16
ADDR
17
ADDR
18
ADDR
19
ADDR
20
ADDR
21
ADDR
12
ADDR
22
ADDR
23
ADDR
13
ADDR
25
ADDR
31
ADDR
15
ADDR
26
ADDR
24
ADDR
30
ADDR
28
ADDR
27
ADDR
29
DATA
0
DATA
1
DATA
8
DATA
3
DATA
9
DATA
4
DATA
13
GPIO
206
DATA
5
DATA
10
DATA
11
DATA
12
DATA
14
DATA
15
DATA
7
EMIOS
6
EMIOS
2
EMIOS
10
EMIOS
15
VDDEH
4
EMIOS
12
EMIOS
17
EMIOS
16
EMIOS
14
EMIOS
22
EMIOS
19
EMIOS
18
EMIOS
23
EMIOS
20
EMIOS
21
BOOT
CFG1
VDDEH
6
PLL
CFG1
BOOT
CFG0
WKP
CFG
VSS
SYN
VRC
CTL
PLL
CFG0
VDD
SYN
RST
CFG
ENG
CLK
Note: No connect. Reserved (W18 & Y19 are shorted to each other) NC
W
Y
AA
AB
MDO11 AN12
AN4
REF
BYPC
AN13
ETPUA
30
ETPUA
31
ETPUA
26
ETPUA
21
ETPUA
18
AN34
VDDEH
9
MDO3
ETPUA
11
ETPUA
12
ETPUA
2
ETPUA
7
ETPUA
8
ETPUA
0
TCRCLK
A
ETPUA
3
ETPUA
4
ETPUA
9
ETPUA
5
ETPUA
1
MCKO MSEO0 MSEO1
CS3
VDD33
TA VDDE2
ADDR
14
VDDE2 VDD33
EMIOS
8
VDDE2
VDDE2
VDDE2
GPIO
207
DATA
2
DATA
6
EMIOS
13
EMIOS
9
EMIOS
5
EMIOS
3
OE
EMIOS
11
EMIOS
7
EMIOS
4
EMIOS
1
EMIOS
0
PLL
CFG2
Mechanicals
4.2 MPC5565 324-Pin Package Dimensions
The package drawings of the MPC5565 324-pin TEPBGA package are shown in Figure29.
Figure 29. MPC5565 324 TEPBGA Package
Mechanicals
Figure 29. MPC5565 324 TEPBGA Package (continued)

Revision History for the MPC5565 Data Sheet
5 Revision History for the MPC5565 Data Sheet
The history of revisions made to this data sheet are shown in this section. The changes are divided into
each revision of this document. The substantive changes incorporated in MPC5565 Data Sheet Rev. 1.0 to
produce Rev. 2.0 of this document are grouped as follows:
Global and text changes
Table and figure changes
Within each group, the changes are listed in sequential order.
5.1 Changes to Revision 1.0 in Revision 2.0
The following table lists the substantive text changes made to paragraphs.
Table 28. Text Changes Between Rev. 1.0 and 2.0
Location Description of Changes
Throughout:
Changed T
A
= T
L
T
H
to T
A
= T
L
to T
H
.
Title page:
Changed the Revision number from 1.0 to 2.0. Made the same changes in the lower left corner of the back page.
Section 1, Overview
Fourth paragraph, First sentence: Deleted of the MPC5500 family; Second to last sentence: Deleted can.
Fifth paragraph, First sentence: Replaced MPC5500 family with MPC5565; Last sentence: Replaced can be
with is.
Sixth paragraph, First sentence: Replaced MPC5500 family with MPC5565;
Second to last paragraph: Rewrote to read: The MCU has an on-chip enhanced queued dual analog-to-digital
converter (eQADC) The 324 package has 40-channels.
Section 3.1, Maximum Ratings:
Changed title from Maximum Rating to Maximum Ratings.
Section 3.2.1, General Notes for Specifications at Maximum Junction Temperature
Updated the address of Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
Section 3.7, Power-Up/Down Sequencing
Last paragraph: Changed the first sentence FROM , , , the voltage on the pins goes to high-impedance until . . .
TO. . .the pins go to a high-impedance state until . . .
Section 3.7.3, Power-Down Sequence (VRC33 Grounded)
Last sentence: Changed from: This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and
can cause the 1.5 V supply to decrease below its specification, is reset properly.
To: This ensures that the digital 1.5 V logic, which is reset only by an ORed POR and can cause the 1.5 V supply
to decrease less than its specification, resets correctly.
The following table lists the information that changed in the tables between Rev. 1.0 and 2.0.
Section 4.1, MPC5565 324 PBGA Pinouts
Added the following NOTE before the 324 BGA Map:
NOTE
The MPC5500 devices are pin compatible for software portability and use the primary
function names to label the pins in the BGA diagram. Although some devices do not support
all the primary functions shown in the BGA diagram, the muxed and GPIO signals on those
pins remain available. See the signals chapter in the device reference manual for the signal
muxing.
Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0
Table 2 Absolute Maximum Ratings:
Added footnote 7 to Spec 12 Internal structures hold the input voltage less than the maximum voltage on all pads
powered by V
DDE
supplies, if the maximum injection current specification is met (2 mA for all pins) and V
DDE
is
within the operating voltage specifications.
Table 4 EMI Testing Specifications:
Table Title: Footnote 1: Deleted the last sentence: The values in this specification reflect EMI performance with
frequency modulation (FM) turned off. For better EMI performance, enable FM.
Table 5 ESD Ratings:
Changed footnote 2 from:
Device failure is defined as: If after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete DC parametric and functional testing will be performed per applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
to:
Device failure is defined as: If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.
Table 6 VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are V
POR15
, V
POR33
, and V
POR5
.
On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power
supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
Reformatted columns.
Table 9 DC Electrical Specifications:
Added (T
A
= T
L
to T
H
) to the table title.
Added footnote that reads: V
DDE2
and V
DDE3
are limited to 2.253.6 V only if SIU_ECCR[EBTS] = 0; V
DDE2
and
V
DDE3
have a range of 1.63.6 V if SIU_ECCR[EBTS] =1.
Table 28. Text Changes Between Rev. 1.0 and 2.0 (continued)
Table 17 Pad AC Specifications:
Footnote 1, Changed V
DDEH
= 4.55.5; to V
DDEH
= 4.55.25;
Footnote 3, Changed from Out delay. . . to The output delay. . .,
Changed from Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock to To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.
Footnote 4: Changed Delay to The output delay.
Table 19 Reset and Configuration Pin Timing
Footnote 1: Removed V
DD
=1.351.65.
Table 20 JTAG Pin AC Electrical Characteristics
DD
=1.351.65; and V
DD33
and V
DDSYN
= 3.03.6 V.
Table 22 Bus Operation Timing:
Specifications 5 and 6. Changed EBTS to SIU_ECCR[EBTS].
Specifications 7 and 8: Removed CS[0:3], BDIP, OE, and WE/BE[0:3] because these pins are not used on the
input signal to CLKOUT.
Specification 7: Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on
the input signal to CLKOUT.
Specification 8: Added to the beginning of the calibration section: CLKOUT positive edge to input signal invalid
(hold time). Removed CAL_CS[0, 2:3], CAL_OE, and CAL_WE/BE[0:1] because these pins are not used on the
input signal to CLKOUT.
Footnote 1: Deleted V
DD
= 1.351.65; and V
DD33
and V
DDSYN
= 3.03.6 V.
Added footnote 2: Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed
including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow
for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM.
Added footnotes 5, 6, and 7, one each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin
limitations, the DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.
Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 External Interrupt Timing (IRQ Signals)
DD
= 1.351.65 V; changed V
DDEH
= 3.05.5 V to V
DDEH
= 3.05.25 V.
Table 24 eTPU Timing
Footnote 1: Changed V
DDEH
= 3.05.5 V to V
DDEH
= 3.05.25 V.
Table 25 eMIOS Timing
DDEH
= 3.05.5 V to V
DDEH
= 3.05.25 V.
Table 26 DSPI Timing:
Specification 1: SCK cycle time. Changed 80 MHz column, Min.: from 25 to 24.4; 112 MHz columns, Min.: from
17.9 to 17.5, Max: from 2.0 to 2.1; 132 MHz columns, Min.: from 15.2 to 14.8, Max: from 1.7 to 1.8.
Footnote 1, changed V
DDEH
= 3.05.5 V; to V
DDEH
= 3.05.25 V;
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, 135 MHz parts allow for 132 MHz system clock + 2%
FM.
Table 27 EQADC SSI Timing Characteristics
DDEH
= 3.05.5 V to V
DDEH
= 3.05.25 V.
Table 29. MPC5565 Changes Between Rev. 1.0 and 2.0 (continued)
5.2 Changes to Revision 0.0 in Revision 1.0
The following table lists the information that changed in the tables between Rev. 0.0 and 1.0.
Table 30. MPC5565 Changes Between Rev. 0.0 and 1.0
Table 6 VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before V
POR15
, V
POR33
, and V
POR5

negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies
fall outside the operating conditions and until the internal POR asserts.
Table 9 DC Electrical Specifications:
Added (T
A
= T
L
to T
H
) to the table title.
Table 22 Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts
allow for 132 MHz system clock + 2% FM.
Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
Specs 7 and 8: Removed from external bus interface: BDIP, OE, and WE/BE[0:3].
DD
= 1.351.65 V, and V
DD33
and V
DDSYN
= 3.03.6 V.
Table 25 eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Deleted . . .f
SYS
= 132 MHz. . ., . . .V
DD33
and V
DDSYN
= 3.03.6 V. . . and . . .and CL = 200 pF
with SRC = 0b11.
Added Footnote 2: This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).
Document Number: MPC5565
Rev. 2.0
11/2008
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Typical parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including Typicals, must be validated for each customer application by
customers technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
Freescale Semiconductor, Inc. 2008. All rights reserved.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescales Environmental Products program, go to
http://www.freescale.com/epp.

MPC 5565 PDF

Uploaded by

Copyright:

Available Formats

MPC 5565 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MPC 5565 PDF

Uploaded by

Copyright:

Available Formats

Freescale Semiconductor

Data Sheet: Technical Data

Interval of pulses 1 second

You might also like